1 /* 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Paul Walmsley 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * XXX handle crossbar/shared link difference for L3? 12 * XXX these should be marked initdata for multi-OMAP kernels 13 */ 14 #include <plat/omap_hwmod.h> 15 #include <mach/irqs.h> 16 #include <plat/cpu.h> 17 #include <plat/dma.h> 18 #include <plat/serial.h> 19 #include <plat/i2c.h> 20 #include <plat/gpio.h> 21 #include <plat/mcbsp.h> 22 #include <plat/mcspi.h> 23 #include <plat/dmtimer.h> 24 #include <plat/mmc.h> 25 #include <plat/l3_2xxx.h> 26 27 #include "omap_hwmod_common_data.h" 28 29 #include "prm-regbits-24xx.h" 30 #include "cm-regbits-24xx.h" 31 #include "wd_timer.h" 32 33 /* 34 * OMAP2430 hardware module integration data 35 * 36 * ALl of the data in this section should be autogeneratable from the 37 * TI hardware database or other technical documentation. Data that 38 * is driver-specific or driver-kernel integration-specific belongs 39 * elsewhere. 40 */ 41 42 static struct omap_hwmod omap2430_mpu_hwmod; 43 static struct omap_hwmod omap2430_iva_hwmod; 44 static struct omap_hwmod omap2430_l3_main_hwmod; 45 static struct omap_hwmod omap2430_l4_core_hwmod; 46 static struct omap_hwmod omap2430_dss_core_hwmod; 47 static struct omap_hwmod omap2430_dss_dispc_hwmod; 48 static struct omap_hwmod omap2430_dss_rfbi_hwmod; 49 static struct omap_hwmod omap2430_dss_venc_hwmod; 50 static struct omap_hwmod omap2430_wd_timer2_hwmod; 51 static struct omap_hwmod omap2430_gpio1_hwmod; 52 static struct omap_hwmod omap2430_gpio2_hwmod; 53 static struct omap_hwmod omap2430_gpio3_hwmod; 54 static struct omap_hwmod omap2430_gpio4_hwmod; 55 static struct omap_hwmod omap2430_gpio5_hwmod; 56 static struct omap_hwmod omap2430_dma_system_hwmod; 57 static struct omap_hwmod omap2430_mcbsp1_hwmod; 58 static struct omap_hwmod omap2430_mcbsp2_hwmod; 59 static struct omap_hwmod omap2430_mcbsp3_hwmod; 60 static struct omap_hwmod omap2430_mcbsp4_hwmod; 61 static struct omap_hwmod omap2430_mcbsp5_hwmod; 62 static struct omap_hwmod omap2430_mcspi1_hwmod; 63 static struct omap_hwmod omap2430_mcspi2_hwmod; 64 static struct omap_hwmod omap2430_mcspi3_hwmod; 65 static struct omap_hwmod omap2430_mmc1_hwmod; 66 static struct omap_hwmod omap2430_mmc2_hwmod; 67 68 /* L3 -> L4_CORE interface */ 69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 70 .master = &omap2430_l3_main_hwmod, 71 .slave = &omap2430_l4_core_hwmod, 72 .user = OCP_USER_MPU | OCP_USER_SDMA, 73 }; 74 75 /* MPU -> L3 interface */ 76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { 77 .master = &omap2430_mpu_hwmod, 78 .slave = &omap2430_l3_main_hwmod, 79 .user = OCP_USER_MPU, 80 }; 81 82 /* Slave interfaces on the L3 interconnect */ 83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { 84 &omap2430_mpu__l3_main, 85 }; 86 87 /* DSS -> l3 */ 88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = { 89 .master = &omap2430_dss_core_hwmod, 90 .slave = &omap2430_l3_main_hwmod, 91 .fw = { 92 .omap2 = { 93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 94 .flags = OMAP_FIREWALL_L3, 95 } 96 }, 97 .user = OCP_USER_MPU | OCP_USER_SDMA, 98 }; 99 100 /* Master interfaces on the L3 interconnect */ 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { 102 &omap2430_l3_main__l4_core, 103 }; 104 105 /* L3 */ 106 static struct omap_hwmod omap2430_l3_main_hwmod = { 107 .name = "l3_main", 108 .class = &l3_hwmod_class, 109 .masters = omap2430_l3_main_masters, 110 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), 111 .slaves = omap2430_l3_main_slaves, 112 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), 113 .flags = HWMOD_NO_IDLEST, 114 }; 115 116 static struct omap_hwmod omap2430_l4_wkup_hwmod; 117 static struct omap_hwmod omap2430_uart1_hwmod; 118 static struct omap_hwmod omap2430_uart2_hwmod; 119 static struct omap_hwmod omap2430_uart3_hwmod; 120 static struct omap_hwmod omap2430_i2c1_hwmod; 121 static struct omap_hwmod omap2430_i2c2_hwmod; 122 123 static struct omap_hwmod omap2430_usbhsotg_hwmod; 124 125 /* l3_core -> usbhsotg interface */ 126 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { 127 .master = &omap2430_usbhsotg_hwmod, 128 .slave = &omap2430_l3_main_hwmod, 129 .clk = "core_l3_ck", 130 .user = OCP_USER_MPU, 131 }; 132 133 /* L4 CORE -> I2C1 interface */ 134 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 135 .master = &omap2430_l4_core_hwmod, 136 .slave = &omap2430_i2c1_hwmod, 137 .clk = "i2c1_ick", 138 .addr = omap2_i2c1_addr_space, 139 .user = OCP_USER_MPU | OCP_USER_SDMA, 140 }; 141 142 /* L4 CORE -> I2C2 interface */ 143 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 144 .master = &omap2430_l4_core_hwmod, 145 .slave = &omap2430_i2c2_hwmod, 146 .clk = "i2c2_ick", 147 .addr = omap2_i2c2_addr_space, 148 .user = OCP_USER_MPU | OCP_USER_SDMA, 149 }; 150 151 /* L4_CORE -> L4_WKUP interface */ 152 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { 153 .master = &omap2430_l4_core_hwmod, 154 .slave = &omap2430_l4_wkup_hwmod, 155 .user = OCP_USER_MPU | OCP_USER_SDMA, 156 }; 157 158 /* L4 CORE -> UART1 interface */ 159 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 160 .master = &omap2430_l4_core_hwmod, 161 .slave = &omap2430_uart1_hwmod, 162 .clk = "uart1_ick", 163 .addr = omap2xxx_uart1_addr_space, 164 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 }; 166 167 /* L4 CORE -> UART2 interface */ 168 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 169 .master = &omap2430_l4_core_hwmod, 170 .slave = &omap2430_uart2_hwmod, 171 .clk = "uart2_ick", 172 .addr = omap2xxx_uart2_addr_space, 173 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 }; 175 176 /* L4 PER -> UART3 interface */ 177 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 178 .master = &omap2430_l4_core_hwmod, 179 .slave = &omap2430_uart3_hwmod, 180 .clk = "uart3_ick", 181 .addr = omap2xxx_uart3_addr_space, 182 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 }; 184 185 /* 186 * usbhsotg interface data 187 */ 188 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { 189 { 190 .pa_start = OMAP243X_HS_BASE, 191 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, 192 .flags = ADDR_TYPE_RT 193 }, 194 { } 195 }; 196 197 /* l4_core ->usbhsotg interface */ 198 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 199 .master = &omap2430_l4_core_hwmod, 200 .slave = &omap2430_usbhsotg_hwmod, 201 .clk = "usb_l4_ick", 202 .addr = omap2430_usbhsotg_addrs, 203 .user = OCP_USER_MPU, 204 }; 205 206 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { 207 &omap2430_usbhsotg__l3, 208 }; 209 210 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { 211 &omap2430_l4_core__usbhsotg, 212 }; 213 214 /* L4 CORE -> MMC1 interface */ 215 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 216 .master = &omap2430_l4_core_hwmod, 217 .slave = &omap2430_mmc1_hwmod, 218 .clk = "mmchs1_ick", 219 .addr = omap2430_mmc1_addr_space, 220 .user = OCP_USER_MPU | OCP_USER_SDMA, 221 }; 222 223 /* L4 CORE -> MMC2 interface */ 224 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 225 .master = &omap2430_l4_core_hwmod, 226 .slave = &omap2430_mmc2_hwmod, 227 .clk = "mmchs2_ick", 228 .addr = omap2430_mmc2_addr_space, 229 .user = OCP_USER_MPU | OCP_USER_SDMA, 230 }; 231 232 /* Slave interfaces on the L4_CORE interconnect */ 233 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 234 &omap2430_l3_main__l4_core, 235 }; 236 237 /* Master interfaces on the L4_CORE interconnect */ 238 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { 239 &omap2430_l4_core__l4_wkup, 240 &omap2430_l4_core__mmc1, 241 &omap2430_l4_core__mmc2, 242 }; 243 244 /* L4 CORE */ 245 static struct omap_hwmod omap2430_l4_core_hwmod = { 246 .name = "l4_core", 247 .class = &l4_hwmod_class, 248 .masters = omap2430_l4_core_masters, 249 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), 250 .slaves = omap2430_l4_core_slaves, 251 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), 252 .flags = HWMOD_NO_IDLEST, 253 }; 254 255 /* Slave interfaces on the L4_WKUP interconnect */ 256 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { 257 &omap2430_l4_core__l4_wkup, 258 &omap2_l4_core__uart1, 259 &omap2_l4_core__uart2, 260 &omap2_l4_core__uart3, 261 }; 262 263 /* Master interfaces on the L4_WKUP interconnect */ 264 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { 265 }; 266 267 /* l4 core -> mcspi1 interface */ 268 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { 269 .master = &omap2430_l4_core_hwmod, 270 .slave = &omap2430_mcspi1_hwmod, 271 .clk = "mcspi1_ick", 272 .addr = omap2_mcspi1_addr_space, 273 .user = OCP_USER_MPU | OCP_USER_SDMA, 274 }; 275 276 /* l4 core -> mcspi2 interface */ 277 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { 278 .master = &omap2430_l4_core_hwmod, 279 .slave = &omap2430_mcspi2_hwmod, 280 .clk = "mcspi2_ick", 281 .addr = omap2_mcspi2_addr_space, 282 .user = OCP_USER_MPU | OCP_USER_SDMA, 283 }; 284 285 /* l4 core -> mcspi3 interface */ 286 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 287 .master = &omap2430_l4_core_hwmod, 288 .slave = &omap2430_mcspi3_hwmod, 289 .clk = "mcspi3_ick", 290 .addr = omap2430_mcspi3_addr_space, 291 .user = OCP_USER_MPU | OCP_USER_SDMA, 292 }; 293 294 /* L4 WKUP */ 295 static struct omap_hwmod omap2430_l4_wkup_hwmod = { 296 .name = "l4_wkup", 297 .class = &l4_hwmod_class, 298 .masters = omap2430_l4_wkup_masters, 299 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), 300 .slaves = omap2430_l4_wkup_slaves, 301 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), 302 .flags = HWMOD_NO_IDLEST, 303 }; 304 305 /* Master interfaces on the MPU device */ 306 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { 307 &omap2430_mpu__l3_main, 308 }; 309 310 /* MPU */ 311 static struct omap_hwmod omap2430_mpu_hwmod = { 312 .name = "mpu", 313 .class = &mpu_hwmod_class, 314 .main_clk = "mpu_ck", 315 .masters = omap2430_mpu_masters, 316 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), 317 }; 318 319 /* 320 * IVA2_1 interface data 321 */ 322 323 /* IVA2 <- L3 interface */ 324 static struct omap_hwmod_ocp_if omap2430_l3__iva = { 325 .master = &omap2430_l3_main_hwmod, 326 .slave = &omap2430_iva_hwmod, 327 .clk = "dsp_fck", 328 .user = OCP_USER_MPU | OCP_USER_SDMA, 329 }; 330 331 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { 332 &omap2430_l3__iva, 333 }; 334 335 /* 336 * IVA2 (IVA2) 337 */ 338 339 static struct omap_hwmod omap2430_iva_hwmod = { 340 .name = "iva", 341 .class = &iva_hwmod_class, 342 .masters = omap2430_iva_masters, 343 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), 344 }; 345 346 /* always-on timers dev attribute */ 347 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 348 .timer_capability = OMAP_TIMER_ALWON, 349 }; 350 351 /* pwm timers dev attribute */ 352 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 353 .timer_capability = OMAP_TIMER_HAS_PWM, 354 }; 355 356 /* timer1 */ 357 static struct omap_hwmod omap2430_timer1_hwmod; 358 359 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { 360 { 361 .pa_start = 0x49018000, 362 .pa_end = 0x49018000 + SZ_1K - 1, 363 .flags = ADDR_TYPE_RT 364 }, 365 { } 366 }; 367 368 /* l4_wkup -> timer1 */ 369 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 370 .master = &omap2430_l4_wkup_hwmod, 371 .slave = &omap2430_timer1_hwmod, 372 .clk = "gpt1_ick", 373 .addr = omap2430_timer1_addrs, 374 .user = OCP_USER_MPU | OCP_USER_SDMA, 375 }; 376 377 /* timer1 slave port */ 378 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { 379 &omap2430_l4_wkup__timer1, 380 }; 381 382 /* timer1 hwmod */ 383 static struct omap_hwmod omap2430_timer1_hwmod = { 384 .name = "timer1", 385 .mpu_irqs = omap2_timer1_mpu_irqs, 386 .main_clk = "gpt1_fck", 387 .prcm = { 388 .omap2 = { 389 .prcm_reg_id = 1, 390 .module_bit = OMAP24XX_EN_GPT1_SHIFT, 391 .module_offs = WKUP_MOD, 392 .idlest_reg_id = 1, 393 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, 394 }, 395 }, 396 .dev_attr = &capability_alwon_dev_attr, 397 .slaves = omap2430_timer1_slaves, 398 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), 399 .class = &omap2xxx_timer_hwmod_class, 400 }; 401 402 /* timer2 */ 403 static struct omap_hwmod omap2430_timer2_hwmod; 404 405 /* l4_core -> timer2 */ 406 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { 407 .master = &omap2430_l4_core_hwmod, 408 .slave = &omap2430_timer2_hwmod, 409 .clk = "gpt2_ick", 410 .addr = omap2xxx_timer2_addrs, 411 .user = OCP_USER_MPU | OCP_USER_SDMA, 412 }; 413 414 /* timer2 slave port */ 415 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { 416 &omap2430_l4_core__timer2, 417 }; 418 419 /* timer2 hwmod */ 420 static struct omap_hwmod omap2430_timer2_hwmod = { 421 .name = "timer2", 422 .mpu_irqs = omap2_timer2_mpu_irqs, 423 .main_clk = "gpt2_fck", 424 .prcm = { 425 .omap2 = { 426 .prcm_reg_id = 1, 427 .module_bit = OMAP24XX_EN_GPT2_SHIFT, 428 .module_offs = CORE_MOD, 429 .idlest_reg_id = 1, 430 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 431 }, 432 }, 433 .dev_attr = &capability_alwon_dev_attr, 434 .slaves = omap2430_timer2_slaves, 435 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), 436 .class = &omap2xxx_timer_hwmod_class, 437 }; 438 439 /* timer3 */ 440 static struct omap_hwmod omap2430_timer3_hwmod; 441 442 /* l4_core -> timer3 */ 443 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { 444 .master = &omap2430_l4_core_hwmod, 445 .slave = &omap2430_timer3_hwmod, 446 .clk = "gpt3_ick", 447 .addr = omap2xxx_timer3_addrs, 448 .user = OCP_USER_MPU | OCP_USER_SDMA, 449 }; 450 451 /* timer3 slave port */ 452 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { 453 &omap2430_l4_core__timer3, 454 }; 455 456 /* timer3 hwmod */ 457 static struct omap_hwmod omap2430_timer3_hwmod = { 458 .name = "timer3", 459 .mpu_irqs = omap2_timer3_mpu_irqs, 460 .main_clk = "gpt3_fck", 461 .prcm = { 462 .omap2 = { 463 .prcm_reg_id = 1, 464 .module_bit = OMAP24XX_EN_GPT3_SHIFT, 465 .module_offs = CORE_MOD, 466 .idlest_reg_id = 1, 467 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 468 }, 469 }, 470 .dev_attr = &capability_alwon_dev_attr, 471 .slaves = omap2430_timer3_slaves, 472 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), 473 .class = &omap2xxx_timer_hwmod_class, 474 }; 475 476 /* timer4 */ 477 static struct omap_hwmod omap2430_timer4_hwmod; 478 479 /* l4_core -> timer4 */ 480 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { 481 .master = &omap2430_l4_core_hwmod, 482 .slave = &omap2430_timer4_hwmod, 483 .clk = "gpt4_ick", 484 .addr = omap2xxx_timer4_addrs, 485 .user = OCP_USER_MPU | OCP_USER_SDMA, 486 }; 487 488 /* timer4 slave port */ 489 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { 490 &omap2430_l4_core__timer4, 491 }; 492 493 /* timer4 hwmod */ 494 static struct omap_hwmod omap2430_timer4_hwmod = { 495 .name = "timer4", 496 .mpu_irqs = omap2_timer4_mpu_irqs, 497 .main_clk = "gpt4_fck", 498 .prcm = { 499 .omap2 = { 500 .prcm_reg_id = 1, 501 .module_bit = OMAP24XX_EN_GPT4_SHIFT, 502 .module_offs = CORE_MOD, 503 .idlest_reg_id = 1, 504 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 505 }, 506 }, 507 .dev_attr = &capability_alwon_dev_attr, 508 .slaves = omap2430_timer4_slaves, 509 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), 510 .class = &omap2xxx_timer_hwmod_class, 511 }; 512 513 /* timer5 */ 514 static struct omap_hwmod omap2430_timer5_hwmod; 515 516 /* l4_core -> timer5 */ 517 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { 518 .master = &omap2430_l4_core_hwmod, 519 .slave = &omap2430_timer5_hwmod, 520 .clk = "gpt5_ick", 521 .addr = omap2xxx_timer5_addrs, 522 .user = OCP_USER_MPU | OCP_USER_SDMA, 523 }; 524 525 /* timer5 slave port */ 526 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { 527 &omap2430_l4_core__timer5, 528 }; 529 530 /* timer5 hwmod */ 531 static struct omap_hwmod omap2430_timer5_hwmod = { 532 .name = "timer5", 533 .mpu_irqs = omap2_timer5_mpu_irqs, 534 .main_clk = "gpt5_fck", 535 .prcm = { 536 .omap2 = { 537 .prcm_reg_id = 1, 538 .module_bit = OMAP24XX_EN_GPT5_SHIFT, 539 .module_offs = CORE_MOD, 540 .idlest_reg_id = 1, 541 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 542 }, 543 }, 544 .dev_attr = &capability_alwon_dev_attr, 545 .slaves = omap2430_timer5_slaves, 546 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), 547 .class = &omap2xxx_timer_hwmod_class, 548 }; 549 550 /* timer6 */ 551 static struct omap_hwmod omap2430_timer6_hwmod; 552 553 /* l4_core -> timer6 */ 554 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { 555 .master = &omap2430_l4_core_hwmod, 556 .slave = &omap2430_timer6_hwmod, 557 .clk = "gpt6_ick", 558 .addr = omap2xxx_timer6_addrs, 559 .user = OCP_USER_MPU | OCP_USER_SDMA, 560 }; 561 562 /* timer6 slave port */ 563 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { 564 &omap2430_l4_core__timer6, 565 }; 566 567 /* timer6 hwmod */ 568 static struct omap_hwmod omap2430_timer6_hwmod = { 569 .name = "timer6", 570 .mpu_irqs = omap2_timer6_mpu_irqs, 571 .main_clk = "gpt6_fck", 572 .prcm = { 573 .omap2 = { 574 .prcm_reg_id = 1, 575 .module_bit = OMAP24XX_EN_GPT6_SHIFT, 576 .module_offs = CORE_MOD, 577 .idlest_reg_id = 1, 578 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 579 }, 580 }, 581 .dev_attr = &capability_alwon_dev_attr, 582 .slaves = omap2430_timer6_slaves, 583 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), 584 .class = &omap2xxx_timer_hwmod_class, 585 }; 586 587 /* timer7 */ 588 static struct omap_hwmod omap2430_timer7_hwmod; 589 590 /* l4_core -> timer7 */ 591 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { 592 .master = &omap2430_l4_core_hwmod, 593 .slave = &omap2430_timer7_hwmod, 594 .clk = "gpt7_ick", 595 .addr = omap2xxx_timer7_addrs, 596 .user = OCP_USER_MPU | OCP_USER_SDMA, 597 }; 598 599 /* timer7 slave port */ 600 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { 601 &omap2430_l4_core__timer7, 602 }; 603 604 /* timer7 hwmod */ 605 static struct omap_hwmod omap2430_timer7_hwmod = { 606 .name = "timer7", 607 .mpu_irqs = omap2_timer7_mpu_irqs, 608 .main_clk = "gpt7_fck", 609 .prcm = { 610 .omap2 = { 611 .prcm_reg_id = 1, 612 .module_bit = OMAP24XX_EN_GPT7_SHIFT, 613 .module_offs = CORE_MOD, 614 .idlest_reg_id = 1, 615 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 616 }, 617 }, 618 .dev_attr = &capability_alwon_dev_attr, 619 .slaves = omap2430_timer7_slaves, 620 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), 621 .class = &omap2xxx_timer_hwmod_class, 622 }; 623 624 /* timer8 */ 625 static struct omap_hwmod omap2430_timer8_hwmod; 626 627 /* l4_core -> timer8 */ 628 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { 629 .master = &omap2430_l4_core_hwmod, 630 .slave = &omap2430_timer8_hwmod, 631 .clk = "gpt8_ick", 632 .addr = omap2xxx_timer8_addrs, 633 .user = OCP_USER_MPU | OCP_USER_SDMA, 634 }; 635 636 /* timer8 slave port */ 637 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { 638 &omap2430_l4_core__timer8, 639 }; 640 641 /* timer8 hwmod */ 642 static struct omap_hwmod omap2430_timer8_hwmod = { 643 .name = "timer8", 644 .mpu_irqs = omap2_timer8_mpu_irqs, 645 .main_clk = "gpt8_fck", 646 .prcm = { 647 .omap2 = { 648 .prcm_reg_id = 1, 649 .module_bit = OMAP24XX_EN_GPT8_SHIFT, 650 .module_offs = CORE_MOD, 651 .idlest_reg_id = 1, 652 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 653 }, 654 }, 655 .dev_attr = &capability_alwon_dev_attr, 656 .slaves = omap2430_timer8_slaves, 657 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), 658 .class = &omap2xxx_timer_hwmod_class, 659 }; 660 661 /* timer9 */ 662 static struct omap_hwmod omap2430_timer9_hwmod; 663 664 /* l4_core -> timer9 */ 665 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { 666 .master = &omap2430_l4_core_hwmod, 667 .slave = &omap2430_timer9_hwmod, 668 .clk = "gpt9_ick", 669 .addr = omap2xxx_timer9_addrs, 670 .user = OCP_USER_MPU | OCP_USER_SDMA, 671 }; 672 673 /* timer9 slave port */ 674 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { 675 &omap2430_l4_core__timer9, 676 }; 677 678 /* timer9 hwmod */ 679 static struct omap_hwmod omap2430_timer9_hwmod = { 680 .name = "timer9", 681 .mpu_irqs = omap2_timer9_mpu_irqs, 682 .main_clk = "gpt9_fck", 683 .prcm = { 684 .omap2 = { 685 .prcm_reg_id = 1, 686 .module_bit = OMAP24XX_EN_GPT9_SHIFT, 687 .module_offs = CORE_MOD, 688 .idlest_reg_id = 1, 689 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 690 }, 691 }, 692 .dev_attr = &capability_pwm_dev_attr, 693 .slaves = omap2430_timer9_slaves, 694 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), 695 .class = &omap2xxx_timer_hwmod_class, 696 }; 697 698 /* timer10 */ 699 static struct omap_hwmod omap2430_timer10_hwmod; 700 701 /* l4_core -> timer10 */ 702 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { 703 .master = &omap2430_l4_core_hwmod, 704 .slave = &omap2430_timer10_hwmod, 705 .clk = "gpt10_ick", 706 .addr = omap2_timer10_addrs, 707 .user = OCP_USER_MPU | OCP_USER_SDMA, 708 }; 709 710 /* timer10 slave port */ 711 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { 712 &omap2430_l4_core__timer10, 713 }; 714 715 /* timer10 hwmod */ 716 static struct omap_hwmod omap2430_timer10_hwmod = { 717 .name = "timer10", 718 .mpu_irqs = omap2_timer10_mpu_irqs, 719 .main_clk = "gpt10_fck", 720 .prcm = { 721 .omap2 = { 722 .prcm_reg_id = 1, 723 .module_bit = OMAP24XX_EN_GPT10_SHIFT, 724 .module_offs = CORE_MOD, 725 .idlest_reg_id = 1, 726 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, 727 }, 728 }, 729 .dev_attr = &capability_pwm_dev_attr, 730 .slaves = omap2430_timer10_slaves, 731 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), 732 .class = &omap2xxx_timer_hwmod_class, 733 }; 734 735 /* timer11 */ 736 static struct omap_hwmod omap2430_timer11_hwmod; 737 738 /* l4_core -> timer11 */ 739 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { 740 .master = &omap2430_l4_core_hwmod, 741 .slave = &omap2430_timer11_hwmod, 742 .clk = "gpt11_ick", 743 .addr = omap2_timer11_addrs, 744 .user = OCP_USER_MPU | OCP_USER_SDMA, 745 }; 746 747 /* timer11 slave port */ 748 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { 749 &omap2430_l4_core__timer11, 750 }; 751 752 /* timer11 hwmod */ 753 static struct omap_hwmod omap2430_timer11_hwmod = { 754 .name = "timer11", 755 .mpu_irqs = omap2_timer11_mpu_irqs, 756 .main_clk = "gpt11_fck", 757 .prcm = { 758 .omap2 = { 759 .prcm_reg_id = 1, 760 .module_bit = OMAP24XX_EN_GPT11_SHIFT, 761 .module_offs = CORE_MOD, 762 .idlest_reg_id = 1, 763 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, 764 }, 765 }, 766 .dev_attr = &capability_pwm_dev_attr, 767 .slaves = omap2430_timer11_slaves, 768 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), 769 .class = &omap2xxx_timer_hwmod_class, 770 }; 771 772 /* timer12 */ 773 static struct omap_hwmod omap2430_timer12_hwmod; 774 775 /* l4_core -> timer12 */ 776 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { 777 .master = &omap2430_l4_core_hwmod, 778 .slave = &omap2430_timer12_hwmod, 779 .clk = "gpt12_ick", 780 .addr = omap2xxx_timer12_addrs, 781 .user = OCP_USER_MPU | OCP_USER_SDMA, 782 }; 783 784 /* timer12 slave port */ 785 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { 786 &omap2430_l4_core__timer12, 787 }; 788 789 /* timer12 hwmod */ 790 static struct omap_hwmod omap2430_timer12_hwmod = { 791 .name = "timer12", 792 .mpu_irqs = omap2xxx_timer12_mpu_irqs, 793 .main_clk = "gpt12_fck", 794 .prcm = { 795 .omap2 = { 796 .prcm_reg_id = 1, 797 .module_bit = OMAP24XX_EN_GPT12_SHIFT, 798 .module_offs = CORE_MOD, 799 .idlest_reg_id = 1, 800 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, 801 }, 802 }, 803 .dev_attr = &capability_pwm_dev_attr, 804 .slaves = omap2430_timer12_slaves, 805 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), 806 .class = &omap2xxx_timer_hwmod_class, 807 }; 808 809 /* l4_wkup -> wd_timer2 */ 810 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 811 { 812 .pa_start = 0x49016000, 813 .pa_end = 0x4901607f, 814 .flags = ADDR_TYPE_RT 815 }, 816 { } 817 }; 818 819 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 820 .master = &omap2430_l4_wkup_hwmod, 821 .slave = &omap2430_wd_timer2_hwmod, 822 .clk = "mpu_wdt_ick", 823 .addr = omap2430_wd_timer2_addrs, 824 .user = OCP_USER_MPU | OCP_USER_SDMA, 825 }; 826 827 /* wd_timer2 */ 828 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { 829 &omap2430_l4_wkup__wd_timer2, 830 }; 831 832 static struct omap_hwmod omap2430_wd_timer2_hwmod = { 833 .name = "wd_timer2", 834 .class = &omap2xxx_wd_timer_hwmod_class, 835 .main_clk = "mpu_wdt_fck", 836 .prcm = { 837 .omap2 = { 838 .prcm_reg_id = 1, 839 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 840 .module_offs = WKUP_MOD, 841 .idlest_reg_id = 1, 842 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, 843 }, 844 }, 845 .slaves = omap2430_wd_timer2_slaves, 846 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), 847 }; 848 849 /* UART1 */ 850 851 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { 852 &omap2_l4_core__uart1, 853 }; 854 855 static struct omap_hwmod omap2430_uart1_hwmod = { 856 .name = "uart1", 857 .mpu_irqs = omap2_uart1_mpu_irqs, 858 .sdma_reqs = omap2_uart1_sdma_reqs, 859 .main_clk = "uart1_fck", 860 .prcm = { 861 .omap2 = { 862 .module_offs = CORE_MOD, 863 .prcm_reg_id = 1, 864 .module_bit = OMAP24XX_EN_UART1_SHIFT, 865 .idlest_reg_id = 1, 866 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, 867 }, 868 }, 869 .slaves = omap2430_uart1_slaves, 870 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), 871 .class = &omap2_uart_class, 872 }; 873 874 /* UART2 */ 875 876 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { 877 &omap2_l4_core__uart2, 878 }; 879 880 static struct omap_hwmod omap2430_uart2_hwmod = { 881 .name = "uart2", 882 .mpu_irqs = omap2_uart2_mpu_irqs, 883 .sdma_reqs = omap2_uart2_sdma_reqs, 884 .main_clk = "uart2_fck", 885 .prcm = { 886 .omap2 = { 887 .module_offs = CORE_MOD, 888 .prcm_reg_id = 1, 889 .module_bit = OMAP24XX_EN_UART2_SHIFT, 890 .idlest_reg_id = 1, 891 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, 892 }, 893 }, 894 .slaves = omap2430_uart2_slaves, 895 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), 896 .class = &omap2_uart_class, 897 }; 898 899 /* UART3 */ 900 901 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { 902 &omap2_l4_core__uart3, 903 }; 904 905 static struct omap_hwmod omap2430_uart3_hwmod = { 906 .name = "uart3", 907 .mpu_irqs = omap2_uart3_mpu_irqs, 908 .sdma_reqs = omap2_uart3_sdma_reqs, 909 .main_clk = "uart3_fck", 910 .prcm = { 911 .omap2 = { 912 .module_offs = CORE_MOD, 913 .prcm_reg_id = 2, 914 .module_bit = OMAP24XX_EN_UART3_SHIFT, 915 .idlest_reg_id = 2, 916 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, 917 }, 918 }, 919 .slaves = omap2430_uart3_slaves, 920 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), 921 .class = &omap2_uart_class, 922 }; 923 924 /* dss */ 925 /* dss master ports */ 926 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { 927 &omap2430_dss__l3, 928 }; 929 930 /* l4_core -> dss */ 931 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { 932 .master = &omap2430_l4_core_hwmod, 933 .slave = &omap2430_dss_core_hwmod, 934 .clk = "dss_ick", 935 .addr = omap2_dss_addrs, 936 .user = OCP_USER_MPU | OCP_USER_SDMA, 937 }; 938 939 /* dss slave ports */ 940 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { 941 &omap2430_l4_core__dss, 942 }; 943 944 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 945 { .role = "tv_clk", .clk = "dss_54m_fck" }, 946 { .role = "sys_clk", .clk = "dss2_fck" }, 947 }; 948 949 static struct omap_hwmod omap2430_dss_core_hwmod = { 950 .name = "dss_core", 951 .class = &omap2_dss_hwmod_class, 952 .main_clk = "dss1_fck", /* instead of dss_fck */ 953 .sdma_reqs = omap2xxx_dss_sdma_chs, 954 .prcm = { 955 .omap2 = { 956 .prcm_reg_id = 1, 957 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 958 .module_offs = CORE_MOD, 959 .idlest_reg_id = 1, 960 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 961 }, 962 }, 963 .opt_clks = dss_opt_clks, 964 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 965 .slaves = omap2430_dss_slaves, 966 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), 967 .masters = omap2430_dss_masters, 968 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), 969 .flags = HWMOD_NO_IDLEST, 970 }; 971 972 /* l4_core -> dss_dispc */ 973 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { 974 .master = &omap2430_l4_core_hwmod, 975 .slave = &omap2430_dss_dispc_hwmod, 976 .clk = "dss_ick", 977 .addr = omap2_dss_dispc_addrs, 978 .user = OCP_USER_MPU | OCP_USER_SDMA, 979 }; 980 981 /* dss_dispc slave ports */ 982 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { 983 &omap2430_l4_core__dss_dispc, 984 }; 985 986 static struct omap_hwmod omap2430_dss_dispc_hwmod = { 987 .name = "dss_dispc", 988 .class = &omap2_dispc_hwmod_class, 989 .mpu_irqs = omap2_dispc_irqs, 990 .main_clk = "dss1_fck", 991 .prcm = { 992 .omap2 = { 993 .prcm_reg_id = 1, 994 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 995 .module_offs = CORE_MOD, 996 .idlest_reg_id = 1, 997 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 998 }, 999 }, 1000 .slaves = omap2430_dss_dispc_slaves, 1001 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), 1002 .flags = HWMOD_NO_IDLEST, 1003 }; 1004 1005 /* l4_core -> dss_rfbi */ 1006 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { 1007 .master = &omap2430_l4_core_hwmod, 1008 .slave = &omap2430_dss_rfbi_hwmod, 1009 .clk = "dss_ick", 1010 .addr = omap2_dss_rfbi_addrs, 1011 .user = OCP_USER_MPU | OCP_USER_SDMA, 1012 }; 1013 1014 /* dss_rfbi slave ports */ 1015 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { 1016 &omap2430_l4_core__dss_rfbi, 1017 }; 1018 1019 static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1020 .name = "dss_rfbi", 1021 .class = &omap2_rfbi_hwmod_class, 1022 .main_clk = "dss1_fck", 1023 .prcm = { 1024 .omap2 = { 1025 .prcm_reg_id = 1, 1026 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1027 .module_offs = CORE_MOD, 1028 }, 1029 }, 1030 .slaves = omap2430_dss_rfbi_slaves, 1031 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), 1032 .flags = HWMOD_NO_IDLEST, 1033 }; 1034 1035 /* l4_core -> dss_venc */ 1036 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1037 .master = &omap2430_l4_core_hwmod, 1038 .slave = &omap2430_dss_venc_hwmod, 1039 .clk = "dss_54m_fck", 1040 .addr = omap2_dss_venc_addrs, 1041 .flags = OCPIF_SWSUP_IDLE, 1042 .user = OCP_USER_MPU | OCP_USER_SDMA, 1043 }; 1044 1045 /* dss_venc slave ports */ 1046 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { 1047 &omap2430_l4_core__dss_venc, 1048 }; 1049 1050 static struct omap_hwmod omap2430_dss_venc_hwmod = { 1051 .name = "dss_venc", 1052 .class = &omap2_venc_hwmod_class, 1053 .main_clk = "dss1_fck", 1054 .prcm = { 1055 .omap2 = { 1056 .prcm_reg_id = 1, 1057 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1058 .module_offs = CORE_MOD, 1059 }, 1060 }, 1061 .slaves = omap2430_dss_venc_slaves, 1062 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), 1063 .flags = HWMOD_NO_IDLEST, 1064 }; 1065 1066 /* I2C common */ 1067 static struct omap_hwmod_class_sysconfig i2c_sysc = { 1068 .rev_offs = 0x00, 1069 .sysc_offs = 0x20, 1070 .syss_offs = 0x10, 1071 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1072 SYSS_HAS_RESET_STATUS), 1073 .sysc_fields = &omap_hwmod_sysc_type1, 1074 }; 1075 1076 static struct omap_hwmod_class i2c_class = { 1077 .name = "i2c", 1078 .sysc = &i2c_sysc, 1079 .rev = OMAP_I2C_IP_VERSION_1, 1080 .reset = &omap_i2c_reset, 1081 }; 1082 1083 static struct omap_i2c_dev_attr i2c_dev_attr = { 1084 .fifo_depth = 8, /* bytes */ 1085 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 1086 OMAP_I2C_FLAG_BUS_SHIFT_2 | 1087 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 1088 }; 1089 1090 /* I2C1 */ 1091 1092 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { 1093 &omap2430_l4_core__i2c1, 1094 }; 1095 1096 static struct omap_hwmod omap2430_i2c1_hwmod = { 1097 .name = "i2c1", 1098 .flags = HWMOD_16BIT_REG, 1099 .mpu_irqs = omap2_i2c1_mpu_irqs, 1100 .sdma_reqs = omap2_i2c1_sdma_reqs, 1101 .main_clk = "i2chs1_fck", 1102 .prcm = { 1103 .omap2 = { 1104 /* 1105 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for 1106 * I2CHS IP's do not follow the usual pattern. 1107 * prcm_reg_id alone cannot be used to program 1108 * the iclk and fclk. Needs to be handled using 1109 * additional flags when clk handling is moved 1110 * to hwmod framework. 1111 */ 1112 .module_offs = CORE_MOD, 1113 .prcm_reg_id = 1, 1114 .module_bit = OMAP2430_EN_I2CHS1_SHIFT, 1115 .idlest_reg_id = 1, 1116 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 1117 }, 1118 }, 1119 .slaves = omap2430_i2c1_slaves, 1120 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), 1121 .class = &i2c_class, 1122 .dev_attr = &i2c_dev_attr, 1123 }; 1124 1125 /* I2C2 */ 1126 1127 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { 1128 &omap2430_l4_core__i2c2, 1129 }; 1130 1131 static struct omap_hwmod omap2430_i2c2_hwmod = { 1132 .name = "i2c2", 1133 .flags = HWMOD_16BIT_REG, 1134 .mpu_irqs = omap2_i2c2_mpu_irqs, 1135 .sdma_reqs = omap2_i2c2_sdma_reqs, 1136 .main_clk = "i2chs2_fck", 1137 .prcm = { 1138 .omap2 = { 1139 .module_offs = CORE_MOD, 1140 .prcm_reg_id = 1, 1141 .module_bit = OMAP2430_EN_I2CHS2_SHIFT, 1142 .idlest_reg_id = 1, 1143 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 1144 }, 1145 }, 1146 .slaves = omap2430_i2c2_slaves, 1147 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), 1148 .class = &i2c_class, 1149 .dev_attr = &i2c_dev_attr, 1150 }; 1151 1152 /* l4_wkup -> gpio1 */ 1153 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { 1154 { 1155 .pa_start = 0x4900C000, 1156 .pa_end = 0x4900C1ff, 1157 .flags = ADDR_TYPE_RT 1158 }, 1159 { } 1160 }; 1161 1162 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 1163 .master = &omap2430_l4_wkup_hwmod, 1164 .slave = &omap2430_gpio1_hwmod, 1165 .clk = "gpios_ick", 1166 .addr = omap2430_gpio1_addr_space, 1167 .user = OCP_USER_MPU | OCP_USER_SDMA, 1168 }; 1169 1170 /* l4_wkup -> gpio2 */ 1171 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { 1172 { 1173 .pa_start = 0x4900E000, 1174 .pa_end = 0x4900E1ff, 1175 .flags = ADDR_TYPE_RT 1176 }, 1177 { } 1178 }; 1179 1180 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 1181 .master = &omap2430_l4_wkup_hwmod, 1182 .slave = &omap2430_gpio2_hwmod, 1183 .clk = "gpios_ick", 1184 .addr = omap2430_gpio2_addr_space, 1185 .user = OCP_USER_MPU | OCP_USER_SDMA, 1186 }; 1187 1188 /* l4_wkup -> gpio3 */ 1189 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { 1190 { 1191 .pa_start = 0x49010000, 1192 .pa_end = 0x490101ff, 1193 .flags = ADDR_TYPE_RT 1194 }, 1195 { } 1196 }; 1197 1198 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 1199 .master = &omap2430_l4_wkup_hwmod, 1200 .slave = &omap2430_gpio3_hwmod, 1201 .clk = "gpios_ick", 1202 .addr = omap2430_gpio3_addr_space, 1203 .user = OCP_USER_MPU | OCP_USER_SDMA, 1204 }; 1205 1206 /* l4_wkup -> gpio4 */ 1207 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { 1208 { 1209 .pa_start = 0x49012000, 1210 .pa_end = 0x490121ff, 1211 .flags = ADDR_TYPE_RT 1212 }, 1213 { } 1214 }; 1215 1216 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 1217 .master = &omap2430_l4_wkup_hwmod, 1218 .slave = &omap2430_gpio4_hwmod, 1219 .clk = "gpios_ick", 1220 .addr = omap2430_gpio4_addr_space, 1221 .user = OCP_USER_MPU | OCP_USER_SDMA, 1222 }; 1223 1224 /* l4_core -> gpio5 */ 1225 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { 1226 { 1227 .pa_start = 0x480B6000, 1228 .pa_end = 0x480B61ff, 1229 .flags = ADDR_TYPE_RT 1230 }, 1231 { } 1232 }; 1233 1234 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 1235 .master = &omap2430_l4_core_hwmod, 1236 .slave = &omap2430_gpio5_hwmod, 1237 .clk = "gpio5_ick", 1238 .addr = omap2430_gpio5_addr_space, 1239 .user = OCP_USER_MPU | OCP_USER_SDMA, 1240 }; 1241 1242 /* gpio dev_attr */ 1243 static struct omap_gpio_dev_attr gpio_dev_attr = { 1244 .bank_width = 32, 1245 .dbck_flag = false, 1246 }; 1247 1248 /* gpio1 */ 1249 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { 1250 &omap2430_l4_wkup__gpio1, 1251 }; 1252 1253 static struct omap_hwmod omap2430_gpio1_hwmod = { 1254 .name = "gpio1", 1255 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1256 .mpu_irqs = omap2_gpio1_irqs, 1257 .main_clk = "gpios_fck", 1258 .prcm = { 1259 .omap2 = { 1260 .prcm_reg_id = 1, 1261 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1262 .module_offs = WKUP_MOD, 1263 .idlest_reg_id = 1, 1264 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, 1265 }, 1266 }, 1267 .slaves = omap2430_gpio1_slaves, 1268 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), 1269 .class = &omap2xxx_gpio_hwmod_class, 1270 .dev_attr = &gpio_dev_attr, 1271 }; 1272 1273 /* gpio2 */ 1274 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { 1275 &omap2430_l4_wkup__gpio2, 1276 }; 1277 1278 static struct omap_hwmod omap2430_gpio2_hwmod = { 1279 .name = "gpio2", 1280 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1281 .mpu_irqs = omap2_gpio2_irqs, 1282 .main_clk = "gpios_fck", 1283 .prcm = { 1284 .omap2 = { 1285 .prcm_reg_id = 1, 1286 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1287 .module_offs = WKUP_MOD, 1288 .idlest_reg_id = 1, 1289 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1290 }, 1291 }, 1292 .slaves = omap2430_gpio2_slaves, 1293 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), 1294 .class = &omap2xxx_gpio_hwmod_class, 1295 .dev_attr = &gpio_dev_attr, 1296 }; 1297 1298 /* gpio3 */ 1299 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { 1300 &omap2430_l4_wkup__gpio3, 1301 }; 1302 1303 static struct omap_hwmod omap2430_gpio3_hwmod = { 1304 .name = "gpio3", 1305 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1306 .mpu_irqs = omap2_gpio3_irqs, 1307 .main_clk = "gpios_fck", 1308 .prcm = { 1309 .omap2 = { 1310 .prcm_reg_id = 1, 1311 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1312 .module_offs = WKUP_MOD, 1313 .idlest_reg_id = 1, 1314 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1315 }, 1316 }, 1317 .slaves = omap2430_gpio3_slaves, 1318 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), 1319 .class = &omap2xxx_gpio_hwmod_class, 1320 .dev_attr = &gpio_dev_attr, 1321 }; 1322 1323 /* gpio4 */ 1324 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { 1325 &omap2430_l4_wkup__gpio4, 1326 }; 1327 1328 static struct omap_hwmod omap2430_gpio4_hwmod = { 1329 .name = "gpio4", 1330 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1331 .mpu_irqs = omap2_gpio4_irqs, 1332 .main_clk = "gpios_fck", 1333 .prcm = { 1334 .omap2 = { 1335 .prcm_reg_id = 1, 1336 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1337 .module_offs = WKUP_MOD, 1338 .idlest_reg_id = 1, 1339 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1340 }, 1341 }, 1342 .slaves = omap2430_gpio4_slaves, 1343 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), 1344 .class = &omap2xxx_gpio_hwmod_class, 1345 .dev_attr = &gpio_dev_attr, 1346 }; 1347 1348 /* gpio5 */ 1349 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 1350 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ 1351 { .irq = -1 } 1352 }; 1353 1354 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { 1355 &omap2430_l4_core__gpio5, 1356 }; 1357 1358 static struct omap_hwmod omap2430_gpio5_hwmod = { 1359 .name = "gpio5", 1360 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1361 .mpu_irqs = omap243x_gpio5_irqs, 1362 .main_clk = "gpio5_fck", 1363 .prcm = { 1364 .omap2 = { 1365 .prcm_reg_id = 2, 1366 .module_bit = OMAP2430_EN_GPIO5_SHIFT, 1367 .module_offs = CORE_MOD, 1368 .idlest_reg_id = 2, 1369 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 1370 }, 1371 }, 1372 .slaves = omap2430_gpio5_slaves, 1373 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), 1374 .class = &omap2xxx_gpio_hwmod_class, 1375 .dev_attr = &gpio_dev_attr, 1376 }; 1377 1378 /* dma attributes */ 1379 static struct omap_dma_dev_attr dma_dev_attr = { 1380 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1381 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 1382 .lch_count = 32, 1383 }; 1384 1385 /* dma_system -> L3 */ 1386 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 1387 .master = &omap2430_dma_system_hwmod, 1388 .slave = &omap2430_l3_main_hwmod, 1389 .clk = "core_l3_ck", 1390 .user = OCP_USER_MPU | OCP_USER_SDMA, 1391 }; 1392 1393 /* dma_system master ports */ 1394 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { 1395 &omap2430_dma_system__l3, 1396 }; 1397 1398 /* l4_core -> dma_system */ 1399 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { 1400 .master = &omap2430_l4_core_hwmod, 1401 .slave = &omap2430_dma_system_hwmod, 1402 .clk = "sdma_ick", 1403 .addr = omap2_dma_system_addrs, 1404 .user = OCP_USER_MPU | OCP_USER_SDMA, 1405 }; 1406 1407 /* dma_system slave ports */ 1408 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { 1409 &omap2430_l4_core__dma_system, 1410 }; 1411 1412 static struct omap_hwmod omap2430_dma_system_hwmod = { 1413 .name = "dma", 1414 .class = &omap2xxx_dma_hwmod_class, 1415 .mpu_irqs = omap2_dma_system_irqs, 1416 .main_clk = "core_l3_ck", 1417 .slaves = omap2430_dma_system_slaves, 1418 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), 1419 .masters = omap2430_dma_system_masters, 1420 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), 1421 .dev_attr = &dma_dev_attr, 1422 .flags = HWMOD_NO_IDLEST, 1423 }; 1424 1425 /* mailbox */ 1426 static struct omap_hwmod omap2430_mailbox_hwmod; 1427 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 1428 { .irq = 26 }, 1429 { .irq = -1 } 1430 }; 1431 1432 /* l4_core -> mailbox */ 1433 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 1434 .master = &omap2430_l4_core_hwmod, 1435 .slave = &omap2430_mailbox_hwmod, 1436 .addr = omap2_mailbox_addrs, 1437 .user = OCP_USER_MPU | OCP_USER_SDMA, 1438 }; 1439 1440 /* mailbox slave ports */ 1441 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { 1442 &omap2430_l4_core__mailbox, 1443 }; 1444 1445 static struct omap_hwmod omap2430_mailbox_hwmod = { 1446 .name = "mailbox", 1447 .class = &omap2xxx_mailbox_hwmod_class, 1448 .mpu_irqs = omap2430_mailbox_irqs, 1449 .main_clk = "mailboxes_ick", 1450 .prcm = { 1451 .omap2 = { 1452 .prcm_reg_id = 1, 1453 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 1454 .module_offs = CORE_MOD, 1455 .idlest_reg_id = 1, 1456 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 1457 }, 1458 }, 1459 .slaves = omap2430_mailbox_slaves, 1460 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), 1461 }; 1462 1463 /* mcspi1 */ 1464 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { 1465 &omap2430_l4_core__mcspi1, 1466 }; 1467 1468 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1469 .num_chipselect = 4, 1470 }; 1471 1472 static struct omap_hwmod omap2430_mcspi1_hwmod = { 1473 .name = "mcspi1_hwmod", 1474 .mpu_irqs = omap2_mcspi1_mpu_irqs, 1475 .sdma_reqs = omap2_mcspi1_sdma_reqs, 1476 .main_clk = "mcspi1_fck", 1477 .prcm = { 1478 .omap2 = { 1479 .module_offs = CORE_MOD, 1480 .prcm_reg_id = 1, 1481 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1482 .idlest_reg_id = 1, 1483 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, 1484 }, 1485 }, 1486 .slaves = omap2430_mcspi1_slaves, 1487 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), 1488 .class = &omap2xxx_mcspi_class, 1489 .dev_attr = &omap_mcspi1_dev_attr, 1490 }; 1491 1492 /* mcspi2 */ 1493 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { 1494 &omap2430_l4_core__mcspi2, 1495 }; 1496 1497 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1498 .num_chipselect = 2, 1499 }; 1500 1501 static struct omap_hwmod omap2430_mcspi2_hwmod = { 1502 .name = "mcspi2_hwmod", 1503 .mpu_irqs = omap2_mcspi2_mpu_irqs, 1504 .sdma_reqs = omap2_mcspi2_sdma_reqs, 1505 .main_clk = "mcspi2_fck", 1506 .prcm = { 1507 .omap2 = { 1508 .module_offs = CORE_MOD, 1509 .prcm_reg_id = 1, 1510 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1511 .idlest_reg_id = 1, 1512 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, 1513 }, 1514 }, 1515 .slaves = omap2430_mcspi2_slaves, 1516 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), 1517 .class = &omap2xxx_mcspi_class, 1518 .dev_attr = &omap_mcspi2_dev_attr, 1519 }; 1520 1521 /* mcspi3 */ 1522 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { 1523 { .irq = 91 }, 1524 { .irq = -1 } 1525 }; 1526 1527 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { 1528 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ 1529 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ 1530 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ 1531 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ 1532 { .dma_req = -1 } 1533 }; 1534 1535 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { 1536 &omap2430_l4_core__mcspi3, 1537 }; 1538 1539 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1540 .num_chipselect = 2, 1541 }; 1542 1543 static struct omap_hwmod omap2430_mcspi3_hwmod = { 1544 .name = "mcspi3_hwmod", 1545 .mpu_irqs = omap2430_mcspi3_mpu_irqs, 1546 .sdma_reqs = omap2430_mcspi3_sdma_reqs, 1547 .main_clk = "mcspi3_fck", 1548 .prcm = { 1549 .omap2 = { 1550 .module_offs = CORE_MOD, 1551 .prcm_reg_id = 2, 1552 .module_bit = OMAP2430_EN_MCSPI3_SHIFT, 1553 .idlest_reg_id = 2, 1554 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 1555 }, 1556 }, 1557 .slaves = omap2430_mcspi3_slaves, 1558 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), 1559 .class = &omap2xxx_mcspi_class, 1560 .dev_attr = &omap_mcspi3_dev_attr, 1561 }; 1562 1563 /* 1564 * usbhsotg 1565 */ 1566 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 1567 .rev_offs = 0x0400, 1568 .sysc_offs = 0x0404, 1569 .syss_offs = 0x0408, 1570 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 1571 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1572 SYSC_HAS_AUTOIDLE), 1573 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1574 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1575 .sysc_fields = &omap_hwmod_sysc_type1, 1576 }; 1577 1578 static struct omap_hwmod_class usbotg_class = { 1579 .name = "usbotg", 1580 .sysc = &omap2430_usbhsotg_sysc, 1581 }; 1582 1583 /* usb_otg_hs */ 1584 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { 1585 1586 { .name = "mc", .irq = 92 }, 1587 { .name = "dma", .irq = 93 }, 1588 { .irq = -1 } 1589 }; 1590 1591 static struct omap_hwmod omap2430_usbhsotg_hwmod = { 1592 .name = "usb_otg_hs", 1593 .mpu_irqs = omap2430_usbhsotg_mpu_irqs, 1594 .main_clk = "usbhs_ick", 1595 .prcm = { 1596 .omap2 = { 1597 .prcm_reg_id = 1, 1598 .module_bit = OMAP2430_EN_USBHS_MASK, 1599 .module_offs = CORE_MOD, 1600 .idlest_reg_id = 1, 1601 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 1602 }, 1603 }, 1604 .masters = omap2430_usbhsotg_masters, 1605 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), 1606 .slaves = omap2430_usbhsotg_slaves, 1607 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), 1608 .class = &usbotg_class, 1609 /* 1610 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1611 * broken when autoidle is enabled 1612 * workaround is to disable the autoidle bit at module level. 1613 */ 1614 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 1615 | HWMOD_SWSUP_MSTANDBY, 1616 }; 1617 1618 /* 1619 * 'mcbsp' class 1620 * multi channel buffered serial port controller 1621 */ 1622 1623 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { 1624 .rev_offs = 0x007C, 1625 .sysc_offs = 0x008C, 1626 .sysc_flags = (SYSC_HAS_SOFTRESET), 1627 .sysc_fields = &omap_hwmod_sysc_type1, 1628 }; 1629 1630 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { 1631 .name = "mcbsp", 1632 .sysc = &omap2430_mcbsp_sysc, 1633 .rev = MCBSP_CONFIG_TYPE2, 1634 }; 1635 1636 /* mcbsp1 */ 1637 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { 1638 { .name = "tx", .irq = 59 }, 1639 { .name = "rx", .irq = 60 }, 1640 { .name = "ovr", .irq = 61 }, 1641 { .name = "common", .irq = 64 }, 1642 { .irq = -1 } 1643 }; 1644 1645 /* l4_core -> mcbsp1 */ 1646 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { 1647 .master = &omap2430_l4_core_hwmod, 1648 .slave = &omap2430_mcbsp1_hwmod, 1649 .clk = "mcbsp1_ick", 1650 .addr = omap2_mcbsp1_addrs, 1651 .user = OCP_USER_MPU | OCP_USER_SDMA, 1652 }; 1653 1654 /* mcbsp1 slave ports */ 1655 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { 1656 &omap2430_l4_core__mcbsp1, 1657 }; 1658 1659 static struct omap_hwmod omap2430_mcbsp1_hwmod = { 1660 .name = "mcbsp1", 1661 .class = &omap2430_mcbsp_hwmod_class, 1662 .mpu_irqs = omap2430_mcbsp1_irqs, 1663 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 1664 .main_clk = "mcbsp1_fck", 1665 .prcm = { 1666 .omap2 = { 1667 .prcm_reg_id = 1, 1668 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1669 .module_offs = CORE_MOD, 1670 .idlest_reg_id = 1, 1671 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 1672 }, 1673 }, 1674 .slaves = omap2430_mcbsp1_slaves, 1675 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), 1676 }; 1677 1678 /* mcbsp2 */ 1679 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { 1680 { .name = "tx", .irq = 62 }, 1681 { .name = "rx", .irq = 63 }, 1682 { .name = "common", .irq = 16 }, 1683 { .irq = -1 } 1684 }; 1685 1686 /* l4_core -> mcbsp2 */ 1687 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { 1688 .master = &omap2430_l4_core_hwmod, 1689 .slave = &omap2430_mcbsp2_hwmod, 1690 .clk = "mcbsp2_ick", 1691 .addr = omap2xxx_mcbsp2_addrs, 1692 .user = OCP_USER_MPU | OCP_USER_SDMA, 1693 }; 1694 1695 /* mcbsp2 slave ports */ 1696 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { 1697 &omap2430_l4_core__mcbsp2, 1698 }; 1699 1700 static struct omap_hwmod omap2430_mcbsp2_hwmod = { 1701 .name = "mcbsp2", 1702 .class = &omap2430_mcbsp_hwmod_class, 1703 .mpu_irqs = omap2430_mcbsp2_irqs, 1704 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 1705 .main_clk = "mcbsp2_fck", 1706 .prcm = { 1707 .omap2 = { 1708 .prcm_reg_id = 1, 1709 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1710 .module_offs = CORE_MOD, 1711 .idlest_reg_id = 1, 1712 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 1713 }, 1714 }, 1715 .slaves = omap2430_mcbsp2_slaves, 1716 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), 1717 }; 1718 1719 /* mcbsp3 */ 1720 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { 1721 { .name = "tx", .irq = 89 }, 1722 { .name = "rx", .irq = 90 }, 1723 { .name = "common", .irq = 17 }, 1724 { .irq = -1 } 1725 }; 1726 1727 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { 1728 { 1729 .name = "mpu", 1730 .pa_start = 0x4808C000, 1731 .pa_end = 0x4808C0ff, 1732 .flags = ADDR_TYPE_RT 1733 }, 1734 { } 1735 }; 1736 1737 /* l4_core -> mcbsp3 */ 1738 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 1739 .master = &omap2430_l4_core_hwmod, 1740 .slave = &omap2430_mcbsp3_hwmod, 1741 .clk = "mcbsp3_ick", 1742 .addr = omap2430_mcbsp3_addrs, 1743 .user = OCP_USER_MPU | OCP_USER_SDMA, 1744 }; 1745 1746 /* mcbsp3 slave ports */ 1747 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { 1748 &omap2430_l4_core__mcbsp3, 1749 }; 1750 1751 static struct omap_hwmod omap2430_mcbsp3_hwmod = { 1752 .name = "mcbsp3", 1753 .class = &omap2430_mcbsp_hwmod_class, 1754 .mpu_irqs = omap2430_mcbsp3_irqs, 1755 .sdma_reqs = omap2_mcbsp3_sdma_reqs, 1756 .main_clk = "mcbsp3_fck", 1757 .prcm = { 1758 .omap2 = { 1759 .prcm_reg_id = 1, 1760 .module_bit = OMAP2430_EN_MCBSP3_SHIFT, 1761 .module_offs = CORE_MOD, 1762 .idlest_reg_id = 2, 1763 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 1764 }, 1765 }, 1766 .slaves = omap2430_mcbsp3_slaves, 1767 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), 1768 }; 1769 1770 /* mcbsp4 */ 1771 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { 1772 { .name = "tx", .irq = 54 }, 1773 { .name = "rx", .irq = 55 }, 1774 { .name = "common", .irq = 18 }, 1775 { .irq = -1 } 1776 }; 1777 1778 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { 1779 { .name = "rx", .dma_req = 20 }, 1780 { .name = "tx", .dma_req = 19 }, 1781 { .dma_req = -1 } 1782 }; 1783 1784 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { 1785 { 1786 .name = "mpu", 1787 .pa_start = 0x4808E000, 1788 .pa_end = 0x4808E0ff, 1789 .flags = ADDR_TYPE_RT 1790 }, 1791 { } 1792 }; 1793 1794 /* l4_core -> mcbsp4 */ 1795 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 1796 .master = &omap2430_l4_core_hwmod, 1797 .slave = &omap2430_mcbsp4_hwmod, 1798 .clk = "mcbsp4_ick", 1799 .addr = omap2430_mcbsp4_addrs, 1800 .user = OCP_USER_MPU | OCP_USER_SDMA, 1801 }; 1802 1803 /* mcbsp4 slave ports */ 1804 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { 1805 &omap2430_l4_core__mcbsp4, 1806 }; 1807 1808 static struct omap_hwmod omap2430_mcbsp4_hwmod = { 1809 .name = "mcbsp4", 1810 .class = &omap2430_mcbsp_hwmod_class, 1811 .mpu_irqs = omap2430_mcbsp4_irqs, 1812 .sdma_reqs = omap2430_mcbsp4_sdma_chs, 1813 .main_clk = "mcbsp4_fck", 1814 .prcm = { 1815 .omap2 = { 1816 .prcm_reg_id = 1, 1817 .module_bit = OMAP2430_EN_MCBSP4_SHIFT, 1818 .module_offs = CORE_MOD, 1819 .idlest_reg_id = 2, 1820 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 1821 }, 1822 }, 1823 .slaves = omap2430_mcbsp4_slaves, 1824 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), 1825 }; 1826 1827 /* mcbsp5 */ 1828 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { 1829 { .name = "tx", .irq = 81 }, 1830 { .name = "rx", .irq = 82 }, 1831 { .name = "common", .irq = 19 }, 1832 { .irq = -1 } 1833 }; 1834 1835 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { 1836 { .name = "rx", .dma_req = 22 }, 1837 { .name = "tx", .dma_req = 21 }, 1838 { .dma_req = -1 } 1839 }; 1840 1841 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { 1842 { 1843 .name = "mpu", 1844 .pa_start = 0x48096000, 1845 .pa_end = 0x480960ff, 1846 .flags = ADDR_TYPE_RT 1847 }, 1848 { } 1849 }; 1850 1851 /* l4_core -> mcbsp5 */ 1852 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 1853 .master = &omap2430_l4_core_hwmod, 1854 .slave = &omap2430_mcbsp5_hwmod, 1855 .clk = "mcbsp5_ick", 1856 .addr = omap2430_mcbsp5_addrs, 1857 .user = OCP_USER_MPU | OCP_USER_SDMA, 1858 }; 1859 1860 /* mcbsp5 slave ports */ 1861 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { 1862 &omap2430_l4_core__mcbsp5, 1863 }; 1864 1865 static struct omap_hwmod omap2430_mcbsp5_hwmod = { 1866 .name = "mcbsp5", 1867 .class = &omap2430_mcbsp_hwmod_class, 1868 .mpu_irqs = omap2430_mcbsp5_irqs, 1869 .sdma_reqs = omap2430_mcbsp5_sdma_chs, 1870 .main_clk = "mcbsp5_fck", 1871 .prcm = { 1872 .omap2 = { 1873 .prcm_reg_id = 1, 1874 .module_bit = OMAP2430_EN_MCBSP5_SHIFT, 1875 .module_offs = CORE_MOD, 1876 .idlest_reg_id = 2, 1877 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 1878 }, 1879 }, 1880 .slaves = omap2430_mcbsp5_slaves, 1881 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), 1882 }; 1883 1884 /* MMC/SD/SDIO common */ 1885 1886 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 1887 .rev_offs = 0x1fc, 1888 .sysc_offs = 0x10, 1889 .syss_offs = 0x14, 1890 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1891 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1892 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1893 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1894 .sysc_fields = &omap_hwmod_sysc_type1, 1895 }; 1896 1897 static struct omap_hwmod_class omap2430_mmc_class = { 1898 .name = "mmc", 1899 .sysc = &omap2430_mmc_sysc, 1900 }; 1901 1902 /* MMC/SD/SDIO1 */ 1903 1904 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { 1905 { .irq = 83 }, 1906 { .irq = -1 } 1907 }; 1908 1909 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { 1910 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ 1911 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ 1912 { .dma_req = -1 } 1913 }; 1914 1915 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 1916 { .role = "dbck", .clk = "mmchsdb1_fck" }, 1917 }; 1918 1919 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { 1920 &omap2430_l4_core__mmc1, 1921 }; 1922 1923 static struct omap_mmc_dev_attr mmc1_dev_attr = { 1924 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1925 }; 1926 1927 static struct omap_hwmod omap2430_mmc1_hwmod = { 1928 .name = "mmc1", 1929 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1930 .mpu_irqs = omap2430_mmc1_mpu_irqs, 1931 .sdma_reqs = omap2430_mmc1_sdma_reqs, 1932 .opt_clks = omap2430_mmc1_opt_clks, 1933 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 1934 .main_clk = "mmchs1_fck", 1935 .prcm = { 1936 .omap2 = { 1937 .module_offs = CORE_MOD, 1938 .prcm_reg_id = 2, 1939 .module_bit = OMAP2430_EN_MMCHS1_SHIFT, 1940 .idlest_reg_id = 2, 1941 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, 1942 }, 1943 }, 1944 .dev_attr = &mmc1_dev_attr, 1945 .slaves = omap2430_mmc1_slaves, 1946 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), 1947 .class = &omap2430_mmc_class, 1948 }; 1949 1950 /* MMC/SD/SDIO2 */ 1951 1952 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { 1953 { .irq = 86 }, 1954 { .irq = -1 } 1955 }; 1956 1957 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { 1958 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ 1959 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ 1960 { .dma_req = -1 } 1961 }; 1962 1963 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 1964 { .role = "dbck", .clk = "mmchsdb2_fck" }, 1965 }; 1966 1967 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { 1968 &omap2430_l4_core__mmc2, 1969 }; 1970 1971 static struct omap_hwmod omap2430_mmc2_hwmod = { 1972 .name = "mmc2", 1973 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1974 .mpu_irqs = omap2430_mmc2_mpu_irqs, 1975 .sdma_reqs = omap2430_mmc2_sdma_reqs, 1976 .opt_clks = omap2430_mmc2_opt_clks, 1977 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 1978 .main_clk = "mmchs2_fck", 1979 .prcm = { 1980 .omap2 = { 1981 .module_offs = CORE_MOD, 1982 .prcm_reg_id = 2, 1983 .module_bit = OMAP2430_EN_MMCHS2_SHIFT, 1984 .idlest_reg_id = 2, 1985 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 1986 }, 1987 }, 1988 .slaves = omap2430_mmc2_slaves, 1989 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), 1990 .class = &omap2430_mmc_class, 1991 }; 1992 1993 static __initdata struct omap_hwmod *omap2430_hwmods[] = { 1994 &omap2430_l3_main_hwmod, 1995 &omap2430_l4_core_hwmod, 1996 &omap2430_l4_wkup_hwmod, 1997 &omap2430_mpu_hwmod, 1998 &omap2430_iva_hwmod, 1999 2000 &omap2430_timer1_hwmod, 2001 &omap2430_timer2_hwmod, 2002 &omap2430_timer3_hwmod, 2003 &omap2430_timer4_hwmod, 2004 &omap2430_timer5_hwmod, 2005 &omap2430_timer6_hwmod, 2006 &omap2430_timer7_hwmod, 2007 &omap2430_timer8_hwmod, 2008 &omap2430_timer9_hwmod, 2009 &omap2430_timer10_hwmod, 2010 &omap2430_timer11_hwmod, 2011 &omap2430_timer12_hwmod, 2012 2013 &omap2430_wd_timer2_hwmod, 2014 &omap2430_uart1_hwmod, 2015 &omap2430_uart2_hwmod, 2016 &omap2430_uart3_hwmod, 2017 /* dss class */ 2018 &omap2430_dss_core_hwmod, 2019 &omap2430_dss_dispc_hwmod, 2020 &omap2430_dss_rfbi_hwmod, 2021 &omap2430_dss_venc_hwmod, 2022 /* i2c class */ 2023 &omap2430_i2c1_hwmod, 2024 &omap2430_i2c2_hwmod, 2025 &omap2430_mmc1_hwmod, 2026 &omap2430_mmc2_hwmod, 2027 2028 /* gpio class */ 2029 &omap2430_gpio1_hwmod, 2030 &omap2430_gpio2_hwmod, 2031 &omap2430_gpio3_hwmod, 2032 &omap2430_gpio4_hwmod, 2033 &omap2430_gpio5_hwmod, 2034 2035 /* dma_system class*/ 2036 &omap2430_dma_system_hwmod, 2037 2038 /* mcbsp class */ 2039 &omap2430_mcbsp1_hwmod, 2040 &omap2430_mcbsp2_hwmod, 2041 &omap2430_mcbsp3_hwmod, 2042 &omap2430_mcbsp4_hwmod, 2043 &omap2430_mcbsp5_hwmod, 2044 2045 /* mailbox class */ 2046 &omap2430_mailbox_hwmod, 2047 2048 /* mcspi class */ 2049 &omap2430_mcspi1_hwmod, 2050 &omap2430_mcspi2_hwmod, 2051 &omap2430_mcspi3_hwmod, 2052 2053 /* usbotg class*/ 2054 &omap2430_usbhsotg_hwmod, 2055 2056 NULL, 2057 }; 2058 2059 int __init omap2430_hwmod_init(void) 2060 { 2061 return omap_hwmod_register(omap2430_hwmods); 2062 } 2063