1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 4 * 5 * Copyright (C) 2009-2011 Nokia Corporation 6 * Copyright (C) 2012 Texas Instruments, Inc. 7 * Paul Walmsley 8 * 9 * XXX handle crossbar/shared link difference for L3? 10 * XXX these should be marked initdata for multi-OMAP kernels 11 */ 12 13 #include <linux/platform_data/i2c-omap.h> 14 #include <linux/platform_data/hsmmc-omap.h> 15 #include <linux/omap-dma.h> 16 17 #include "omap_hwmod.h" 18 #include "l3_2xxx.h" 19 20 #include "soc.h" 21 #include "omap_hwmod_common_data.h" 22 #include "prm-regbits-24xx.h" 23 #include "cm-regbits-24xx.h" 24 #include "i2c.h" 25 #include "wd_timer.h" 26 27 /* 28 * OMAP2430 hardware module integration data 29 * 30 * All of the data in this section should be autogeneratable from the 31 * TI hardware database or other technical documentation. Data that 32 * is driver-specific or driver-kernel integration-specific belongs 33 * elsewhere. 34 */ 35 36 /* 37 * IP blocks 38 */ 39 40 /* IVA2 (IVA2) */ 41 static struct omap_hwmod_rst_info omap2430_iva_resets[] = { 42 { .name = "logic", .rst_shift = 0 }, 43 { .name = "mmu", .rst_shift = 1 }, 44 }; 45 46 static struct omap_hwmod omap2430_iva_hwmod = { 47 .name = "iva", 48 .class = &iva_hwmod_class, 49 .clkdm_name = "dsp_clkdm", 50 .rst_lines = omap2430_iva_resets, 51 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), 52 .main_clk = "dsp_fck", 53 }; 54 55 /* I2C common */ 56 static struct omap_hwmod_class_sysconfig i2c_sysc = { 57 .rev_offs = 0x00, 58 .sysc_offs = 0x20, 59 .syss_offs = 0x10, 60 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 61 SYSS_HAS_RESET_STATUS), 62 .sysc_fields = &omap_hwmod_sysc_type1, 63 }; 64 65 static struct omap_hwmod_class i2c_class = { 66 .name = "i2c", 67 .sysc = &i2c_sysc, 68 .reset = &omap_i2c_reset, 69 }; 70 71 /* I2C1 */ 72 static struct omap_hwmod omap2430_i2c1_hwmod = { 73 .name = "i2c1", 74 .flags = HWMOD_16BIT_REG, 75 .main_clk = "i2chs1_fck", 76 .prcm = { 77 .omap2 = { 78 /* 79 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for 80 * I2CHS IP's do not follow the usual pattern. 81 * prcm_reg_id alone cannot be used to program 82 * the iclk and fclk. Needs to be handled using 83 * additional flags when clk handling is moved 84 * to hwmod framework. 85 */ 86 .module_offs = CORE_MOD, 87 .idlest_reg_id = 1, 88 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 89 }, 90 }, 91 .class = &i2c_class, 92 }; 93 94 /* I2C2 */ 95 static struct omap_hwmod omap2430_i2c2_hwmod = { 96 .name = "i2c2", 97 .flags = HWMOD_16BIT_REG, 98 .main_clk = "i2chs2_fck", 99 .prcm = { 100 .omap2 = { 101 .module_offs = CORE_MOD, 102 .idlest_reg_id = 1, 103 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 104 }, 105 }, 106 .class = &i2c_class, 107 }; 108 109 /* gpio5 */ 110 static struct omap_hwmod omap2430_gpio5_hwmod = { 111 .name = "gpio5", 112 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 113 .main_clk = "gpio5_fck", 114 .prcm = { 115 .omap2 = { 116 .module_offs = CORE_MOD, 117 .idlest_reg_id = 2, 118 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 119 }, 120 }, 121 .class = &omap2xxx_gpio_hwmod_class, 122 }; 123 124 /* dma attributes */ 125 static struct omap_dma_dev_attr dma_dev_attr = { 126 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 127 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 128 .lch_count = 32, 129 }; 130 131 static struct omap_hwmod omap2430_dma_system_hwmod = { 132 .name = "dma", 133 .class = &omap2xxx_dma_hwmod_class, 134 .main_clk = "core_l3_ck", 135 .dev_attr = &dma_dev_attr, 136 .flags = HWMOD_NO_IDLEST, 137 }; 138 139 /* mailbox */ 140 static struct omap_hwmod omap2430_mailbox_hwmod = { 141 .name = "mailbox", 142 .class = &omap2xxx_mailbox_hwmod_class, 143 .main_clk = "mailboxes_ick", 144 .prcm = { 145 .omap2 = { 146 .module_offs = CORE_MOD, 147 .idlest_reg_id = 1, 148 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 149 }, 150 }, 151 }; 152 153 /* mcspi3 */ 154 static struct omap_hwmod omap2430_mcspi3_hwmod = { 155 .name = "mcspi3", 156 .main_clk = "mcspi3_fck", 157 .prcm = { 158 .omap2 = { 159 .module_offs = CORE_MOD, 160 .idlest_reg_id = 2, 161 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 162 }, 163 }, 164 .class = &omap2xxx_mcspi_class, 165 }; 166 167 /* usbhsotg */ 168 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 169 .rev_offs = 0x0400, 170 .sysc_offs = 0x0404, 171 .syss_offs = 0x0408, 172 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 173 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 174 SYSC_HAS_AUTOIDLE), 175 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 176 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 177 .sysc_fields = &omap_hwmod_sysc_type1, 178 }; 179 180 static struct omap_hwmod_class usbotg_class = { 181 .name = "usbotg", 182 .sysc = &omap2430_usbhsotg_sysc, 183 }; 184 185 /* usb_otg_hs */ 186 static struct omap_hwmod omap2430_usbhsotg_hwmod = { 187 .name = "usb_otg_hs", 188 .main_clk = "usbhs_ick", 189 .prcm = { 190 .omap2 = { 191 .module_offs = CORE_MOD, 192 .idlest_reg_id = 1, 193 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 194 }, 195 }, 196 .class = &usbotg_class, 197 /* 198 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 199 * broken when autoidle is enabled 200 * workaround is to disable the autoidle bit at module level. 201 */ 202 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 203 | HWMOD_SWSUP_MSTANDBY, 204 }; 205 206 /* 207 * 'mcbsp' class 208 * multi channel buffered serial port controller 209 */ 210 211 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { 212 .rev_offs = 0x007C, 213 .sysc_offs = 0x008C, 214 .sysc_flags = (SYSC_HAS_SOFTRESET), 215 .sysc_fields = &omap_hwmod_sysc_type1, 216 }; 217 218 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { 219 .name = "mcbsp", 220 .sysc = &omap2430_mcbsp_sysc, 221 }; 222 223 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { 224 { .role = "pad_fck", .clk = "mcbsp_clks" }, 225 { .role = "prcm_fck", .clk = "func_96m_ck" }, 226 }; 227 228 /* mcbsp1 */ 229 static struct omap_hwmod omap2430_mcbsp1_hwmod = { 230 .name = "mcbsp1", 231 .class = &omap2430_mcbsp_hwmod_class, 232 .main_clk = "mcbsp1_fck", 233 .prcm = { 234 .omap2 = { 235 .module_offs = CORE_MOD, 236 .idlest_reg_id = 1, 237 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 238 }, 239 }, 240 .opt_clks = mcbsp_opt_clks, 241 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 242 }; 243 244 /* mcbsp2 */ 245 static struct omap_hwmod omap2430_mcbsp2_hwmod = { 246 .name = "mcbsp2", 247 .class = &omap2430_mcbsp_hwmod_class, 248 .main_clk = "mcbsp2_fck", 249 .prcm = { 250 .omap2 = { 251 .module_offs = CORE_MOD, 252 .idlest_reg_id = 1, 253 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 254 }, 255 }, 256 .opt_clks = mcbsp_opt_clks, 257 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 258 }; 259 260 /* mcbsp3 */ 261 static struct omap_hwmod omap2430_mcbsp3_hwmod = { 262 .name = "mcbsp3", 263 .class = &omap2430_mcbsp_hwmod_class, 264 .main_clk = "mcbsp3_fck", 265 .prcm = { 266 .omap2 = { 267 .module_offs = CORE_MOD, 268 .idlest_reg_id = 2, 269 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 270 }, 271 }, 272 .opt_clks = mcbsp_opt_clks, 273 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 274 }; 275 276 /* mcbsp4 */ 277 static struct omap_hwmod omap2430_mcbsp4_hwmod = { 278 .name = "mcbsp4", 279 .class = &omap2430_mcbsp_hwmod_class, 280 .main_clk = "mcbsp4_fck", 281 .prcm = { 282 .omap2 = { 283 .module_offs = CORE_MOD, 284 .idlest_reg_id = 2, 285 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 286 }, 287 }, 288 .opt_clks = mcbsp_opt_clks, 289 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 290 }; 291 292 /* mcbsp5 */ 293 static struct omap_hwmod omap2430_mcbsp5_hwmod = { 294 .name = "mcbsp5", 295 .class = &omap2430_mcbsp_hwmod_class, 296 .main_clk = "mcbsp5_fck", 297 .prcm = { 298 .omap2 = { 299 .module_offs = CORE_MOD, 300 .idlest_reg_id = 2, 301 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 302 }, 303 }, 304 .opt_clks = mcbsp_opt_clks, 305 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 306 }; 307 308 /* MMC/SD/SDIO common */ 309 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 310 .rev_offs = 0x1fc, 311 .sysc_offs = 0x10, 312 .syss_offs = 0x14, 313 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 314 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 315 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 316 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 317 .sysc_fields = &omap_hwmod_sysc_type1, 318 }; 319 320 static struct omap_hwmod_class omap2430_mmc_class = { 321 .name = "mmc", 322 .sysc = &omap2430_mmc_sysc, 323 }; 324 325 /* MMC/SD/SDIO1 */ 326 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 327 { .role = "dbck", .clk = "mmchsdb1_fck" }, 328 }; 329 330 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 331 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 332 }; 333 334 static struct omap_hwmod omap2430_mmc1_hwmod = { 335 .name = "mmc1", 336 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 337 .opt_clks = omap2430_mmc1_opt_clks, 338 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 339 .main_clk = "mmchs1_fck", 340 .prcm = { 341 .omap2 = { 342 .module_offs = CORE_MOD, 343 .idlest_reg_id = 2, 344 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, 345 }, 346 }, 347 .dev_attr = &mmc1_dev_attr, 348 .class = &omap2430_mmc_class, 349 }; 350 351 /* MMC/SD/SDIO2 */ 352 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 353 { .role = "dbck", .clk = "mmchsdb2_fck" }, 354 }; 355 356 static struct omap_hwmod omap2430_mmc2_hwmod = { 357 .name = "mmc2", 358 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 359 .opt_clks = omap2430_mmc2_opt_clks, 360 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 361 .main_clk = "mmchs2_fck", 362 .prcm = { 363 .omap2 = { 364 .module_offs = CORE_MOD, 365 .idlest_reg_id = 2, 366 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 367 }, 368 }, 369 .class = &omap2430_mmc_class, 370 }; 371 372 /* HDQ1W/1-wire */ 373 static struct omap_hwmod omap2430_hdq1w_hwmod = { 374 .name = "hdq1w", 375 .main_clk = "hdq_fck", 376 .prcm = { 377 .omap2 = { 378 .module_offs = CORE_MOD, 379 .idlest_reg_id = 1, 380 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, 381 }, 382 }, 383 .class = &omap2_hdq1w_class, 384 }; 385 386 /* 387 * interfaces 388 */ 389 390 /* L3 -> L4_CORE interface */ 391 /* l3_core -> usbhsotg interface */ 392 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { 393 .master = &omap2430_usbhsotg_hwmod, 394 .slave = &omap2xxx_l3_main_hwmod, 395 .clk = "core_l3_ck", 396 .user = OCP_USER_MPU, 397 }; 398 399 /* L4 CORE -> I2C1 interface */ 400 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 401 .master = &omap2xxx_l4_core_hwmod, 402 .slave = &omap2430_i2c1_hwmod, 403 .clk = "i2c1_ick", 404 .user = OCP_USER_MPU | OCP_USER_SDMA, 405 }; 406 407 /* L4 CORE -> I2C2 interface */ 408 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 409 .master = &omap2xxx_l4_core_hwmod, 410 .slave = &omap2430_i2c2_hwmod, 411 .clk = "i2c2_ick", 412 .user = OCP_USER_MPU | OCP_USER_SDMA, 413 }; 414 415 /* l4_core ->usbhsotg interface */ 416 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 417 .master = &omap2xxx_l4_core_hwmod, 418 .slave = &omap2430_usbhsotg_hwmod, 419 .clk = "usb_l4_ick", 420 .user = OCP_USER_MPU, 421 }; 422 423 /* L4 CORE -> MMC1 interface */ 424 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 425 .master = &omap2xxx_l4_core_hwmod, 426 .slave = &omap2430_mmc1_hwmod, 427 .clk = "mmchs1_ick", 428 .user = OCP_USER_MPU | OCP_USER_SDMA, 429 }; 430 431 /* L4 CORE -> MMC2 interface */ 432 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 433 .master = &omap2xxx_l4_core_hwmod, 434 .slave = &omap2430_mmc2_hwmod, 435 .clk = "mmchs2_ick", 436 .user = OCP_USER_MPU | OCP_USER_SDMA, 437 }; 438 439 /* l4 core -> mcspi3 interface */ 440 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 441 .master = &omap2xxx_l4_core_hwmod, 442 .slave = &omap2430_mcspi3_hwmod, 443 .clk = "mcspi3_ick", 444 .user = OCP_USER_MPU | OCP_USER_SDMA, 445 }; 446 447 /* IVA2 <- L3 interface */ 448 static struct omap_hwmod_ocp_if omap2430_l3__iva = { 449 .master = &omap2xxx_l3_main_hwmod, 450 .slave = &omap2430_iva_hwmod, 451 .clk = "core_l3_ck", 452 .user = OCP_USER_MPU | OCP_USER_SDMA, 453 }; 454 455 /* l4_wkup -> timer1 */ 456 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 457 .master = &omap2xxx_l4_wkup_hwmod, 458 .slave = &omap2xxx_timer1_hwmod, 459 .clk = "gpt1_ick", 460 .user = OCP_USER_MPU | OCP_USER_SDMA, 461 }; 462 463 /* l4_wkup -> wd_timer2 */ 464 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 465 .master = &omap2xxx_l4_wkup_hwmod, 466 .slave = &omap2xxx_wd_timer2_hwmod, 467 .clk = "mpu_wdt_ick", 468 .user = OCP_USER_MPU | OCP_USER_SDMA, 469 }; 470 471 /* l4_wkup -> gpio1 */ 472 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 473 .master = &omap2xxx_l4_wkup_hwmod, 474 .slave = &omap2xxx_gpio1_hwmod, 475 .clk = "gpios_ick", 476 .user = OCP_USER_MPU | OCP_USER_SDMA, 477 }; 478 479 /* l4_wkup -> gpio2 */ 480 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 481 .master = &omap2xxx_l4_wkup_hwmod, 482 .slave = &omap2xxx_gpio2_hwmod, 483 .clk = "gpios_ick", 484 .user = OCP_USER_MPU | OCP_USER_SDMA, 485 }; 486 487 /* l4_wkup -> gpio3 */ 488 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 489 .master = &omap2xxx_l4_wkup_hwmod, 490 .slave = &omap2xxx_gpio3_hwmod, 491 .clk = "gpios_ick", 492 .user = OCP_USER_MPU | OCP_USER_SDMA, 493 }; 494 495 /* l4_wkup -> gpio4 */ 496 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 497 .master = &omap2xxx_l4_wkup_hwmod, 498 .slave = &omap2xxx_gpio4_hwmod, 499 .clk = "gpios_ick", 500 .user = OCP_USER_MPU | OCP_USER_SDMA, 501 }; 502 503 /* l4_core -> gpio5 */ 504 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 505 .master = &omap2xxx_l4_core_hwmod, 506 .slave = &omap2430_gpio5_hwmod, 507 .clk = "gpio5_ick", 508 .user = OCP_USER_MPU | OCP_USER_SDMA, 509 }; 510 511 /* dma_system -> L3 */ 512 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 513 .master = &omap2430_dma_system_hwmod, 514 .slave = &omap2xxx_l3_main_hwmod, 515 .clk = "core_l3_ck", 516 .user = OCP_USER_MPU | OCP_USER_SDMA, 517 }; 518 519 /* l4_core -> dma_system */ 520 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { 521 .master = &omap2xxx_l4_core_hwmod, 522 .slave = &omap2430_dma_system_hwmod, 523 .clk = "sdma_ick", 524 .user = OCP_USER_MPU | OCP_USER_SDMA, 525 }; 526 527 /* l4_core -> mailbox */ 528 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 529 .master = &omap2xxx_l4_core_hwmod, 530 .slave = &omap2430_mailbox_hwmod, 531 .user = OCP_USER_MPU | OCP_USER_SDMA, 532 }; 533 534 /* l4_core -> mcbsp1 */ 535 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { 536 .master = &omap2xxx_l4_core_hwmod, 537 .slave = &omap2430_mcbsp1_hwmod, 538 .clk = "mcbsp1_ick", 539 .user = OCP_USER_MPU | OCP_USER_SDMA, 540 }; 541 542 /* l4_core -> mcbsp2 */ 543 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { 544 .master = &omap2xxx_l4_core_hwmod, 545 .slave = &omap2430_mcbsp2_hwmod, 546 .clk = "mcbsp2_ick", 547 .user = OCP_USER_MPU | OCP_USER_SDMA, 548 }; 549 550 /* l4_core -> mcbsp3 */ 551 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 552 .master = &omap2xxx_l4_core_hwmod, 553 .slave = &omap2430_mcbsp3_hwmod, 554 .clk = "mcbsp3_ick", 555 .user = OCP_USER_MPU | OCP_USER_SDMA, 556 }; 557 558 /* l4_core -> mcbsp4 */ 559 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 560 .master = &omap2xxx_l4_core_hwmod, 561 .slave = &omap2430_mcbsp4_hwmod, 562 .clk = "mcbsp4_ick", 563 .user = OCP_USER_MPU | OCP_USER_SDMA, 564 }; 565 566 /* l4_core -> mcbsp5 */ 567 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 568 .master = &omap2xxx_l4_core_hwmod, 569 .slave = &omap2430_mcbsp5_hwmod, 570 .clk = "mcbsp5_ick", 571 .user = OCP_USER_MPU | OCP_USER_SDMA, 572 }; 573 574 /* l4_core -> hdq1w */ 575 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { 576 .master = &omap2xxx_l4_core_hwmod, 577 .slave = &omap2430_hdq1w_hwmod, 578 .clk = "hdq_ick", 579 .user = OCP_USER_MPU | OCP_USER_SDMA, 580 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 581 }; 582 583 /* l4_wkup -> 32ksync_counter */ 584 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 585 .master = &omap2xxx_l4_wkup_hwmod, 586 .slave = &omap2xxx_counter_32k_hwmod, 587 .clk = "sync_32k_ick", 588 .user = OCP_USER_MPU | OCP_USER_SDMA, 589 }; 590 591 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { 592 .master = &omap2xxx_l3_main_hwmod, 593 .slave = &omap2xxx_gpmc_hwmod, 594 .clk = "core_l3_ck", 595 .user = OCP_USER_MPU | OCP_USER_SDMA, 596 }; 597 598 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { 599 &omap2xxx_l3_main__l4_core, 600 &omap2xxx_mpu__l3_main, 601 &omap2xxx_dss__l3, 602 &omap2430_usbhsotg__l3, 603 &omap2430_l4_core__i2c1, 604 &omap2430_l4_core__i2c2, 605 &omap2xxx_l4_core__l4_wkup, 606 &omap2_l4_core__uart1, 607 &omap2_l4_core__uart2, 608 &omap2_l4_core__uart3, 609 &omap2430_l4_core__usbhsotg, 610 &omap2430_l4_core__mmc1, 611 &omap2430_l4_core__mmc2, 612 &omap2xxx_l4_core__mcspi1, 613 &omap2xxx_l4_core__mcspi2, 614 &omap2430_l4_core__mcspi3, 615 &omap2430_l3__iva, 616 &omap2430_l4_wkup__timer1, 617 &omap2xxx_l4_core__timer2, 618 &omap2xxx_l4_core__timer3, 619 &omap2xxx_l4_core__timer4, 620 &omap2xxx_l4_core__timer5, 621 &omap2xxx_l4_core__timer6, 622 &omap2xxx_l4_core__timer7, 623 &omap2xxx_l4_core__timer8, 624 &omap2xxx_l4_core__timer9, 625 &omap2xxx_l4_core__timer10, 626 &omap2xxx_l4_core__timer11, 627 &omap2xxx_l4_core__timer12, 628 &omap2430_l4_wkup__wd_timer2, 629 &omap2xxx_l4_core__dss, 630 &omap2xxx_l4_core__dss_dispc, 631 &omap2xxx_l4_core__dss_rfbi, 632 &omap2xxx_l4_core__dss_venc, 633 &omap2430_l4_wkup__gpio1, 634 &omap2430_l4_wkup__gpio2, 635 &omap2430_l4_wkup__gpio3, 636 &omap2430_l4_wkup__gpio4, 637 &omap2430_l4_core__gpio5, 638 &omap2430_dma_system__l3, 639 &omap2430_l4_core__dma_system, 640 &omap2430_l4_core__mailbox, 641 &omap2430_l4_core__mcbsp1, 642 &omap2430_l4_core__mcbsp2, 643 &omap2430_l4_core__mcbsp3, 644 &omap2430_l4_core__mcbsp4, 645 &omap2430_l4_core__mcbsp5, 646 &omap2430_l4_core__hdq1w, 647 &omap2xxx_l4_core__rng, 648 &omap2xxx_l4_core__sham, 649 &omap2xxx_l4_core__aes, 650 &omap2430_l4_wkup__counter_32k, 651 &omap2430_l3__gpmc, 652 NULL, 653 }; 654 655 int __init omap2430_hwmod_init(void) 656 { 657 omap_hwmod_init(); 658 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); 659 } 660