1 /* 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * XXX handle crossbar/shared link difference for L3? 13 * XXX these should be marked initdata for multi-OMAP kernels 14 */ 15 16 #include <linux/platform_data/i2c-omap.h> 17 #include <linux/omap-dma.h> 18 19 #include "omap_hwmod.h" 20 #include "l3_2xxx.h" 21 #include "l4_2xxx.h" 22 23 #include "omap_hwmod_common_data.h" 24 25 #include "cm-regbits-24xx.h" 26 #include "prm-regbits-24xx.h" 27 #include "i2c.h" 28 #include "mmc.h" 29 #include "serial.h" 30 #include "wd_timer.h" 31 32 /* 33 * OMAP2420 hardware module integration data 34 * 35 * All of the data in this section should be autogeneratable from the 36 * TI hardware database or other technical documentation. Data that 37 * is driver-specific or driver-kernel integration-specific belongs 38 * elsewhere. 39 */ 40 41 /* 42 * IP blocks 43 */ 44 45 /* IVA1 (IVA1) */ 46 static struct omap_hwmod_class iva1_hwmod_class = { 47 .name = "iva1", 48 }; 49 50 static struct omap_hwmod_rst_info omap2420_iva_resets[] = { 51 { .name = "iva", .rst_shift = 8 }, 52 }; 53 54 static struct omap_hwmod omap2420_iva_hwmod = { 55 .name = "iva", 56 .class = &iva1_hwmod_class, 57 .clkdm_name = "iva1_clkdm", 58 .rst_lines = omap2420_iva_resets, 59 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), 60 .main_clk = "iva1_ifck", 61 }; 62 63 /* DSP */ 64 static struct omap_hwmod_class dsp_hwmod_class = { 65 .name = "dsp", 66 }; 67 68 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { 69 { .name = "logic", .rst_shift = 0 }, 70 { .name = "mmu", .rst_shift = 1 }, 71 }; 72 73 static struct omap_hwmod omap2420_dsp_hwmod = { 74 .name = "dsp", 75 .class = &dsp_hwmod_class, 76 .clkdm_name = "dsp_clkdm", 77 .rst_lines = omap2420_dsp_resets, 78 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), 79 .main_clk = "dsp_fck", 80 }; 81 82 /* I2C common */ 83 static struct omap_hwmod_class_sysconfig i2c_sysc = { 84 .rev_offs = 0x00, 85 .sysc_offs = 0x20, 86 .syss_offs = 0x10, 87 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 88 .sysc_fields = &omap_hwmod_sysc_type1, 89 }; 90 91 static struct omap_hwmod_class i2c_class = { 92 .name = "i2c", 93 .sysc = &i2c_sysc, 94 .rev = OMAP_I2C_IP_VERSION_1, 95 .reset = &omap_i2c_reset, 96 }; 97 98 /* I2C1 */ 99 static struct omap_hwmod omap2420_i2c1_hwmod = { 100 .name = "i2c1", 101 .main_clk = "i2c1_fck", 102 .prcm = { 103 .omap2 = { 104 .module_offs = CORE_MOD, 105 .idlest_reg_id = 1, 106 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, 107 }, 108 }, 109 .class = &i2c_class, 110 /* 111 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state 112 * while a transfer is active seems to cause the I2C block to 113 * timeout. Why? Good question." 114 */ 115 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI), 116 }; 117 118 /* I2C2 */ 119 static struct omap_hwmod omap2420_i2c2_hwmod = { 120 .name = "i2c2", 121 .main_clk = "i2c2_fck", 122 .prcm = { 123 .omap2 = { 124 .module_offs = CORE_MOD, 125 .idlest_reg_id = 1, 126 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, 127 }, 128 }, 129 .class = &i2c_class, 130 .flags = HWMOD_16BIT_REG, 131 }; 132 133 /* dma attributes */ 134 static struct omap_dma_dev_attr dma_dev_attr = { 135 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 136 IS_CSSA_32 | IS_CDSA_32, 137 .lch_count = 32, 138 }; 139 140 static struct omap_hwmod omap2420_dma_system_hwmod = { 141 .name = "dma", 142 .class = &omap2xxx_dma_hwmod_class, 143 .main_clk = "core_l3_ck", 144 .dev_attr = &dma_dev_attr, 145 .flags = HWMOD_NO_IDLEST, 146 }; 147 148 /* mailbox */ 149 static struct omap_hwmod omap2420_mailbox_hwmod = { 150 .name = "mailbox", 151 .class = &omap2xxx_mailbox_hwmod_class, 152 .main_clk = "mailboxes_ick", 153 .prcm = { 154 .omap2 = { 155 .module_offs = CORE_MOD, 156 .idlest_reg_id = 1, 157 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 158 }, 159 }, 160 }; 161 162 /* 163 * 'mcbsp' class 164 * multi channel buffered serial port controller 165 */ 166 167 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { 168 .name = "mcbsp", 169 }; 170 171 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { 172 { .role = "pad_fck", .clk = "mcbsp_clks" }, 173 { .role = "prcm_fck", .clk = "func_96m_ck" }, 174 }; 175 176 /* mcbsp1 */ 177 static struct omap_hwmod omap2420_mcbsp1_hwmod = { 178 .name = "mcbsp1", 179 .class = &omap2420_mcbsp_hwmod_class, 180 .main_clk = "mcbsp1_fck", 181 .prcm = { 182 .omap2 = { 183 .module_offs = CORE_MOD, 184 .idlest_reg_id = 1, 185 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 186 }, 187 }, 188 .opt_clks = mcbsp_opt_clks, 189 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 190 }; 191 192 /* mcbsp2 */ 193 static struct omap_hwmod omap2420_mcbsp2_hwmod = { 194 .name = "mcbsp2", 195 .class = &omap2420_mcbsp_hwmod_class, 196 .main_clk = "mcbsp2_fck", 197 .prcm = { 198 .omap2 = { 199 .module_offs = CORE_MOD, 200 .idlest_reg_id = 1, 201 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 202 }, 203 }, 204 .opt_clks = mcbsp_opt_clks, 205 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 206 }; 207 208 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { 209 .rev_offs = 0x3c, 210 .sysc_offs = 0x64, 211 .syss_offs = 0x68, 212 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 213 .sysc_fields = &omap_hwmod_sysc_type1, 214 }; 215 216 static struct omap_hwmod_class omap2420_msdi_hwmod_class = { 217 .name = "msdi", 218 .sysc = &omap2420_msdi_sysc, 219 .reset = &omap_msdi_reset, 220 }; 221 222 /* msdi1 */ 223 static struct omap_hwmod omap2420_msdi1_hwmod = { 224 .name = "msdi1", 225 .class = &omap2420_msdi_hwmod_class, 226 .main_clk = "mmc_fck", 227 .prcm = { 228 .omap2 = { 229 .module_offs = CORE_MOD, 230 .idlest_reg_id = 1, 231 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT, 232 }, 233 }, 234 .flags = HWMOD_16BIT_REG, 235 }; 236 237 /* HDQ1W/1-wire */ 238 static struct omap_hwmod omap2420_hdq1w_hwmod = { 239 .name = "hdq1w", 240 .main_clk = "hdq_fck", 241 .prcm = { 242 .omap2 = { 243 .module_offs = CORE_MOD, 244 .idlest_reg_id = 1, 245 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, 246 }, 247 }, 248 .class = &omap2_hdq1w_class, 249 }; 250 251 /* 252 * interfaces 253 */ 254 255 /* L4 CORE -> I2C1 interface */ 256 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 257 .master = &omap2xxx_l4_core_hwmod, 258 .slave = &omap2420_i2c1_hwmod, 259 .clk = "i2c1_ick", 260 .user = OCP_USER_MPU | OCP_USER_SDMA, 261 }; 262 263 /* L4 CORE -> I2C2 interface */ 264 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 265 .master = &omap2xxx_l4_core_hwmod, 266 .slave = &omap2420_i2c2_hwmod, 267 .clk = "i2c2_ick", 268 .user = OCP_USER_MPU | OCP_USER_SDMA, 269 }; 270 271 /* IVA <- L3 interface */ 272 static struct omap_hwmod_ocp_if omap2420_l3__iva = { 273 .master = &omap2xxx_l3_main_hwmod, 274 .slave = &omap2420_iva_hwmod, 275 .clk = "core_l3_ck", 276 .user = OCP_USER_MPU | OCP_USER_SDMA, 277 }; 278 279 /* DSP <- L3 interface */ 280 static struct omap_hwmod_ocp_if omap2420_l3__dsp = { 281 .master = &omap2xxx_l3_main_hwmod, 282 .slave = &omap2420_dsp_hwmod, 283 .clk = "dsp_ick", 284 .user = OCP_USER_MPU | OCP_USER_SDMA, 285 }; 286 287 /* l4_wkup -> timer1 */ 288 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 289 .master = &omap2xxx_l4_wkup_hwmod, 290 .slave = &omap2xxx_timer1_hwmod, 291 .clk = "gpt1_ick", 292 .user = OCP_USER_MPU | OCP_USER_SDMA, 293 }; 294 295 /* l4_wkup -> wd_timer2 */ 296 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 297 .master = &omap2xxx_l4_wkup_hwmod, 298 .slave = &omap2xxx_wd_timer2_hwmod, 299 .clk = "mpu_wdt_ick", 300 .user = OCP_USER_MPU | OCP_USER_SDMA, 301 }; 302 303 /* l4_wkup -> gpio1 */ 304 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 305 .master = &omap2xxx_l4_wkup_hwmod, 306 .slave = &omap2xxx_gpio1_hwmod, 307 .clk = "gpios_ick", 308 .user = OCP_USER_MPU | OCP_USER_SDMA, 309 }; 310 311 /* l4_wkup -> gpio2 */ 312 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 313 .master = &omap2xxx_l4_wkup_hwmod, 314 .slave = &omap2xxx_gpio2_hwmod, 315 .clk = "gpios_ick", 316 .user = OCP_USER_MPU | OCP_USER_SDMA, 317 }; 318 319 /* l4_wkup -> gpio3 */ 320 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 321 .master = &omap2xxx_l4_wkup_hwmod, 322 .slave = &omap2xxx_gpio3_hwmod, 323 .clk = "gpios_ick", 324 .user = OCP_USER_MPU | OCP_USER_SDMA, 325 }; 326 327 /* l4_wkup -> gpio4 */ 328 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 329 .master = &omap2xxx_l4_wkup_hwmod, 330 .slave = &omap2xxx_gpio4_hwmod, 331 .clk = "gpios_ick", 332 .user = OCP_USER_MPU | OCP_USER_SDMA, 333 }; 334 335 /* dma_system -> L3 */ 336 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 337 .master = &omap2420_dma_system_hwmod, 338 .slave = &omap2xxx_l3_main_hwmod, 339 .clk = "core_l3_ck", 340 .user = OCP_USER_MPU | OCP_USER_SDMA, 341 }; 342 343 /* l4_core -> dma_system */ 344 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { 345 .master = &omap2xxx_l4_core_hwmod, 346 .slave = &omap2420_dma_system_hwmod, 347 .clk = "sdma_ick", 348 .user = OCP_USER_MPU | OCP_USER_SDMA, 349 }; 350 351 /* l4_core -> mailbox */ 352 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 353 .master = &omap2xxx_l4_core_hwmod, 354 .slave = &omap2420_mailbox_hwmod, 355 .user = OCP_USER_MPU | OCP_USER_SDMA, 356 }; 357 358 /* l4_core -> mcbsp1 */ 359 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { 360 .master = &omap2xxx_l4_core_hwmod, 361 .slave = &omap2420_mcbsp1_hwmod, 362 .clk = "mcbsp1_ick", 363 .user = OCP_USER_MPU | OCP_USER_SDMA, 364 }; 365 366 /* l4_core -> mcbsp2 */ 367 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 368 .master = &omap2xxx_l4_core_hwmod, 369 .slave = &omap2420_mcbsp2_hwmod, 370 .clk = "mcbsp2_ick", 371 .user = OCP_USER_MPU | OCP_USER_SDMA, 372 }; 373 374 /* l4_core -> msdi1 */ 375 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { 376 .master = &omap2xxx_l4_core_hwmod, 377 .slave = &omap2420_msdi1_hwmod, 378 .clk = "mmc_ick", 379 .user = OCP_USER_MPU | OCP_USER_SDMA, 380 }; 381 382 /* l4_core -> hdq1w interface */ 383 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { 384 .master = &omap2xxx_l4_core_hwmod, 385 .slave = &omap2420_hdq1w_hwmod, 386 .clk = "hdq_ick", 387 .user = OCP_USER_MPU | OCP_USER_SDMA, 388 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 389 }; 390 391 392 /* l4_wkup -> 32ksync_counter */ 393 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { 394 .master = &omap2xxx_l4_wkup_hwmod, 395 .slave = &omap2xxx_counter_32k_hwmod, 396 .clk = "sync_32k_ick", 397 .user = OCP_USER_MPU | OCP_USER_SDMA, 398 }; 399 400 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { 401 .master = &omap2xxx_l3_main_hwmod, 402 .slave = &omap2xxx_gpmc_hwmod, 403 .clk = "core_l3_ck", 404 .user = OCP_USER_MPU | OCP_USER_SDMA, 405 }; 406 407 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { 408 &omap2xxx_l3_main__l4_core, 409 &omap2xxx_mpu__l3_main, 410 &omap2xxx_dss__l3, 411 &omap2xxx_l4_core__mcspi1, 412 &omap2xxx_l4_core__mcspi2, 413 &omap2xxx_l4_core__l4_wkup, 414 &omap2_l4_core__uart1, 415 &omap2_l4_core__uart2, 416 &omap2_l4_core__uart3, 417 &omap2420_l4_core__i2c1, 418 &omap2420_l4_core__i2c2, 419 &omap2420_l3__iva, 420 &omap2420_l3__dsp, 421 &omap2420_l4_wkup__timer1, 422 &omap2xxx_l4_core__timer2, 423 &omap2xxx_l4_core__timer3, 424 &omap2xxx_l4_core__timer4, 425 &omap2xxx_l4_core__timer5, 426 &omap2xxx_l4_core__timer6, 427 &omap2xxx_l4_core__timer7, 428 &omap2xxx_l4_core__timer8, 429 &omap2xxx_l4_core__timer9, 430 &omap2xxx_l4_core__timer10, 431 &omap2xxx_l4_core__timer11, 432 &omap2xxx_l4_core__timer12, 433 &omap2420_l4_wkup__wd_timer2, 434 &omap2xxx_l4_core__dss, 435 &omap2xxx_l4_core__dss_dispc, 436 &omap2xxx_l4_core__dss_rfbi, 437 &omap2xxx_l4_core__dss_venc, 438 &omap2420_l4_wkup__gpio1, 439 &omap2420_l4_wkup__gpio2, 440 &omap2420_l4_wkup__gpio3, 441 &omap2420_l4_wkup__gpio4, 442 &omap2420_dma_system__l3, 443 &omap2420_l4_core__dma_system, 444 &omap2420_l4_core__mailbox, 445 &omap2420_l4_core__mcbsp1, 446 &omap2420_l4_core__mcbsp2, 447 &omap2420_l4_core__msdi1, 448 &omap2xxx_l4_core__rng, 449 &omap2xxx_l4_core__sham, 450 &omap2xxx_l4_core__aes, 451 &omap2420_l4_core__hdq1w, 452 &omap2420_l4_wkup__counter_32k, 453 &omap2420_l3__gpmc, 454 NULL, 455 }; 456 457 int __init omap2420_hwmod_init(void) 458 { 459 omap_hwmod_init(); 460 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); 461 } 462