1 /* 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * XXX handle crossbar/shared link difference for L3? 13 * XXX these should be marked initdata for multi-OMAP kernels 14 */ 15 16 #include <linux/i2c-omap.h> 17 #include <linux/platform_data/spi-omap2-mcspi.h> 18 #include <linux/omap-dma.h> 19 #include <plat/dmtimer.h> 20 21 #include "omap_hwmod.h" 22 #include "l3_2xxx.h" 23 #include "l4_2xxx.h" 24 25 #include "omap_hwmod_common_data.h" 26 27 #include "cm-regbits-24xx.h" 28 #include "prm-regbits-24xx.h" 29 #include "i2c.h" 30 #include "mmc.h" 31 #include "serial.h" 32 #include "wd_timer.h" 33 34 /* 35 * OMAP2420 hardware module integration data 36 * 37 * All of the data in this section should be autogeneratable from the 38 * TI hardware database or other technical documentation. Data that 39 * is driver-specific or driver-kernel integration-specific belongs 40 * elsewhere. 41 */ 42 43 /* 44 * IP blocks 45 */ 46 47 /* IVA1 (IVA1) */ 48 static struct omap_hwmod_class iva1_hwmod_class = { 49 .name = "iva1", 50 }; 51 52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = { 53 { .name = "iva", .rst_shift = 8 }, 54 }; 55 56 static struct omap_hwmod omap2420_iva_hwmod = { 57 .name = "iva", 58 .class = &iva1_hwmod_class, 59 .clkdm_name = "iva1_clkdm", 60 .rst_lines = omap2420_iva_resets, 61 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), 62 .main_clk = "iva1_ifck", 63 }; 64 65 /* DSP */ 66 static struct omap_hwmod_class dsp_hwmod_class = { 67 .name = "dsp", 68 }; 69 70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { 71 { .name = "logic", .rst_shift = 0 }, 72 { .name = "mmu", .rst_shift = 1 }, 73 }; 74 75 static struct omap_hwmod omap2420_dsp_hwmod = { 76 .name = "dsp", 77 .class = &dsp_hwmod_class, 78 .clkdm_name = "dsp_clkdm", 79 .rst_lines = omap2420_dsp_resets, 80 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), 81 .main_clk = "dsp_fck", 82 }; 83 84 /* I2C common */ 85 static struct omap_hwmod_class_sysconfig i2c_sysc = { 86 .rev_offs = 0x00, 87 .sysc_offs = 0x20, 88 .syss_offs = 0x10, 89 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 90 .sysc_fields = &omap_hwmod_sysc_type1, 91 }; 92 93 static struct omap_hwmod_class i2c_class = { 94 .name = "i2c", 95 .sysc = &i2c_sysc, 96 .rev = OMAP_I2C_IP_VERSION_1, 97 .reset = &omap_i2c_reset, 98 }; 99 100 static struct omap_i2c_dev_attr i2c_dev_attr = { 101 .flags = OMAP_I2C_FLAG_NO_FIFO | 102 OMAP_I2C_FLAG_SIMPLE_CLOCK | 103 OMAP_I2C_FLAG_16BIT_DATA_REG | 104 OMAP_I2C_FLAG_BUS_SHIFT_2, 105 }; 106 107 /* I2C1 */ 108 static struct omap_hwmod omap2420_i2c1_hwmod = { 109 .name = "i2c1", 110 .main_clk = "i2c1_fck", 111 .prcm = { 112 .omap2 = { 113 .module_offs = CORE_MOD, 114 .prcm_reg_id = 1, 115 .module_bit = OMAP2420_EN_I2C1_SHIFT, 116 .idlest_reg_id = 1, 117 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, 118 }, 119 }, 120 .class = &i2c_class, 121 .dev_attr = &i2c_dev_attr, 122 /* 123 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state 124 * while a transfer is active seems to cause the I2C block to 125 * timeout. Why? Good question." 126 */ 127 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI), 128 }; 129 130 /* I2C2 */ 131 static struct omap_hwmod omap2420_i2c2_hwmod = { 132 .name = "i2c2", 133 .main_clk = "i2c2_fck", 134 .prcm = { 135 .omap2 = { 136 .module_offs = CORE_MOD, 137 .prcm_reg_id = 1, 138 .module_bit = OMAP2420_EN_I2C2_SHIFT, 139 .idlest_reg_id = 1, 140 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, 141 }, 142 }, 143 .class = &i2c_class, 144 .dev_attr = &i2c_dev_attr, 145 .flags = HWMOD_16BIT_REG, 146 }; 147 148 /* dma attributes */ 149 static struct omap_dma_dev_attr dma_dev_attr = { 150 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 151 IS_CSSA_32 | IS_CDSA_32, 152 .lch_count = 32, 153 }; 154 155 static struct omap_hwmod omap2420_dma_system_hwmod = { 156 .name = "dma", 157 .class = &omap2xxx_dma_hwmod_class, 158 .mpu_irqs = omap2_dma_system_irqs, 159 .main_clk = "core_l3_ck", 160 .dev_attr = &dma_dev_attr, 161 .flags = HWMOD_NO_IDLEST, 162 }; 163 164 /* mailbox */ 165 static struct omap_hwmod omap2420_mailbox_hwmod = { 166 .name = "mailbox", 167 .class = &omap2xxx_mailbox_hwmod_class, 168 .main_clk = "mailboxes_ick", 169 .prcm = { 170 .omap2 = { 171 .prcm_reg_id = 1, 172 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 173 .module_offs = CORE_MOD, 174 .idlest_reg_id = 1, 175 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 176 }, 177 }, 178 }; 179 180 /* 181 * 'mcbsp' class 182 * multi channel buffered serial port controller 183 */ 184 185 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { 186 .name = "mcbsp", 187 }; 188 189 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { 190 { .role = "pad_fck", .clk = "mcbsp_clks" }, 191 { .role = "prcm_fck", .clk = "func_96m_ck" }, 192 }; 193 194 /* mcbsp1 */ 195 static struct omap_hwmod omap2420_mcbsp1_hwmod = { 196 .name = "mcbsp1", 197 .class = &omap2420_mcbsp_hwmod_class, 198 .main_clk = "mcbsp1_fck", 199 .prcm = { 200 .omap2 = { 201 .prcm_reg_id = 1, 202 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, 203 .module_offs = CORE_MOD, 204 .idlest_reg_id = 1, 205 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 206 }, 207 }, 208 .opt_clks = mcbsp_opt_clks, 209 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 210 }; 211 212 /* mcbsp2 */ 213 static struct omap_hwmod omap2420_mcbsp2_hwmod = { 214 .name = "mcbsp2", 215 .class = &omap2420_mcbsp_hwmod_class, 216 .main_clk = "mcbsp2_fck", 217 .prcm = { 218 .omap2 = { 219 .prcm_reg_id = 1, 220 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, 221 .module_offs = CORE_MOD, 222 .idlest_reg_id = 1, 223 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 224 }, 225 }, 226 .opt_clks = mcbsp_opt_clks, 227 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 228 }; 229 230 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { 231 .rev_offs = 0x3c, 232 .sysc_offs = 0x64, 233 .syss_offs = 0x68, 234 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 235 .sysc_fields = &omap_hwmod_sysc_type1, 236 }; 237 238 static struct omap_hwmod_class omap2420_msdi_hwmod_class = { 239 .name = "msdi", 240 .sysc = &omap2420_msdi_sysc, 241 .reset = &omap_msdi_reset, 242 }; 243 244 /* msdi1 */ 245 static struct omap_hwmod omap2420_msdi1_hwmod = { 246 .name = "msdi1", 247 .class = &omap2420_msdi_hwmod_class, 248 .main_clk = "mmc_fck", 249 .prcm = { 250 .omap2 = { 251 .prcm_reg_id = 1, 252 .module_bit = OMAP2420_EN_MMC_SHIFT, 253 .module_offs = CORE_MOD, 254 .idlest_reg_id = 1, 255 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT, 256 }, 257 }, 258 .flags = HWMOD_16BIT_REG, 259 }; 260 261 /* HDQ1W/1-wire */ 262 static struct omap_hwmod omap2420_hdq1w_hwmod = { 263 .name = "hdq1w", 264 .main_clk = "hdq_fck", 265 .prcm = { 266 .omap2 = { 267 .module_offs = CORE_MOD, 268 .prcm_reg_id = 1, 269 .module_bit = OMAP24XX_EN_HDQ_SHIFT, 270 .idlest_reg_id = 1, 271 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, 272 }, 273 }, 274 .class = &omap2_hdq1w_class, 275 }; 276 277 /* 278 * interfaces 279 */ 280 281 /* L4 CORE -> I2C1 interface */ 282 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 283 .master = &omap2xxx_l4_core_hwmod, 284 .slave = &omap2420_i2c1_hwmod, 285 .clk = "i2c1_ick", 286 .user = OCP_USER_MPU | OCP_USER_SDMA, 287 }; 288 289 /* L4 CORE -> I2C2 interface */ 290 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 291 .master = &omap2xxx_l4_core_hwmod, 292 .slave = &omap2420_i2c2_hwmod, 293 .clk = "i2c2_ick", 294 .user = OCP_USER_MPU | OCP_USER_SDMA, 295 }; 296 297 /* IVA <- L3 interface */ 298 static struct omap_hwmod_ocp_if omap2420_l3__iva = { 299 .master = &omap2xxx_l3_main_hwmod, 300 .slave = &omap2420_iva_hwmod, 301 .clk = "core_l3_ck", 302 .user = OCP_USER_MPU | OCP_USER_SDMA, 303 }; 304 305 /* DSP <- L3 interface */ 306 static struct omap_hwmod_ocp_if omap2420_l3__dsp = { 307 .master = &omap2xxx_l3_main_hwmod, 308 .slave = &omap2420_dsp_hwmod, 309 .clk = "dsp_ick", 310 .user = OCP_USER_MPU | OCP_USER_SDMA, 311 }; 312 313 /* l4_wkup -> timer1 */ 314 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 315 .master = &omap2xxx_l4_wkup_hwmod, 316 .slave = &omap2xxx_timer1_hwmod, 317 .clk = "gpt1_ick", 318 .user = OCP_USER_MPU | OCP_USER_SDMA, 319 }; 320 321 /* l4_wkup -> wd_timer2 */ 322 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 323 .master = &omap2xxx_l4_wkup_hwmod, 324 .slave = &omap2xxx_wd_timer2_hwmod, 325 .clk = "mpu_wdt_ick", 326 .user = OCP_USER_MPU | OCP_USER_SDMA, 327 }; 328 329 /* l4_wkup -> gpio1 */ 330 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 331 .master = &omap2xxx_l4_wkup_hwmod, 332 .slave = &omap2xxx_gpio1_hwmod, 333 .clk = "gpios_ick", 334 .user = OCP_USER_MPU | OCP_USER_SDMA, 335 }; 336 337 /* l4_wkup -> gpio2 */ 338 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 339 .master = &omap2xxx_l4_wkup_hwmod, 340 .slave = &omap2xxx_gpio2_hwmod, 341 .clk = "gpios_ick", 342 .user = OCP_USER_MPU | OCP_USER_SDMA, 343 }; 344 345 /* l4_wkup -> gpio3 */ 346 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 347 .master = &omap2xxx_l4_wkup_hwmod, 348 .slave = &omap2xxx_gpio3_hwmod, 349 .clk = "gpios_ick", 350 .user = OCP_USER_MPU | OCP_USER_SDMA, 351 }; 352 353 /* l4_wkup -> gpio4 */ 354 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 355 .master = &omap2xxx_l4_wkup_hwmod, 356 .slave = &omap2xxx_gpio4_hwmod, 357 .clk = "gpios_ick", 358 .user = OCP_USER_MPU | OCP_USER_SDMA, 359 }; 360 361 /* dma_system -> L3 */ 362 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 363 .master = &omap2420_dma_system_hwmod, 364 .slave = &omap2xxx_l3_main_hwmod, 365 .clk = "core_l3_ck", 366 .user = OCP_USER_MPU | OCP_USER_SDMA, 367 }; 368 369 /* l4_core -> dma_system */ 370 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { 371 .master = &omap2xxx_l4_core_hwmod, 372 .slave = &omap2420_dma_system_hwmod, 373 .clk = "sdma_ick", 374 .addr = omap2_dma_system_addrs, 375 .user = OCP_USER_MPU | OCP_USER_SDMA, 376 }; 377 378 /* l4_core -> mailbox */ 379 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 380 .master = &omap2xxx_l4_core_hwmod, 381 .slave = &omap2420_mailbox_hwmod, 382 .user = OCP_USER_MPU | OCP_USER_SDMA, 383 }; 384 385 /* l4_core -> mcbsp1 */ 386 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { 387 .master = &omap2xxx_l4_core_hwmod, 388 .slave = &omap2420_mcbsp1_hwmod, 389 .clk = "mcbsp1_ick", 390 .user = OCP_USER_MPU | OCP_USER_SDMA, 391 }; 392 393 /* l4_core -> mcbsp2 */ 394 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 395 .master = &omap2xxx_l4_core_hwmod, 396 .slave = &omap2420_mcbsp2_hwmod, 397 .clk = "mcbsp2_ick", 398 .user = OCP_USER_MPU | OCP_USER_SDMA, 399 }; 400 401 /* l4_core -> msdi1 */ 402 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { 403 .master = &omap2xxx_l4_core_hwmod, 404 .slave = &omap2420_msdi1_hwmod, 405 .clk = "mmc_ick", 406 .user = OCP_USER_MPU | OCP_USER_SDMA, 407 }; 408 409 /* l4_core -> hdq1w interface */ 410 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { 411 .master = &omap2xxx_l4_core_hwmod, 412 .slave = &omap2420_hdq1w_hwmod, 413 .clk = "hdq_ick", 414 .user = OCP_USER_MPU | OCP_USER_SDMA, 415 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 416 }; 417 418 419 /* l4_wkup -> 32ksync_counter */ 420 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { 421 .master = &omap2xxx_l4_wkup_hwmod, 422 .slave = &omap2xxx_counter_32k_hwmod, 423 .clk = "sync_32k_ick", 424 .user = OCP_USER_MPU | OCP_USER_SDMA, 425 }; 426 427 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { 428 .master = &omap2xxx_l3_main_hwmod, 429 .slave = &omap2xxx_gpmc_hwmod, 430 .clk = "core_l3_ck", 431 .user = OCP_USER_MPU | OCP_USER_SDMA, 432 }; 433 434 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { 435 &omap2xxx_l3_main__l4_core, 436 &omap2xxx_mpu__l3_main, 437 &omap2xxx_dss__l3, 438 &omap2xxx_l4_core__mcspi1, 439 &omap2xxx_l4_core__mcspi2, 440 &omap2xxx_l4_core__l4_wkup, 441 &omap2_l4_core__uart1, 442 &omap2_l4_core__uart2, 443 &omap2_l4_core__uart3, 444 &omap2420_l4_core__i2c1, 445 &omap2420_l4_core__i2c2, 446 &omap2420_l3__iva, 447 &omap2420_l3__dsp, 448 &omap2420_l4_wkup__timer1, 449 &omap2xxx_l4_core__timer2, 450 &omap2xxx_l4_core__timer3, 451 &omap2xxx_l4_core__timer4, 452 &omap2xxx_l4_core__timer5, 453 &omap2xxx_l4_core__timer6, 454 &omap2xxx_l4_core__timer7, 455 &omap2xxx_l4_core__timer8, 456 &omap2xxx_l4_core__timer9, 457 &omap2xxx_l4_core__timer10, 458 &omap2xxx_l4_core__timer11, 459 &omap2xxx_l4_core__timer12, 460 &omap2420_l4_wkup__wd_timer2, 461 &omap2xxx_l4_core__dss, 462 &omap2xxx_l4_core__dss_dispc, 463 &omap2xxx_l4_core__dss_rfbi, 464 &omap2xxx_l4_core__dss_venc, 465 &omap2420_l4_wkup__gpio1, 466 &omap2420_l4_wkup__gpio2, 467 &omap2420_l4_wkup__gpio3, 468 &omap2420_l4_wkup__gpio4, 469 &omap2420_dma_system__l3, 470 &omap2420_l4_core__dma_system, 471 &omap2420_l4_core__mailbox, 472 &omap2420_l4_core__mcbsp1, 473 &omap2420_l4_core__mcbsp2, 474 &omap2420_l4_core__msdi1, 475 &omap2xxx_l4_core__rng, 476 &omap2xxx_l4_core__sham, 477 &omap2xxx_l4_core__aes, 478 &omap2420_l4_core__hdq1w, 479 &omap2420_l4_wkup__counter_32k, 480 &omap2420_l3__gpmc, 481 NULL, 482 }; 483 484 int __init omap2420_hwmod_init(void) 485 { 486 omap_hwmod_init(); 487 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); 488 } 489