1 /* 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Paul Walmsley 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * XXX handle crossbar/shared link difference for L3? 12 * XXX these should be marked initdata for multi-OMAP kernels 13 */ 14 #include <plat/omap_hwmod.h> 15 #include <mach/irqs.h> 16 #include <plat/cpu.h> 17 #include <plat/dma.h> 18 #include <plat/serial.h> 19 #include <plat/i2c.h> 20 #include <plat/gpio.h> 21 #include <plat/mcspi.h> 22 #include <plat/dmtimer.h> 23 #include <plat/l3_2xxx.h> 24 #include <plat/l4_2xxx.h> 25 26 #include "omap_hwmod_common_data.h" 27 28 #include "cm-regbits-24xx.h" 29 #include "prm-regbits-24xx.h" 30 #include "wd_timer.h" 31 32 /* 33 * OMAP2420 hardware module integration data 34 * 35 * ALl of the data in this section should be autogeneratable from the 36 * TI hardware database or other technical documentation. Data that 37 * is driver-specific or driver-kernel integration-specific belongs 38 * elsewhere. 39 */ 40 41 static struct omap_hwmod omap2420_mpu_hwmod; 42 static struct omap_hwmod omap2420_iva_hwmod; 43 static struct omap_hwmod omap2420_l3_main_hwmod; 44 static struct omap_hwmod omap2420_l4_core_hwmod; 45 static struct omap_hwmod omap2420_dss_core_hwmod; 46 static struct omap_hwmod omap2420_dss_dispc_hwmod; 47 static struct omap_hwmod omap2420_dss_rfbi_hwmod; 48 static struct omap_hwmod omap2420_dss_venc_hwmod; 49 static struct omap_hwmod omap2420_wd_timer2_hwmod; 50 static struct omap_hwmod omap2420_gpio1_hwmod; 51 static struct omap_hwmod omap2420_gpio2_hwmod; 52 static struct omap_hwmod omap2420_gpio3_hwmod; 53 static struct omap_hwmod omap2420_gpio4_hwmod; 54 static struct omap_hwmod omap2420_dma_system_hwmod; 55 static struct omap_hwmod omap2420_mcspi1_hwmod; 56 static struct omap_hwmod omap2420_mcspi2_hwmod; 57 58 /* L3 -> L4_CORE interface */ 59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { 60 .master = &omap2420_l3_main_hwmod, 61 .slave = &omap2420_l4_core_hwmod, 62 .user = OCP_USER_MPU | OCP_USER_SDMA, 63 }; 64 65 /* MPU -> L3 interface */ 66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { 67 .master = &omap2420_mpu_hwmod, 68 .slave = &omap2420_l3_main_hwmod, 69 .user = OCP_USER_MPU, 70 }; 71 72 /* Slave interfaces on the L3 interconnect */ 73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { 74 &omap2420_mpu__l3_main, 75 }; 76 77 /* DSS -> l3 */ 78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = { 79 .master = &omap2420_dss_core_hwmod, 80 .slave = &omap2420_l3_main_hwmod, 81 .fw = { 82 .omap2 = { 83 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 84 .flags = OMAP_FIREWALL_L3, 85 } 86 }, 87 .user = OCP_USER_MPU | OCP_USER_SDMA, 88 }; 89 90 /* Master interfaces on the L3 interconnect */ 91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { 92 &omap2420_l3_main__l4_core, 93 }; 94 95 /* L3 */ 96 static struct omap_hwmod omap2420_l3_main_hwmod = { 97 .name = "l3_main", 98 .class = &l3_hwmod_class, 99 .masters = omap2420_l3_main_masters, 100 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), 101 .slaves = omap2420_l3_main_slaves, 102 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), 103 .flags = HWMOD_NO_IDLEST, 104 }; 105 106 static struct omap_hwmod omap2420_l4_wkup_hwmod; 107 static struct omap_hwmod omap2420_uart1_hwmod; 108 static struct omap_hwmod omap2420_uart2_hwmod; 109 static struct omap_hwmod omap2420_uart3_hwmod; 110 static struct omap_hwmod omap2420_i2c1_hwmod; 111 static struct omap_hwmod omap2420_i2c2_hwmod; 112 static struct omap_hwmod omap2420_mcbsp1_hwmod; 113 static struct omap_hwmod omap2420_mcbsp2_hwmod; 114 115 /* l4 core -> mcspi1 interface */ 116 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { 117 .master = &omap2420_l4_core_hwmod, 118 .slave = &omap2420_mcspi1_hwmod, 119 .clk = "mcspi1_ick", 120 .addr = omap2_mcspi1_addr_space, 121 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 }; 123 124 /* l4 core -> mcspi2 interface */ 125 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { 126 .master = &omap2420_l4_core_hwmod, 127 .slave = &omap2420_mcspi2_hwmod, 128 .clk = "mcspi2_ick", 129 .addr = omap2_mcspi2_addr_space, 130 .user = OCP_USER_MPU | OCP_USER_SDMA, 131 }; 132 133 /* L4_CORE -> L4_WKUP interface */ 134 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { 135 .master = &omap2420_l4_core_hwmod, 136 .slave = &omap2420_l4_wkup_hwmod, 137 .user = OCP_USER_MPU | OCP_USER_SDMA, 138 }; 139 140 /* L4 CORE -> UART1 interface */ 141 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 142 .master = &omap2420_l4_core_hwmod, 143 .slave = &omap2420_uart1_hwmod, 144 .clk = "uart1_ick", 145 .addr = omap2xxx_uart1_addr_space, 146 .user = OCP_USER_MPU | OCP_USER_SDMA, 147 }; 148 149 /* L4 CORE -> UART2 interface */ 150 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 151 .master = &omap2420_l4_core_hwmod, 152 .slave = &omap2420_uart2_hwmod, 153 .clk = "uart2_ick", 154 .addr = omap2xxx_uart2_addr_space, 155 .user = OCP_USER_MPU | OCP_USER_SDMA, 156 }; 157 158 /* L4 PER -> UART3 interface */ 159 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 160 .master = &omap2420_l4_core_hwmod, 161 .slave = &omap2420_uart3_hwmod, 162 .clk = "uart3_ick", 163 .addr = omap2xxx_uart3_addr_space, 164 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 }; 166 167 /* L4 CORE -> I2C1 interface */ 168 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 169 .master = &omap2420_l4_core_hwmod, 170 .slave = &omap2420_i2c1_hwmod, 171 .clk = "i2c1_ick", 172 .addr = omap2_i2c1_addr_space, 173 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 }; 175 176 /* L4 CORE -> I2C2 interface */ 177 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 178 .master = &omap2420_l4_core_hwmod, 179 .slave = &omap2420_i2c2_hwmod, 180 .clk = "i2c2_ick", 181 .addr = omap2_i2c2_addr_space, 182 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 }; 184 185 /* Slave interfaces on the L4_CORE interconnect */ 186 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { 187 &omap2420_l3_main__l4_core, 188 }; 189 190 /* Master interfaces on the L4_CORE interconnect */ 191 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { 192 &omap2420_l4_core__l4_wkup, 193 &omap2_l4_core__uart1, 194 &omap2_l4_core__uart2, 195 &omap2_l4_core__uart3, 196 &omap2420_l4_core__i2c1, 197 &omap2420_l4_core__i2c2 198 }; 199 200 /* L4 CORE */ 201 static struct omap_hwmod omap2420_l4_core_hwmod = { 202 .name = "l4_core", 203 .class = &l4_hwmod_class, 204 .masters = omap2420_l4_core_masters, 205 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), 206 .slaves = omap2420_l4_core_slaves, 207 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), 208 .flags = HWMOD_NO_IDLEST, 209 }; 210 211 /* Slave interfaces on the L4_WKUP interconnect */ 212 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { 213 &omap2420_l4_core__l4_wkup, 214 }; 215 216 /* Master interfaces on the L4_WKUP interconnect */ 217 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { 218 }; 219 220 /* L4 WKUP */ 221 static struct omap_hwmod omap2420_l4_wkup_hwmod = { 222 .name = "l4_wkup", 223 .class = &l4_hwmod_class, 224 .masters = omap2420_l4_wkup_masters, 225 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), 226 .slaves = omap2420_l4_wkup_slaves, 227 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), 228 .flags = HWMOD_NO_IDLEST, 229 }; 230 231 /* Master interfaces on the MPU device */ 232 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { 233 &omap2420_mpu__l3_main, 234 }; 235 236 /* MPU */ 237 static struct omap_hwmod omap2420_mpu_hwmod = { 238 .name = "mpu", 239 .class = &mpu_hwmod_class, 240 .main_clk = "mpu_ck", 241 .masters = omap2420_mpu_masters, 242 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), 243 }; 244 245 /* 246 * IVA1 interface data 247 */ 248 249 /* IVA <- L3 interface */ 250 static struct omap_hwmod_ocp_if omap2420_l3__iva = { 251 .master = &omap2420_l3_main_hwmod, 252 .slave = &omap2420_iva_hwmod, 253 .clk = "iva1_ifck", 254 .user = OCP_USER_MPU | OCP_USER_SDMA, 255 }; 256 257 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { 258 &omap2420_l3__iva, 259 }; 260 261 /* 262 * IVA2 (IVA2) 263 */ 264 265 static struct omap_hwmod omap2420_iva_hwmod = { 266 .name = "iva", 267 .class = &iva_hwmod_class, 268 .masters = omap2420_iva_masters, 269 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), 270 }; 271 272 /* always-on timers dev attribute */ 273 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 274 .timer_capability = OMAP_TIMER_ALWON, 275 }; 276 277 /* pwm timers dev attribute */ 278 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 279 .timer_capability = OMAP_TIMER_HAS_PWM, 280 }; 281 282 /* timer1 */ 283 static struct omap_hwmod omap2420_timer1_hwmod; 284 285 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { 286 { 287 .pa_start = 0x48028000, 288 .pa_end = 0x48028000 + SZ_1K - 1, 289 .flags = ADDR_TYPE_RT 290 }, 291 { } 292 }; 293 294 /* l4_wkup -> timer1 */ 295 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 296 .master = &omap2420_l4_wkup_hwmod, 297 .slave = &omap2420_timer1_hwmod, 298 .clk = "gpt1_ick", 299 .addr = omap2420_timer1_addrs, 300 .user = OCP_USER_MPU | OCP_USER_SDMA, 301 }; 302 303 /* timer1 slave port */ 304 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { 305 &omap2420_l4_wkup__timer1, 306 }; 307 308 /* timer1 hwmod */ 309 static struct omap_hwmod omap2420_timer1_hwmod = { 310 .name = "timer1", 311 .mpu_irqs = omap2_timer1_mpu_irqs, 312 .main_clk = "gpt1_fck", 313 .prcm = { 314 .omap2 = { 315 .prcm_reg_id = 1, 316 .module_bit = OMAP24XX_EN_GPT1_SHIFT, 317 .module_offs = WKUP_MOD, 318 .idlest_reg_id = 1, 319 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, 320 }, 321 }, 322 .dev_attr = &capability_alwon_dev_attr, 323 .slaves = omap2420_timer1_slaves, 324 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), 325 .class = &omap2xxx_timer_hwmod_class, 326 }; 327 328 /* timer2 */ 329 static struct omap_hwmod omap2420_timer2_hwmod; 330 331 /* l4_core -> timer2 */ 332 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 333 .master = &omap2420_l4_core_hwmod, 334 .slave = &omap2420_timer2_hwmod, 335 .clk = "gpt2_ick", 336 .addr = omap2xxx_timer2_addrs, 337 .user = OCP_USER_MPU | OCP_USER_SDMA, 338 }; 339 340 /* timer2 slave port */ 341 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { 342 &omap2420_l4_core__timer2, 343 }; 344 345 /* timer2 hwmod */ 346 static struct omap_hwmod omap2420_timer2_hwmod = { 347 .name = "timer2", 348 .mpu_irqs = omap2_timer2_mpu_irqs, 349 .main_clk = "gpt2_fck", 350 .prcm = { 351 .omap2 = { 352 .prcm_reg_id = 1, 353 .module_bit = OMAP24XX_EN_GPT2_SHIFT, 354 .module_offs = CORE_MOD, 355 .idlest_reg_id = 1, 356 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 357 }, 358 }, 359 .dev_attr = &capability_alwon_dev_attr, 360 .slaves = omap2420_timer2_slaves, 361 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 362 .class = &omap2xxx_timer_hwmod_class, 363 }; 364 365 /* timer3 */ 366 static struct omap_hwmod omap2420_timer3_hwmod; 367 368 /* l4_core -> timer3 */ 369 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { 370 .master = &omap2420_l4_core_hwmod, 371 .slave = &omap2420_timer3_hwmod, 372 .clk = "gpt3_ick", 373 .addr = omap2xxx_timer3_addrs, 374 .user = OCP_USER_MPU | OCP_USER_SDMA, 375 }; 376 377 /* timer3 slave port */ 378 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { 379 &omap2420_l4_core__timer3, 380 }; 381 382 /* timer3 hwmod */ 383 static struct omap_hwmod omap2420_timer3_hwmod = { 384 .name = "timer3", 385 .mpu_irqs = omap2_timer3_mpu_irqs, 386 .main_clk = "gpt3_fck", 387 .prcm = { 388 .omap2 = { 389 .prcm_reg_id = 1, 390 .module_bit = OMAP24XX_EN_GPT3_SHIFT, 391 .module_offs = CORE_MOD, 392 .idlest_reg_id = 1, 393 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 394 }, 395 }, 396 .dev_attr = &capability_alwon_dev_attr, 397 .slaves = omap2420_timer3_slaves, 398 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 399 .class = &omap2xxx_timer_hwmod_class, 400 }; 401 402 /* timer4 */ 403 static struct omap_hwmod omap2420_timer4_hwmod; 404 405 /* l4_core -> timer4 */ 406 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { 407 .master = &omap2420_l4_core_hwmod, 408 .slave = &omap2420_timer4_hwmod, 409 .clk = "gpt4_ick", 410 .addr = omap2xxx_timer4_addrs, 411 .user = OCP_USER_MPU | OCP_USER_SDMA, 412 }; 413 414 /* timer4 slave port */ 415 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { 416 &omap2420_l4_core__timer4, 417 }; 418 419 /* timer4 hwmod */ 420 static struct omap_hwmod omap2420_timer4_hwmod = { 421 .name = "timer4", 422 .mpu_irqs = omap2_timer4_mpu_irqs, 423 .main_clk = "gpt4_fck", 424 .prcm = { 425 .omap2 = { 426 .prcm_reg_id = 1, 427 .module_bit = OMAP24XX_EN_GPT4_SHIFT, 428 .module_offs = CORE_MOD, 429 .idlest_reg_id = 1, 430 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 431 }, 432 }, 433 .dev_attr = &capability_alwon_dev_attr, 434 .slaves = omap2420_timer4_slaves, 435 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), 436 .class = &omap2xxx_timer_hwmod_class, 437 }; 438 439 /* timer5 */ 440 static struct omap_hwmod omap2420_timer5_hwmod; 441 442 /* l4_core -> timer5 */ 443 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { 444 .master = &omap2420_l4_core_hwmod, 445 .slave = &omap2420_timer5_hwmod, 446 .clk = "gpt5_ick", 447 .addr = omap2xxx_timer5_addrs, 448 .user = OCP_USER_MPU | OCP_USER_SDMA, 449 }; 450 451 /* timer5 slave port */ 452 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { 453 &omap2420_l4_core__timer5, 454 }; 455 456 /* timer5 hwmod */ 457 static struct omap_hwmod omap2420_timer5_hwmod = { 458 .name = "timer5", 459 .mpu_irqs = omap2_timer5_mpu_irqs, 460 .main_clk = "gpt5_fck", 461 .prcm = { 462 .omap2 = { 463 .prcm_reg_id = 1, 464 .module_bit = OMAP24XX_EN_GPT5_SHIFT, 465 .module_offs = CORE_MOD, 466 .idlest_reg_id = 1, 467 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 468 }, 469 }, 470 .dev_attr = &capability_alwon_dev_attr, 471 .slaves = omap2420_timer5_slaves, 472 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 473 .class = &omap2xxx_timer_hwmod_class, 474 }; 475 476 477 /* timer6 */ 478 static struct omap_hwmod omap2420_timer6_hwmod; 479 480 /* l4_core -> timer6 */ 481 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { 482 .master = &omap2420_l4_core_hwmod, 483 .slave = &omap2420_timer6_hwmod, 484 .clk = "gpt6_ick", 485 .addr = omap2xxx_timer6_addrs, 486 .user = OCP_USER_MPU | OCP_USER_SDMA, 487 }; 488 489 /* timer6 slave port */ 490 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { 491 &omap2420_l4_core__timer6, 492 }; 493 494 /* timer6 hwmod */ 495 static struct omap_hwmod omap2420_timer6_hwmod = { 496 .name = "timer6", 497 .mpu_irqs = omap2_timer6_mpu_irqs, 498 .main_clk = "gpt6_fck", 499 .prcm = { 500 .omap2 = { 501 .prcm_reg_id = 1, 502 .module_bit = OMAP24XX_EN_GPT6_SHIFT, 503 .module_offs = CORE_MOD, 504 .idlest_reg_id = 1, 505 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 506 }, 507 }, 508 .dev_attr = &capability_alwon_dev_attr, 509 .slaves = omap2420_timer6_slaves, 510 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), 511 .class = &omap2xxx_timer_hwmod_class, 512 }; 513 514 /* timer7 */ 515 static struct omap_hwmod omap2420_timer7_hwmod; 516 517 /* l4_core -> timer7 */ 518 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 519 .master = &omap2420_l4_core_hwmod, 520 .slave = &omap2420_timer7_hwmod, 521 .clk = "gpt7_ick", 522 .addr = omap2xxx_timer7_addrs, 523 .user = OCP_USER_MPU | OCP_USER_SDMA, 524 }; 525 526 /* timer7 slave port */ 527 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { 528 &omap2420_l4_core__timer7, 529 }; 530 531 /* timer7 hwmod */ 532 static struct omap_hwmod omap2420_timer7_hwmod = { 533 .name = "timer7", 534 .mpu_irqs = omap2_timer7_mpu_irqs, 535 .main_clk = "gpt7_fck", 536 .prcm = { 537 .omap2 = { 538 .prcm_reg_id = 1, 539 .module_bit = OMAP24XX_EN_GPT7_SHIFT, 540 .module_offs = CORE_MOD, 541 .idlest_reg_id = 1, 542 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 543 }, 544 }, 545 .dev_attr = &capability_alwon_dev_attr, 546 .slaves = omap2420_timer7_slaves, 547 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), 548 .class = &omap2xxx_timer_hwmod_class, 549 }; 550 551 /* timer8 */ 552 static struct omap_hwmod omap2420_timer8_hwmod; 553 554 /* l4_core -> timer8 */ 555 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { 556 .master = &omap2420_l4_core_hwmod, 557 .slave = &omap2420_timer8_hwmod, 558 .clk = "gpt8_ick", 559 .addr = omap2xxx_timer8_addrs, 560 .user = OCP_USER_MPU | OCP_USER_SDMA, 561 }; 562 563 /* timer8 slave port */ 564 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { 565 &omap2420_l4_core__timer8, 566 }; 567 568 /* timer8 hwmod */ 569 static struct omap_hwmod omap2420_timer8_hwmod = { 570 .name = "timer8", 571 .mpu_irqs = omap2_timer8_mpu_irqs, 572 .main_clk = "gpt8_fck", 573 .prcm = { 574 .omap2 = { 575 .prcm_reg_id = 1, 576 .module_bit = OMAP24XX_EN_GPT8_SHIFT, 577 .module_offs = CORE_MOD, 578 .idlest_reg_id = 1, 579 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 580 }, 581 }, 582 .dev_attr = &capability_alwon_dev_attr, 583 .slaves = omap2420_timer8_slaves, 584 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), 585 .class = &omap2xxx_timer_hwmod_class, 586 }; 587 588 /* timer9 */ 589 static struct omap_hwmod omap2420_timer9_hwmod; 590 591 /* l4_core -> timer9 */ 592 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { 593 .master = &omap2420_l4_core_hwmod, 594 .slave = &omap2420_timer9_hwmod, 595 .clk = "gpt9_ick", 596 .addr = omap2xxx_timer9_addrs, 597 .user = OCP_USER_MPU | OCP_USER_SDMA, 598 }; 599 600 /* timer9 slave port */ 601 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { 602 &omap2420_l4_core__timer9, 603 }; 604 605 /* timer9 hwmod */ 606 static struct omap_hwmod omap2420_timer9_hwmod = { 607 .name = "timer9", 608 .mpu_irqs = omap2_timer9_mpu_irqs, 609 .main_clk = "gpt9_fck", 610 .prcm = { 611 .omap2 = { 612 .prcm_reg_id = 1, 613 .module_bit = OMAP24XX_EN_GPT9_SHIFT, 614 .module_offs = CORE_MOD, 615 .idlest_reg_id = 1, 616 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 617 }, 618 }, 619 .dev_attr = &capability_pwm_dev_attr, 620 .slaves = omap2420_timer9_slaves, 621 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), 622 .class = &omap2xxx_timer_hwmod_class, 623 }; 624 625 /* timer10 */ 626 static struct omap_hwmod omap2420_timer10_hwmod; 627 628 /* l4_core -> timer10 */ 629 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 630 .master = &omap2420_l4_core_hwmod, 631 .slave = &omap2420_timer10_hwmod, 632 .clk = "gpt10_ick", 633 .addr = omap2_timer10_addrs, 634 .user = OCP_USER_MPU | OCP_USER_SDMA, 635 }; 636 637 /* timer10 slave port */ 638 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { 639 &omap2420_l4_core__timer10, 640 }; 641 642 /* timer10 hwmod */ 643 static struct omap_hwmod omap2420_timer10_hwmod = { 644 .name = "timer10", 645 .mpu_irqs = omap2_timer10_mpu_irqs, 646 .main_clk = "gpt10_fck", 647 .prcm = { 648 .omap2 = { 649 .prcm_reg_id = 1, 650 .module_bit = OMAP24XX_EN_GPT10_SHIFT, 651 .module_offs = CORE_MOD, 652 .idlest_reg_id = 1, 653 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, 654 }, 655 }, 656 .dev_attr = &capability_pwm_dev_attr, 657 .slaves = omap2420_timer10_slaves, 658 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), 659 .class = &omap2xxx_timer_hwmod_class, 660 }; 661 662 /* timer11 */ 663 static struct omap_hwmod omap2420_timer11_hwmod; 664 665 /* l4_core -> timer11 */ 666 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 667 .master = &omap2420_l4_core_hwmod, 668 .slave = &omap2420_timer11_hwmod, 669 .clk = "gpt11_ick", 670 .addr = omap2_timer11_addrs, 671 .user = OCP_USER_MPU | OCP_USER_SDMA, 672 }; 673 674 /* timer11 slave port */ 675 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { 676 &omap2420_l4_core__timer11, 677 }; 678 679 /* timer11 hwmod */ 680 static struct omap_hwmod omap2420_timer11_hwmod = { 681 .name = "timer11", 682 .mpu_irqs = omap2_timer11_mpu_irqs, 683 .main_clk = "gpt11_fck", 684 .prcm = { 685 .omap2 = { 686 .prcm_reg_id = 1, 687 .module_bit = OMAP24XX_EN_GPT11_SHIFT, 688 .module_offs = CORE_MOD, 689 .idlest_reg_id = 1, 690 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, 691 }, 692 }, 693 .dev_attr = &capability_pwm_dev_attr, 694 .slaves = omap2420_timer11_slaves, 695 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), 696 .class = &omap2xxx_timer_hwmod_class, 697 }; 698 699 /* timer12 */ 700 static struct omap_hwmod omap2420_timer12_hwmod; 701 702 /* l4_core -> timer12 */ 703 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 704 .master = &omap2420_l4_core_hwmod, 705 .slave = &omap2420_timer12_hwmod, 706 .clk = "gpt12_ick", 707 .addr = omap2xxx_timer12_addrs, 708 .user = OCP_USER_MPU | OCP_USER_SDMA, 709 }; 710 711 /* timer12 slave port */ 712 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { 713 &omap2420_l4_core__timer12, 714 }; 715 716 /* timer12 hwmod */ 717 static struct omap_hwmod omap2420_timer12_hwmod = { 718 .name = "timer12", 719 .mpu_irqs = omap2xxx_timer12_mpu_irqs, 720 .main_clk = "gpt12_fck", 721 .prcm = { 722 .omap2 = { 723 .prcm_reg_id = 1, 724 .module_bit = OMAP24XX_EN_GPT12_SHIFT, 725 .module_offs = CORE_MOD, 726 .idlest_reg_id = 1, 727 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, 728 }, 729 }, 730 .dev_attr = &capability_pwm_dev_attr, 731 .slaves = omap2420_timer12_slaves, 732 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), 733 .class = &omap2xxx_timer_hwmod_class, 734 }; 735 736 /* l4_wkup -> wd_timer2 */ 737 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { 738 { 739 .pa_start = 0x48022000, 740 .pa_end = 0x4802207f, 741 .flags = ADDR_TYPE_RT 742 }, 743 { } 744 }; 745 746 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 747 .master = &omap2420_l4_wkup_hwmod, 748 .slave = &omap2420_wd_timer2_hwmod, 749 .clk = "mpu_wdt_ick", 750 .addr = omap2420_wd_timer2_addrs, 751 .user = OCP_USER_MPU | OCP_USER_SDMA, 752 }; 753 754 /* wd_timer2 */ 755 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 756 &omap2420_l4_wkup__wd_timer2, 757 }; 758 759 static struct omap_hwmod omap2420_wd_timer2_hwmod = { 760 .name = "wd_timer2", 761 .class = &omap2xxx_wd_timer_hwmod_class, 762 .main_clk = "mpu_wdt_fck", 763 .prcm = { 764 .omap2 = { 765 .prcm_reg_id = 1, 766 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 767 .module_offs = WKUP_MOD, 768 .idlest_reg_id = 1, 769 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, 770 }, 771 }, 772 .slaves = omap2420_wd_timer2_slaves, 773 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), 774 }; 775 776 /* UART1 */ 777 778 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { 779 &omap2_l4_core__uart1, 780 }; 781 782 static struct omap_hwmod omap2420_uart1_hwmod = { 783 .name = "uart1", 784 .mpu_irqs = omap2_uart1_mpu_irqs, 785 .sdma_reqs = omap2_uart1_sdma_reqs, 786 .main_clk = "uart1_fck", 787 .prcm = { 788 .omap2 = { 789 .module_offs = CORE_MOD, 790 .prcm_reg_id = 1, 791 .module_bit = OMAP24XX_EN_UART1_SHIFT, 792 .idlest_reg_id = 1, 793 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, 794 }, 795 }, 796 .slaves = omap2420_uart1_slaves, 797 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), 798 .class = &omap2_uart_class, 799 }; 800 801 /* UART2 */ 802 803 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { 804 &omap2_l4_core__uart2, 805 }; 806 807 static struct omap_hwmod omap2420_uart2_hwmod = { 808 .name = "uart2", 809 .mpu_irqs = omap2_uart2_mpu_irqs, 810 .sdma_reqs = omap2_uart2_sdma_reqs, 811 .main_clk = "uart2_fck", 812 .prcm = { 813 .omap2 = { 814 .module_offs = CORE_MOD, 815 .prcm_reg_id = 1, 816 .module_bit = OMAP24XX_EN_UART2_SHIFT, 817 .idlest_reg_id = 1, 818 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, 819 }, 820 }, 821 .slaves = omap2420_uart2_slaves, 822 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), 823 .class = &omap2_uart_class, 824 }; 825 826 /* UART3 */ 827 828 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { 829 &omap2_l4_core__uart3, 830 }; 831 832 static struct omap_hwmod omap2420_uart3_hwmod = { 833 .name = "uart3", 834 .mpu_irqs = omap2_uart3_mpu_irqs, 835 .sdma_reqs = omap2_uart3_sdma_reqs, 836 .main_clk = "uart3_fck", 837 .prcm = { 838 .omap2 = { 839 .module_offs = CORE_MOD, 840 .prcm_reg_id = 2, 841 .module_bit = OMAP24XX_EN_UART3_SHIFT, 842 .idlest_reg_id = 2, 843 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, 844 }, 845 }, 846 .slaves = omap2420_uart3_slaves, 847 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), 848 .class = &omap2_uart_class, 849 }; 850 851 /* dss */ 852 /* dss master ports */ 853 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { 854 &omap2420_dss__l3, 855 }; 856 857 /* l4_core -> dss */ 858 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { 859 .master = &omap2420_l4_core_hwmod, 860 .slave = &omap2420_dss_core_hwmod, 861 .clk = "dss_ick", 862 .addr = omap2_dss_addrs, 863 .fw = { 864 .omap2 = { 865 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 866 .flags = OMAP_FIREWALL_L4, 867 } 868 }, 869 .user = OCP_USER_MPU | OCP_USER_SDMA, 870 }; 871 872 /* dss slave ports */ 873 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { 874 &omap2420_l4_core__dss, 875 }; 876 877 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 878 /* 879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 880 * driver does not use these clocks. 881 */ 882 { .role = "tv_clk", .clk = "dss_54m_fck" }, 883 { .role = "sys_clk", .clk = "dss2_fck" }, 884 }; 885 886 static struct omap_hwmod omap2420_dss_core_hwmod = { 887 .name = "dss_core", 888 .class = &omap2_dss_hwmod_class, 889 .main_clk = "dss1_fck", /* instead of dss_fck */ 890 .sdma_reqs = omap2xxx_dss_sdma_chs, 891 .prcm = { 892 .omap2 = { 893 .prcm_reg_id = 1, 894 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 895 .module_offs = CORE_MOD, 896 .idlest_reg_id = 1, 897 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 898 }, 899 }, 900 .opt_clks = dss_opt_clks, 901 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 902 .slaves = omap2420_dss_slaves, 903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), 904 .masters = omap2420_dss_masters, 905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), 906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 907 }; 908 909 /* l4_core -> dss_dispc */ 910 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { 911 .master = &omap2420_l4_core_hwmod, 912 .slave = &omap2420_dss_dispc_hwmod, 913 .clk = "dss_ick", 914 .addr = omap2_dss_dispc_addrs, 915 .fw = { 916 .omap2 = { 917 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 918 .flags = OMAP_FIREWALL_L4, 919 } 920 }, 921 .user = OCP_USER_MPU | OCP_USER_SDMA, 922 }; 923 924 /* dss_dispc slave ports */ 925 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { 926 &omap2420_l4_core__dss_dispc, 927 }; 928 929 static struct omap_hwmod omap2420_dss_dispc_hwmod = { 930 .name = "dss_dispc", 931 .class = &omap2_dispc_hwmod_class, 932 .mpu_irqs = omap2_dispc_irqs, 933 .main_clk = "dss1_fck", 934 .prcm = { 935 .omap2 = { 936 .prcm_reg_id = 1, 937 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 938 .module_offs = CORE_MOD, 939 .idlest_reg_id = 1, 940 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 941 }, 942 }, 943 .slaves = omap2420_dss_dispc_slaves, 944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), 945 .flags = HWMOD_NO_IDLEST, 946 .dev_attr = &omap2_3_dss_dispc_dev_attr 947 }; 948 949 /* l4_core -> dss_rfbi */ 950 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { 951 .master = &omap2420_l4_core_hwmod, 952 .slave = &omap2420_dss_rfbi_hwmod, 953 .clk = "dss_ick", 954 .addr = omap2_dss_rfbi_addrs, 955 .fw = { 956 .omap2 = { 957 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 958 .flags = OMAP_FIREWALL_L4, 959 } 960 }, 961 .user = OCP_USER_MPU | OCP_USER_SDMA, 962 }; 963 964 /* dss_rfbi slave ports */ 965 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { 966 &omap2420_l4_core__dss_rfbi, 967 }; 968 969 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 970 { .role = "ick", .clk = "dss_ick" }, 971 }; 972 973 static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 974 .name = "dss_rfbi", 975 .class = &omap2_rfbi_hwmod_class, 976 .main_clk = "dss1_fck", 977 .prcm = { 978 .omap2 = { 979 .prcm_reg_id = 1, 980 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 981 .module_offs = CORE_MOD, 982 }, 983 }, 984 .opt_clks = dss_rfbi_opt_clks, 985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 986 .slaves = omap2420_dss_rfbi_slaves, 987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), 988 .flags = HWMOD_NO_IDLEST, 989 }; 990 991 /* l4_core -> dss_venc */ 992 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 993 .master = &omap2420_l4_core_hwmod, 994 .slave = &omap2420_dss_venc_hwmod, 995 .clk = "dss_ick", 996 .addr = omap2_dss_venc_addrs, 997 .fw = { 998 .omap2 = { 999 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 1000 .flags = OMAP_FIREWALL_L4, 1001 } 1002 }, 1003 .flags = OCPIF_SWSUP_IDLE, 1004 .user = OCP_USER_MPU | OCP_USER_SDMA, 1005 }; 1006 1007 /* dss_venc slave ports */ 1008 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { 1009 &omap2420_l4_core__dss_venc, 1010 }; 1011 1012 static struct omap_hwmod omap2420_dss_venc_hwmod = { 1013 .name = "dss_venc", 1014 .class = &omap2_venc_hwmod_class, 1015 .main_clk = "dss_54m_fck", 1016 .prcm = { 1017 .omap2 = { 1018 .prcm_reg_id = 1, 1019 .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1020 .module_offs = CORE_MOD, 1021 }, 1022 }, 1023 .slaves = omap2420_dss_venc_slaves, 1024 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), 1025 .flags = HWMOD_NO_IDLEST, 1026 }; 1027 1028 /* I2C common */ 1029 static struct omap_hwmod_class_sysconfig i2c_sysc = { 1030 .rev_offs = 0x00, 1031 .sysc_offs = 0x20, 1032 .syss_offs = 0x10, 1033 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1034 .sysc_fields = &omap_hwmod_sysc_type1, 1035 }; 1036 1037 static struct omap_hwmod_class i2c_class = { 1038 .name = "i2c", 1039 .sysc = &i2c_sysc, 1040 .rev = OMAP_I2C_IP_VERSION_1, 1041 .reset = &omap_i2c_reset, 1042 }; 1043 1044 static struct omap_i2c_dev_attr i2c_dev_attr = { 1045 .flags = OMAP_I2C_FLAG_NO_FIFO | 1046 OMAP_I2C_FLAG_SIMPLE_CLOCK | 1047 OMAP_I2C_FLAG_16BIT_DATA_REG | 1048 OMAP_I2C_FLAG_BUS_SHIFT_2, 1049 }; 1050 1051 /* I2C1 */ 1052 1053 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { 1054 &omap2420_l4_core__i2c1, 1055 }; 1056 1057 static struct omap_hwmod omap2420_i2c1_hwmod = { 1058 .name = "i2c1", 1059 .mpu_irqs = omap2_i2c1_mpu_irqs, 1060 .sdma_reqs = omap2_i2c1_sdma_reqs, 1061 .main_clk = "i2c1_fck", 1062 .prcm = { 1063 .omap2 = { 1064 .module_offs = CORE_MOD, 1065 .prcm_reg_id = 1, 1066 .module_bit = OMAP2420_EN_I2C1_SHIFT, 1067 .idlest_reg_id = 1, 1068 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, 1069 }, 1070 }, 1071 .slaves = omap2420_i2c1_slaves, 1072 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), 1073 .class = &i2c_class, 1074 .dev_attr = &i2c_dev_attr, 1075 .flags = HWMOD_16BIT_REG, 1076 }; 1077 1078 /* I2C2 */ 1079 1080 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { 1081 &omap2420_l4_core__i2c2, 1082 }; 1083 1084 static struct omap_hwmod omap2420_i2c2_hwmod = { 1085 .name = "i2c2", 1086 .mpu_irqs = omap2_i2c2_mpu_irqs, 1087 .sdma_reqs = omap2_i2c2_sdma_reqs, 1088 .main_clk = "i2c2_fck", 1089 .prcm = { 1090 .omap2 = { 1091 .module_offs = CORE_MOD, 1092 .prcm_reg_id = 1, 1093 .module_bit = OMAP2420_EN_I2C2_SHIFT, 1094 .idlest_reg_id = 1, 1095 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, 1096 }, 1097 }, 1098 .slaves = omap2420_i2c2_slaves, 1099 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), 1100 .class = &i2c_class, 1101 .dev_attr = &i2c_dev_attr, 1102 .flags = HWMOD_16BIT_REG, 1103 }; 1104 1105 /* l4_wkup -> gpio1 */ 1106 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { 1107 { 1108 .pa_start = 0x48018000, 1109 .pa_end = 0x480181ff, 1110 .flags = ADDR_TYPE_RT 1111 }, 1112 { } 1113 }; 1114 1115 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 1116 .master = &omap2420_l4_wkup_hwmod, 1117 .slave = &omap2420_gpio1_hwmod, 1118 .clk = "gpios_ick", 1119 .addr = omap2420_gpio1_addr_space, 1120 .user = OCP_USER_MPU | OCP_USER_SDMA, 1121 }; 1122 1123 /* l4_wkup -> gpio2 */ 1124 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { 1125 { 1126 .pa_start = 0x4801a000, 1127 .pa_end = 0x4801a1ff, 1128 .flags = ADDR_TYPE_RT 1129 }, 1130 { } 1131 }; 1132 1133 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 1134 .master = &omap2420_l4_wkup_hwmod, 1135 .slave = &omap2420_gpio2_hwmod, 1136 .clk = "gpios_ick", 1137 .addr = omap2420_gpio2_addr_space, 1138 .user = OCP_USER_MPU | OCP_USER_SDMA, 1139 }; 1140 1141 /* l4_wkup -> gpio3 */ 1142 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { 1143 { 1144 .pa_start = 0x4801c000, 1145 .pa_end = 0x4801c1ff, 1146 .flags = ADDR_TYPE_RT 1147 }, 1148 { } 1149 }; 1150 1151 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 1152 .master = &omap2420_l4_wkup_hwmod, 1153 .slave = &omap2420_gpio3_hwmod, 1154 .clk = "gpios_ick", 1155 .addr = omap2420_gpio3_addr_space, 1156 .user = OCP_USER_MPU | OCP_USER_SDMA, 1157 }; 1158 1159 /* l4_wkup -> gpio4 */ 1160 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { 1161 { 1162 .pa_start = 0x4801e000, 1163 .pa_end = 0x4801e1ff, 1164 .flags = ADDR_TYPE_RT 1165 }, 1166 { } 1167 }; 1168 1169 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 1170 .master = &omap2420_l4_wkup_hwmod, 1171 .slave = &omap2420_gpio4_hwmod, 1172 .clk = "gpios_ick", 1173 .addr = omap2420_gpio4_addr_space, 1174 .user = OCP_USER_MPU | OCP_USER_SDMA, 1175 }; 1176 1177 /* gpio dev_attr */ 1178 static struct omap_gpio_dev_attr gpio_dev_attr = { 1179 .bank_width = 32, 1180 .dbck_flag = false, 1181 }; 1182 1183 /* gpio1 */ 1184 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { 1185 &omap2420_l4_wkup__gpio1, 1186 }; 1187 1188 static struct omap_hwmod omap2420_gpio1_hwmod = { 1189 .name = "gpio1", 1190 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1191 .mpu_irqs = omap2_gpio1_irqs, 1192 .main_clk = "gpios_fck", 1193 .prcm = { 1194 .omap2 = { 1195 .prcm_reg_id = 1, 1196 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1197 .module_offs = WKUP_MOD, 1198 .idlest_reg_id = 1, 1199 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1200 }, 1201 }, 1202 .slaves = omap2420_gpio1_slaves, 1203 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), 1204 .class = &omap2xxx_gpio_hwmod_class, 1205 .dev_attr = &gpio_dev_attr, 1206 }; 1207 1208 /* gpio2 */ 1209 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { 1210 &omap2420_l4_wkup__gpio2, 1211 }; 1212 1213 static struct omap_hwmod omap2420_gpio2_hwmod = { 1214 .name = "gpio2", 1215 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1216 .mpu_irqs = omap2_gpio2_irqs, 1217 .main_clk = "gpios_fck", 1218 .prcm = { 1219 .omap2 = { 1220 .prcm_reg_id = 1, 1221 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1222 .module_offs = WKUP_MOD, 1223 .idlest_reg_id = 1, 1224 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1225 }, 1226 }, 1227 .slaves = omap2420_gpio2_slaves, 1228 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), 1229 .class = &omap2xxx_gpio_hwmod_class, 1230 .dev_attr = &gpio_dev_attr, 1231 }; 1232 1233 /* gpio3 */ 1234 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { 1235 &omap2420_l4_wkup__gpio3, 1236 }; 1237 1238 static struct omap_hwmod omap2420_gpio3_hwmod = { 1239 .name = "gpio3", 1240 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1241 .mpu_irqs = omap2_gpio3_irqs, 1242 .main_clk = "gpios_fck", 1243 .prcm = { 1244 .omap2 = { 1245 .prcm_reg_id = 1, 1246 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1247 .module_offs = WKUP_MOD, 1248 .idlest_reg_id = 1, 1249 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1250 }, 1251 }, 1252 .slaves = omap2420_gpio3_slaves, 1253 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), 1254 .class = &omap2xxx_gpio_hwmod_class, 1255 .dev_attr = &gpio_dev_attr, 1256 }; 1257 1258 /* gpio4 */ 1259 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { 1260 &omap2420_l4_wkup__gpio4, 1261 }; 1262 1263 static struct omap_hwmod omap2420_gpio4_hwmod = { 1264 .name = "gpio4", 1265 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1266 .mpu_irqs = omap2_gpio4_irqs, 1267 .main_clk = "gpios_fck", 1268 .prcm = { 1269 .omap2 = { 1270 .prcm_reg_id = 1, 1271 .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1272 .module_offs = WKUP_MOD, 1273 .idlest_reg_id = 1, 1274 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1275 }, 1276 }, 1277 .slaves = omap2420_gpio4_slaves, 1278 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), 1279 .class = &omap2xxx_gpio_hwmod_class, 1280 .dev_attr = &gpio_dev_attr, 1281 }; 1282 1283 /* dma attributes */ 1284 static struct omap_dma_dev_attr dma_dev_attr = { 1285 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1286 IS_CSSA_32 | IS_CDSA_32, 1287 .lch_count = 32, 1288 }; 1289 1290 /* dma_system -> L3 */ 1291 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 1292 .master = &omap2420_dma_system_hwmod, 1293 .slave = &omap2420_l3_main_hwmod, 1294 .clk = "core_l3_ck", 1295 .user = OCP_USER_MPU | OCP_USER_SDMA, 1296 }; 1297 1298 /* dma_system master ports */ 1299 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { 1300 &omap2420_dma_system__l3, 1301 }; 1302 1303 /* l4_core -> dma_system */ 1304 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { 1305 .master = &omap2420_l4_core_hwmod, 1306 .slave = &omap2420_dma_system_hwmod, 1307 .clk = "sdma_ick", 1308 .addr = omap2_dma_system_addrs, 1309 .user = OCP_USER_MPU | OCP_USER_SDMA, 1310 }; 1311 1312 /* dma_system slave ports */ 1313 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { 1314 &omap2420_l4_core__dma_system, 1315 }; 1316 1317 static struct omap_hwmod omap2420_dma_system_hwmod = { 1318 .name = "dma", 1319 .class = &omap2xxx_dma_hwmod_class, 1320 .mpu_irqs = omap2_dma_system_irqs, 1321 .main_clk = "core_l3_ck", 1322 .slaves = omap2420_dma_system_slaves, 1323 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), 1324 .masters = omap2420_dma_system_masters, 1325 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), 1326 .dev_attr = &dma_dev_attr, 1327 .flags = HWMOD_NO_IDLEST, 1328 }; 1329 1330 /* mailbox */ 1331 static struct omap_hwmod omap2420_mailbox_hwmod; 1332 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 1333 { .name = "dsp", .irq = 26 }, 1334 { .name = "iva", .irq = 34 }, 1335 { .irq = -1 } 1336 }; 1337 1338 /* l4_core -> mailbox */ 1339 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 1340 .master = &omap2420_l4_core_hwmod, 1341 .slave = &omap2420_mailbox_hwmod, 1342 .addr = omap2_mailbox_addrs, 1343 .user = OCP_USER_MPU | OCP_USER_SDMA, 1344 }; 1345 1346 /* mailbox slave ports */ 1347 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { 1348 &omap2420_l4_core__mailbox, 1349 }; 1350 1351 static struct omap_hwmod omap2420_mailbox_hwmod = { 1352 .name = "mailbox", 1353 .class = &omap2xxx_mailbox_hwmod_class, 1354 .mpu_irqs = omap2420_mailbox_irqs, 1355 .main_clk = "mailboxes_ick", 1356 .prcm = { 1357 .omap2 = { 1358 .prcm_reg_id = 1, 1359 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 1360 .module_offs = CORE_MOD, 1361 .idlest_reg_id = 1, 1362 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 1363 }, 1364 }, 1365 .slaves = omap2420_mailbox_slaves, 1366 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), 1367 }; 1368 1369 /* mcspi1 */ 1370 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { 1371 &omap2420_l4_core__mcspi1, 1372 }; 1373 1374 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1375 .num_chipselect = 4, 1376 }; 1377 1378 static struct omap_hwmod omap2420_mcspi1_hwmod = { 1379 .name = "mcspi1_hwmod", 1380 .mpu_irqs = omap2_mcspi1_mpu_irqs, 1381 .sdma_reqs = omap2_mcspi1_sdma_reqs, 1382 .main_clk = "mcspi1_fck", 1383 .prcm = { 1384 .omap2 = { 1385 .module_offs = CORE_MOD, 1386 .prcm_reg_id = 1, 1387 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1388 .idlest_reg_id = 1, 1389 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, 1390 }, 1391 }, 1392 .slaves = omap2420_mcspi1_slaves, 1393 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), 1394 .class = &omap2xxx_mcspi_class, 1395 .dev_attr = &omap_mcspi1_dev_attr, 1396 }; 1397 1398 /* mcspi2 */ 1399 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { 1400 &omap2420_l4_core__mcspi2, 1401 }; 1402 1403 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1404 .num_chipselect = 2, 1405 }; 1406 1407 static struct omap_hwmod omap2420_mcspi2_hwmod = { 1408 .name = "mcspi2_hwmod", 1409 .mpu_irqs = omap2_mcspi2_mpu_irqs, 1410 .sdma_reqs = omap2_mcspi2_sdma_reqs, 1411 .main_clk = "mcspi2_fck", 1412 .prcm = { 1413 .omap2 = { 1414 .module_offs = CORE_MOD, 1415 .prcm_reg_id = 1, 1416 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1417 .idlest_reg_id = 1, 1418 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, 1419 }, 1420 }, 1421 .slaves = omap2420_mcspi2_slaves, 1422 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), 1423 .class = &omap2xxx_mcspi_class, 1424 .dev_attr = &omap_mcspi2_dev_attr, 1425 }; 1426 1427 /* 1428 * 'mcbsp' class 1429 * multi channel buffered serial port controller 1430 */ 1431 1432 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { 1433 .name = "mcbsp", 1434 }; 1435 1436 /* mcbsp1 */ 1437 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 1438 { .name = "tx", .irq = 59 }, 1439 { .name = "rx", .irq = 60 }, 1440 { .irq = -1 } 1441 }; 1442 1443 /* l4_core -> mcbsp1 */ 1444 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { 1445 .master = &omap2420_l4_core_hwmod, 1446 .slave = &omap2420_mcbsp1_hwmod, 1447 .clk = "mcbsp1_ick", 1448 .addr = omap2_mcbsp1_addrs, 1449 .user = OCP_USER_MPU | OCP_USER_SDMA, 1450 }; 1451 1452 /* mcbsp1 slave ports */ 1453 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { 1454 &omap2420_l4_core__mcbsp1, 1455 }; 1456 1457 static struct omap_hwmod omap2420_mcbsp1_hwmod = { 1458 .name = "mcbsp1", 1459 .class = &omap2420_mcbsp_hwmod_class, 1460 .mpu_irqs = omap2420_mcbsp1_irqs, 1461 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 1462 .main_clk = "mcbsp1_fck", 1463 .prcm = { 1464 .omap2 = { 1465 .prcm_reg_id = 1, 1466 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1467 .module_offs = CORE_MOD, 1468 .idlest_reg_id = 1, 1469 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 1470 }, 1471 }, 1472 .slaves = omap2420_mcbsp1_slaves, 1473 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), 1474 }; 1475 1476 /* mcbsp2 */ 1477 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { 1478 { .name = "tx", .irq = 62 }, 1479 { .name = "rx", .irq = 63 }, 1480 { .irq = -1 } 1481 }; 1482 1483 /* l4_core -> mcbsp2 */ 1484 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 1485 .master = &omap2420_l4_core_hwmod, 1486 .slave = &omap2420_mcbsp2_hwmod, 1487 .clk = "mcbsp2_ick", 1488 .addr = omap2xxx_mcbsp2_addrs, 1489 .user = OCP_USER_MPU | OCP_USER_SDMA, 1490 }; 1491 1492 /* mcbsp2 slave ports */ 1493 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { 1494 &omap2420_l4_core__mcbsp2, 1495 }; 1496 1497 static struct omap_hwmod omap2420_mcbsp2_hwmod = { 1498 .name = "mcbsp2", 1499 .class = &omap2420_mcbsp_hwmod_class, 1500 .mpu_irqs = omap2420_mcbsp2_irqs, 1501 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 1502 .main_clk = "mcbsp2_fck", 1503 .prcm = { 1504 .omap2 = { 1505 .prcm_reg_id = 1, 1506 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1507 .module_offs = CORE_MOD, 1508 .idlest_reg_id = 1, 1509 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 1510 }, 1511 }, 1512 .slaves = omap2420_mcbsp2_slaves, 1513 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), 1514 }; 1515 1516 static __initdata struct omap_hwmod *omap2420_hwmods[] = { 1517 &omap2420_l3_main_hwmod, 1518 &omap2420_l4_core_hwmod, 1519 &omap2420_l4_wkup_hwmod, 1520 &omap2420_mpu_hwmod, 1521 &omap2420_iva_hwmod, 1522 1523 &omap2420_timer1_hwmod, 1524 &omap2420_timer2_hwmod, 1525 &omap2420_timer3_hwmod, 1526 &omap2420_timer4_hwmod, 1527 &omap2420_timer5_hwmod, 1528 &omap2420_timer6_hwmod, 1529 &omap2420_timer7_hwmod, 1530 &omap2420_timer8_hwmod, 1531 &omap2420_timer9_hwmod, 1532 &omap2420_timer10_hwmod, 1533 &omap2420_timer11_hwmod, 1534 &omap2420_timer12_hwmod, 1535 1536 &omap2420_wd_timer2_hwmod, 1537 &omap2420_uart1_hwmod, 1538 &omap2420_uart2_hwmod, 1539 &omap2420_uart3_hwmod, 1540 /* dss class */ 1541 &omap2420_dss_core_hwmod, 1542 &omap2420_dss_dispc_hwmod, 1543 &omap2420_dss_rfbi_hwmod, 1544 &omap2420_dss_venc_hwmod, 1545 /* i2c class */ 1546 &omap2420_i2c1_hwmod, 1547 &omap2420_i2c2_hwmod, 1548 1549 /* gpio class */ 1550 &omap2420_gpio1_hwmod, 1551 &omap2420_gpio2_hwmod, 1552 &omap2420_gpio3_hwmod, 1553 &omap2420_gpio4_hwmod, 1554 1555 /* dma_system class*/ 1556 &omap2420_dma_system_hwmod, 1557 1558 /* mailbox class */ 1559 &omap2420_mailbox_hwmod, 1560 1561 /* mcbsp class */ 1562 &omap2420_mcbsp1_hwmod, 1563 &omap2420_mcbsp2_hwmod, 1564 1565 /* mcspi class */ 1566 &omap2420_mcspi1_hwmod, 1567 &omap2420_mcspi2_hwmod, 1568 NULL, 1569 }; 1570 1571 int __init omap2420_hwmod_init(void) 1572 { 1573 return omap_hwmod_register(omap2420_hwmods); 1574 } 1575