1 /* 2 * OMAP4 specific common source file. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. 5 * Author: 6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 7 * 8 * 9 * This program is free software,you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/irqchip.h> 19 #include <linux/platform_device.h> 20 #include <linux/memblock.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/export.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of_address.h> 26 #include <linux/reboot.h> 27 #include <linux/genalloc.h> 28 29 #include <asm/hardware/cache-l2x0.h> 30 #include <asm/mach/map.h> 31 #include <asm/memblock.h> 32 #include <asm/smp_twd.h> 33 34 #include "omap-wakeupgen.h" 35 #include "soc.h" 36 #include "iomap.h" 37 #include "common.h" 38 #include "prminst44xx.h" 39 #include "prcm_mpu44xx.h" 40 #include "omap4-sar-layout.h" 41 #include "omap-secure.h" 42 #include "sram.h" 43 44 #ifdef CONFIG_CACHE_L2X0 45 static void __iomem *l2cache_base; 46 #endif 47 48 static void __iomem *sar_ram_base; 49 static void __iomem *gic_dist_base_addr; 50 static void __iomem *twd_base; 51 52 #define IRQ_LOCALTIMER 29 53 54 #ifdef CONFIG_OMAP4_ERRATA_I688 55 /* Used to implement memory barrier on DRAM path */ 56 #define OMAP4_DRAM_BARRIER_VA 0xfe600000 57 58 void __iomem *dram_sync, *sram_sync; 59 60 static phys_addr_t paddr; 61 static u32 size; 62 63 void omap_bus_sync(void) 64 { 65 if (dram_sync && sram_sync) { 66 writel_relaxed(readl_relaxed(dram_sync), dram_sync); 67 writel_relaxed(readl_relaxed(sram_sync), sram_sync); 68 isb(); 69 } 70 } 71 EXPORT_SYMBOL(omap_bus_sync); 72 73 static int __init omap4_sram_init(void) 74 { 75 struct device_node *np; 76 struct gen_pool *sram_pool; 77 78 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); 79 if (!np) 80 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n", 81 __func__); 82 sram_pool = of_get_named_gen_pool(np, "sram", 0); 83 if (!sram_pool) 84 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n", 85 __func__); 86 else 87 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE); 88 89 return 0; 90 } 91 omap_arch_initcall(omap4_sram_init); 92 93 /* Steal one page physical memory for barrier implementation */ 94 int __init omap_barrier_reserve_memblock(void) 95 { 96 97 size = ALIGN(PAGE_SIZE, SZ_1M); 98 paddr = arm_memblock_steal(size, SZ_1M); 99 100 return 0; 101 } 102 103 void __init omap_barriers_init(void) 104 { 105 struct map_desc dram_io_desc[1]; 106 107 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; 108 dram_io_desc[0].pfn = __phys_to_pfn(paddr); 109 dram_io_desc[0].length = size; 110 dram_io_desc[0].type = MT_MEMORY_RW_SO; 111 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); 112 dram_sync = (void __iomem *) dram_io_desc[0].virtual; 113 114 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", 115 (long long) paddr, dram_io_desc[0].virtual); 116 117 } 118 #else 119 void __init omap_barriers_init(void) 120 {} 121 #endif 122 123 void gic_dist_disable(void) 124 { 125 if (gic_dist_base_addr) 126 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); 127 } 128 129 void gic_dist_enable(void) 130 { 131 if (gic_dist_base_addr) 132 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); 133 } 134 135 bool gic_dist_disabled(void) 136 { 137 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); 138 } 139 140 void gic_timer_retrigger(void) 141 { 142 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); 143 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); 144 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); 145 146 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { 147 /* 148 * The local timer interrupt got lost while the distributor was 149 * disabled. Ack the pending interrupt, and retrigger it. 150 */ 151 pr_warn("%s: lost localtimer interrupt\n", __func__); 152 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); 153 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) { 154 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); 155 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE; 156 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); 157 } 158 } 159 } 160 161 #ifdef CONFIG_CACHE_L2X0 162 163 void __iomem *omap4_get_l2cache_base(void) 164 { 165 return l2cache_base; 166 } 167 168 void omap4_l2c310_write_sec(unsigned long val, unsigned reg) 169 { 170 unsigned smc_op; 171 172 switch (reg) { 173 case L2X0_CTRL: 174 smc_op = OMAP4_MON_L2X0_CTRL_INDEX; 175 break; 176 177 case L2X0_AUX_CTRL: 178 smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX; 179 break; 180 181 case L2X0_DEBUG_CTRL: 182 smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX; 183 break; 184 185 case L310_PREFETCH_CTRL: 186 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX; 187 break; 188 189 case L310_POWER_CTRL: 190 pr_info_once("OMAP L2C310: ROM does not support power control setting\n"); 191 return; 192 193 default: 194 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); 195 return; 196 } 197 198 omap_smc1(smc_op, val); 199 } 200 201 int __init omap_l2_cache_init(void) 202 { 203 /* Static mapping, never released */ 204 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); 205 if (WARN_ON(!l2cache_base)) 206 return -ENOMEM; 207 return 0; 208 } 209 #endif 210 211 void __iomem *omap4_get_sar_ram_base(void) 212 { 213 return sar_ram_base; 214 } 215 216 /* 217 * SAR RAM used to save and restore the HW 218 * context in low power modes 219 */ 220 static int __init omap4_sar_ram_init(void) 221 { 222 unsigned long sar_base; 223 224 /* 225 * To avoid code running on other OMAPs in 226 * multi-omap builds 227 */ 228 if (cpu_is_omap44xx()) 229 sar_base = OMAP44XX_SAR_RAM_BASE; 230 else if (soc_is_omap54xx()) 231 sar_base = OMAP54XX_SAR_RAM_BASE; 232 else 233 return -ENOMEM; 234 235 /* Static mapping, never released */ 236 sar_ram_base = ioremap(sar_base, SZ_16K); 237 if (WARN_ON(!sar_ram_base)) 238 return -ENOMEM; 239 240 return 0; 241 } 242 omap_early_initcall(omap4_sar_ram_init); 243 244 static const struct of_device_id intc_match[] = { 245 { .compatible = "ti,omap4-wugen-mpu", }, 246 { .compatible = "ti,omap5-wugen-mpu", }, 247 { }, 248 }; 249 250 static struct device_node *intc_node; 251 252 unsigned int omap4_xlate_irq(unsigned int hwirq) 253 { 254 struct of_phandle_args irq_data; 255 unsigned int irq; 256 257 if (!intc_node) 258 intc_node = of_find_matching_node(NULL, intc_match); 259 260 if (WARN_ON(!intc_node)) 261 return hwirq; 262 263 irq_data.np = intc_node; 264 irq_data.args_count = 3; 265 irq_data.args[0] = 0; 266 irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START; 267 irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH; 268 269 irq = irq_create_of_mapping(&irq_data); 270 if (WARN_ON(!irq)) 271 irq = hwirq; 272 273 return irq; 274 } 275 276 void __init omap_gic_of_init(void) 277 { 278 struct device_node *np; 279 280 intc_node = of_find_matching_node(NULL, intc_match); 281 if (WARN_ON(!intc_node)) { 282 pr_err("No WUGEN found in DT, system will misbehave.\n"); 283 pr_err("UPDATE YOUR DEVICE TREE!\n"); 284 } 285 286 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */ 287 if (!cpu_is_omap446x()) 288 goto skip_errata_init; 289 290 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); 291 gic_dist_base_addr = of_iomap(np, 0); 292 WARN_ON(!gic_dist_base_addr); 293 294 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); 295 twd_base = of_iomap(np, 0); 296 WARN_ON(!twd_base); 297 298 skip_errata_init: 299 irqchip_init(); 300 } 301