1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP Secure API infrastructure. 4 * 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> 8 * Copyright (C) 2013 Pali Rohár <pali@kernel.org> 9 */ 10 11 #include <linux/arm-smccc.h> 12 #include <linux/cpu_pm.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/memblock.h> 17 #include <linux/of.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/memblock.h> 21 22 #include "common.h" 23 #include "omap-secure.h" 24 #include "soc.h" 25 26 static phys_addr_t omap_secure_memblock_base; 27 28 bool optee_available; 29 30 #define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \ 31 ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \ 32 ARM_SMCCC_OWNER_SIP, (func_num)) 33 34 static void __init omap_optee_init_check(void) 35 { 36 struct device_node *np; 37 38 /* 39 * We only check that the OP-TEE node is present and available. The 40 * OP-TEE kernel driver is not needed for the type of interaction made 41 * with OP-TEE here so the driver's status is not checked. 42 */ 43 np = of_find_node_by_path("/firmware/optee"); 44 if (np && of_device_is_available(np)) 45 optee_available = true; 46 of_node_put(np); 47 } 48 49 /** 50 * omap_sec_dispatcher: Routine to dispatch low power secure 51 * service routines 52 * @idx: The HAL API index 53 * @flag: The flag indicating criticality of operation 54 * @nargs: Number of valid arguments out of four. 55 * @arg1, arg2, arg3 args4: Parameters passed to secure API 56 * 57 * Return the non-zero error value on failure. 58 */ 59 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, 60 u32 arg3, u32 arg4) 61 { 62 static u32 buf[NR_CPUS][5]; 63 u32 *param; 64 int cpu; 65 u32 ret; 66 67 cpu = get_cpu(); 68 param = buf[cpu]; 69 70 param[0] = nargs; 71 param[1] = arg1; 72 param[2] = arg2; 73 param[3] = arg3; 74 param[4] = arg4; 75 76 /* 77 * Secure API needs physical address 78 * pointer for the parameters 79 */ 80 flush_cache_all(); 81 outer_clean_range(__pa(param), __pa(param + 5)); 82 ret = omap_smc2(idx, flag, __pa(param)); 83 84 put_cpu(); 85 86 return ret; 87 } 88 89 void omap_smccc_smc(u32 fn, u32 arg) 90 { 91 struct arm_smccc_res res; 92 93 arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg, 94 0, 0, 0, 0, 0, 0, &res); 95 WARN(res.a0, "Secure function call 0x%08x failed\n", fn); 96 } 97 98 void omap_smc1(u32 fn, u32 arg) 99 { 100 /* 101 * If this platform has OP-TEE installed we use ARM SMC calls 102 * otherwise fall back to the OMAP ROM style calls. 103 */ 104 if (optee_available) 105 omap_smccc_smc(fn, arg); 106 else 107 _omap_smc1(fn, arg); 108 } 109 110 /* Allocate the memory to save secure ram */ 111 int __init omap_secure_ram_reserve_memblock(void) 112 { 113 u32 size = OMAP_SECURE_RAM_STORAGE; 114 115 size = ALIGN(size, SECTION_SIZE); 116 omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE); 117 118 return 0; 119 } 120 121 phys_addr_t omap_secure_ram_mempool_base(void) 122 { 123 return omap_secure_memblock_base; 124 } 125 126 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 127 u32 omap3_save_secure_ram(void *addr, int size) 128 { 129 static u32 param[5]; 130 u32 ret; 131 132 if (size != OMAP3_SAVE_SECURE_RAM_SZ) 133 return OMAP3_SAVE_SECURE_RAM_SZ; 134 135 param[0] = 4; /* Number of arguments */ 136 param[1] = __pa(addr); /* Physical address for saving */ 137 param[2] = 0; 138 param[3] = 1; 139 param[4] = 1; 140 141 ret = save_secure_ram_context(__pa(param)); 142 143 return ret; 144 } 145 #endif 146 147 /** 148 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls 149 * @idx: The PPA API index 150 * @process: Process ID 151 * @flag: The flag indicating criticality of operation 152 * @nargs: Number of valid arguments out of four. 153 * @arg1, arg2, arg3 args4: Parameters passed to secure API 154 * 155 * Return the non-zero error value on failure. 156 * 157 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because 158 * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1 159 */ 160 u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, 161 u32 arg1, u32 arg2, u32 arg3, u32 arg4) 162 { 163 static u32 param[5]; 164 u32 ret; 165 166 param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */ 167 param[1] = arg1; 168 param[2] = arg2; 169 param[3] = arg3; 170 param[4] = arg4; 171 172 /* 173 * Secure API needs physical address 174 * pointer for the parameters 175 */ 176 local_irq_disable(); 177 local_fiq_disable(); 178 flush_cache_all(); 179 outer_clean_range(__pa(param), __pa(param + 5)); 180 ret = omap_smc3(idx, process, flag, __pa(param)); 181 flush_cache_all(); 182 local_fiq_enable(); 183 local_irq_enable(); 184 185 return ret; 186 } 187 188 /** 189 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register 190 * @set_bits: bits to set in ACR 191 * @clr_bits: bits to clear in ACR 192 * 193 * Return the non-zero error value on failure. 194 */ 195 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) 196 { 197 u32 acr; 198 199 /* Read ACR */ 200 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 201 acr &= ~clear_bits; 202 acr |= set_bits; 203 204 return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR, 205 0, 206 FLAG_START_CRITICAL, 207 1, acr, 0, 0, 0); 208 } 209 210 /** 211 * rx51_secure_rng_call: Routine for HW random generator 212 */ 213 u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) 214 { 215 return rx51_secure_dispatcher(RX51_PPA_HWRNG, 216 0, 217 NO_FLAG, 218 3, ptr, count, flag, 0); 219 } 220 221 void __init omap_secure_init(void) 222 { 223 omap_optee_init_check(); 224 } 225 226 /* 227 * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return 228 * address after MMU has been re-enabled after CPU1 has been woken up again. 229 * Otherwise the ROM code will attempt to use the earlier physical return 230 * address that got set with MMU off when waking up CPU1. Only used on secure 231 * devices. 232 */ 233 static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v) 234 { 235 switch (cmd) { 236 case CPU_CLUSTER_PM_EXIT: 237 omap_secure_dispatcher(OMAP4_PPA_SERVICE_0, 238 FLAG_START_CRITICAL, 239 0, 0, 0, 0, 0); 240 break; 241 default: 242 break; 243 } 244 245 return NOTIFY_OK; 246 } 247 248 static struct notifier_block secure_notifier_block = { 249 .notifier_call = cpu_notifier, 250 }; 251 252 static int __init secure_pm_init(void) 253 { 254 if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx()) 255 return 0; 256 257 cpu_pm_register_notifier(&secure_notifier_block); 258 259 return 0; 260 } 261 omap_arch_initcall(secure_pm_init); 262