xref: /linux/arch/arm/mach-omap2/mcbsp.c (revision 26b0d14106954ae46d2f4f7eec3481828a210f7d)
1 /*
2  * linux/arch/arm/mach-omap2/mcbsp.c
3  *
4  * Copyright (C) 2008 Instituto Nokia de Tecnologia
5  * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * Multichannel mode not supported.
12  */
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 
21 #include <mach/irqs.h>
22 #include <plat/dma.h>
23 #include <plat/cpu.h>
24 #include <plat/mcbsp.h>
25 #include <plat/omap_device.h>
26 #include <linux/pm_runtime.h>
27 
28 #include "control.h"
29 
30 /*
31  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
32  * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
33  */
34 #include "cm2xxx_3xxx.h"
35 #include "cm-regbits-34xx.h"
36 
37 /* McBSP1 internal signal muxing function for OMAP2/3 */
38 static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
39 				   const char *src)
40 {
41 	u32 v;
42 
43 	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
44 
45 	if (!strcmp(signal, "clkr")) {
46 		if (!strcmp(src, "clkr"))
47 			v &= ~OMAP2_MCBSP1_CLKR_MASK;
48 		else if (!strcmp(src, "clkx"))
49 			v |= OMAP2_MCBSP1_CLKR_MASK;
50 		else
51 			return -EINVAL;
52 	} else if (!strcmp(signal, "fsr")) {
53 		if (!strcmp(src, "fsr"))
54 			v &= ~OMAP2_MCBSP1_FSR_MASK;
55 		else if (!strcmp(src, "fsx"))
56 			v |= OMAP2_MCBSP1_FSR_MASK;
57 		else
58 			return -EINVAL;
59 	} else {
60 		return -EINVAL;
61 	}
62 
63 	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
64 
65 	return 0;
66 }
67 
68 /* McBSP4 internal signal muxing function for OMAP4 */
69 #define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
70 #define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
71 static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
72 				   const char *src)
73 {
74 	u32 v;
75 
76 	/*
77 	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
78 	 * mux) is used */
79 	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
80 
81 	if (!strcmp(signal, "clkr")) {
82 		if (!strcmp(src, "clkr"))
83 			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
84 		else if (!strcmp(src, "clkx"))
85 			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
86 		else
87 			return -EINVAL;
88 	} else if (!strcmp(signal, "fsr")) {
89 		if (!strcmp(src, "fsr"))
90 			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
91 		else if (!strcmp(src, "fsx"))
92 			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
93 		else
94 			return -EINVAL;
95 	} else {
96 		return -EINVAL;
97 	}
98 
99 	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
100 
101 	return 0;
102 }
103 
104 /* McBSP CLKS source switching function */
105 static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
106 				   const char *src)
107 {
108 	struct clk *fck_src;
109 	char *fck_src_name;
110 	int r;
111 
112 	if (!strcmp(src, "clks_ext"))
113 		fck_src_name = "pad_fck";
114 	else if (!strcmp(src, "clks_fclk"))
115 		fck_src_name = "prcm_fck";
116 	else
117 		return -EINVAL;
118 
119 	fck_src = clk_get(dev, fck_src_name);
120 	if (IS_ERR_OR_NULL(fck_src)) {
121 		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
122 		       fck_src_name);
123 		return -EINVAL;
124 	}
125 
126 	pm_runtime_put_sync(dev);
127 
128 	r = clk_set_parent(clk, fck_src);
129 	if (IS_ERR_VALUE(r)) {
130 		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
131 		       "clks", fck_src_name);
132 		clk_put(fck_src);
133 		return -EINVAL;
134 	}
135 
136 	pm_runtime_get_sync(dev);
137 
138 	clk_put(fck_src);
139 
140 	return 0;
141 }
142 
143 static int omap3_enable_st_clock(unsigned int id, bool enable)
144 {
145 	unsigned int w;
146 
147 	/*
148 	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
149 	 * are enabled or sidetones start sounding ugly.
150 	 */
151 	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
152 	if (enable)
153 		w &= ~(1 << (id - 2));
154 	else
155 		w |= 1 << (id - 2);
156 	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
157 
158 	return 0;
159 }
160 
161 static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
162 {
163 	int id, count = 1;
164 	char *name = "omap-mcbsp";
165 	struct omap_hwmod *oh_device[2];
166 	struct omap_mcbsp_platform_data *pdata = NULL;
167 	struct platform_device *pdev;
168 
169 	sscanf(oh->name, "mcbsp%d", &id);
170 
171 	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
172 	if (!pdata) {
173 		pr_err("%s: No memory for mcbsp\n", __func__);
174 		return -ENOMEM;
175 	}
176 
177 	pdata->reg_step = 4;
178 	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
179 		pdata->reg_size = 2;
180 	} else {
181 		pdata->reg_size = 4;
182 		pdata->has_ccr = true;
183 	}
184 	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
185 
186 	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
187 	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
188 		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
189 
190 	/* On OMAP4 the McBSP4 port has 6 pin configuration */
191 	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
192 		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
193 
194 	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
195 		if (id == 2)
196 			/* The FIFO has 1024 + 256 locations */
197 			pdata->buffer_size = 0x500;
198 		else
199 			/* The FIFO has 128 locations */
200 			pdata->buffer_size = 0x80;
201 	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
202 		/* The FIFO has 128 locations for all instances */
203 		pdata->buffer_size = 0x80;
204 	}
205 
206 	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
207 		pdata->has_wakeup = true;
208 
209 	oh_device[0] = oh;
210 
211 	if (oh->dev_attr) {
212 		oh_device[1] = omap_hwmod_lookup((
213 		(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
214 		pdata->enable_st_clock = omap3_enable_st_clock;
215 		count++;
216 	}
217 	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
218 				sizeof(*pdata), NULL, 0, false);
219 	kfree(pdata);
220 	if (IS_ERR(pdev))  {
221 		pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
222 					name, oh->name);
223 		return PTR_ERR(pdev);
224 	}
225 	return 0;
226 }
227 
228 static int __init omap2_mcbsp_init(void)
229 {
230 	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
231 
232 	return 0;
233 }
234 arch_initcall(omap2_mcbsp_init);
235