xref: /linux/arch/arm/mach-omap2/io.c (revision cf2f33a4e54096f90652cca3511fd6a456ea5abe) 
1 /*
2  * linux/arch/arm/mach-omap2/io.c
3  *
4  * OMAP2 I/O mapping code
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Copyright (C) 2007-2009 Texas Instruments
8  *
9  * Author:
10  *	Juha Yrjola <juha.yrjola@nokia.com>
11  *	Syed Khasim <x0khasim@ti.com>
12  *
13  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
27 
28 #include <linux/omap-dma.h>
29 
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "omap-pm.h"
41 #include "sdrc.h"
42 #include "control.h"
43 #include "serial.h"
44 #include "sram.h"
45 #include "cm2xxx.h"
46 #include "cm3xxx.h"
47 #include "cm33xx.h"
48 #include "cm44xx.h"
49 #include "prm.h"
50 #include "cm.h"
51 #include "prcm_mpu44xx.h"
52 #include "prminst44xx.h"
53 #include "prm2xxx.h"
54 #include "prm3xxx.h"
55 #include "prm33xx.h"
56 #include "prm44xx.h"
57 #include "opp2xxx.h"
58 
59 /*
60  * omap_clk_soc_init: points to a function that does the SoC-specific
61  * clock initializations
62  */
63 static int (*omap_clk_soc_init)(void);
64 
65 /*
66  * The machine specific code may provide the extra mapping besides the
67  * default mapping provided here.
68  */
69 
70 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
71 static struct map_desc omap24xx_io_desc[] __initdata = {
72 	{
73 		.virtual	= L3_24XX_VIRT,
74 		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
75 		.length		= L3_24XX_SIZE,
76 		.type		= MT_DEVICE
77 	},
78 	{
79 		.virtual	= L4_24XX_VIRT,
80 		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
81 		.length		= L4_24XX_SIZE,
82 		.type		= MT_DEVICE
83 	},
84 };
85 
86 #ifdef CONFIG_SOC_OMAP2420
87 static struct map_desc omap242x_io_desc[] __initdata = {
88 	{
89 		.virtual	= DSP_MEM_2420_VIRT,
90 		.pfn		= __phys_to_pfn(DSP_MEM_2420_PHYS),
91 		.length		= DSP_MEM_2420_SIZE,
92 		.type		= MT_DEVICE
93 	},
94 	{
95 		.virtual	= DSP_IPI_2420_VIRT,
96 		.pfn		= __phys_to_pfn(DSP_IPI_2420_PHYS),
97 		.length		= DSP_IPI_2420_SIZE,
98 		.type		= MT_DEVICE
99 	},
100 	{
101 		.virtual	= DSP_MMU_2420_VIRT,
102 		.pfn		= __phys_to_pfn(DSP_MMU_2420_PHYS),
103 		.length		= DSP_MMU_2420_SIZE,
104 		.type		= MT_DEVICE
105 	},
106 };
107 
108 #endif
109 
110 #ifdef CONFIG_SOC_OMAP2430
111 static struct map_desc omap243x_io_desc[] __initdata = {
112 	{
113 		.virtual	= L4_WK_243X_VIRT,
114 		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
115 		.length		= L4_WK_243X_SIZE,
116 		.type		= MT_DEVICE
117 	},
118 	{
119 		.virtual	= OMAP243X_GPMC_VIRT,
120 		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 		.length		= OMAP243X_GPMC_SIZE,
122 		.type		= MT_DEVICE
123 	},
124 	{
125 		.virtual	= OMAP243X_SDRC_VIRT,
126 		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 		.length		= OMAP243X_SDRC_SIZE,
128 		.type		= MT_DEVICE
129 	},
130 	{
131 		.virtual	= OMAP243X_SMS_VIRT,
132 		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
133 		.length		= OMAP243X_SMS_SIZE,
134 		.type		= MT_DEVICE
135 	},
136 };
137 #endif
138 #endif
139 
140 #ifdef	CONFIG_ARCH_OMAP3
141 static struct map_desc omap34xx_io_desc[] __initdata = {
142 	{
143 		.virtual	= L3_34XX_VIRT,
144 		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
145 		.length		= L3_34XX_SIZE,
146 		.type		= MT_DEVICE
147 	},
148 	{
149 		.virtual	= L4_34XX_VIRT,
150 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
151 		.length		= L4_34XX_SIZE,
152 		.type		= MT_DEVICE
153 	},
154 	{
155 		.virtual	= OMAP34XX_GPMC_VIRT,
156 		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 		.length		= OMAP34XX_GPMC_SIZE,
158 		.type		= MT_DEVICE
159 	},
160 	{
161 		.virtual	= OMAP343X_SMS_VIRT,
162 		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
163 		.length		= OMAP343X_SMS_SIZE,
164 		.type		= MT_DEVICE
165 	},
166 	{
167 		.virtual	= OMAP343X_SDRC_VIRT,
168 		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 		.length		= OMAP343X_SDRC_SIZE,
170 		.type		= MT_DEVICE
171 	},
172 	{
173 		.virtual	= L4_PER_34XX_VIRT,
174 		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
175 		.length		= L4_PER_34XX_SIZE,
176 		.type		= MT_DEVICE
177 	},
178 	{
179 		.virtual	= L4_EMU_34XX_VIRT,
180 		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
181 		.length		= L4_EMU_34XX_SIZE,
182 		.type		= MT_DEVICE
183 	},
184 };
185 #endif
186 
187 #ifdef CONFIG_SOC_TI81XX
188 static struct map_desc omapti81xx_io_desc[] __initdata = {
189 	{
190 		.virtual	= L4_34XX_VIRT,
191 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
192 		.length		= L4_34XX_SIZE,
193 		.type		= MT_DEVICE
194 	}
195 };
196 #endif
197 
198 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
199 static struct map_desc omapam33xx_io_desc[] __initdata = {
200 	{
201 		.virtual	= L4_34XX_VIRT,
202 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
203 		.length		= L4_34XX_SIZE,
204 		.type		= MT_DEVICE
205 	},
206 	{
207 		.virtual	= L4_WK_AM33XX_VIRT,
208 		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 		.length		= L4_WK_AM33XX_SIZE,
210 		.type		= MT_DEVICE
211 	}
212 };
213 #endif
214 
215 #ifdef	CONFIG_ARCH_OMAP4
216 static struct map_desc omap44xx_io_desc[] __initdata = {
217 	{
218 		.virtual	= L3_44XX_VIRT,
219 		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
220 		.length		= L3_44XX_SIZE,
221 		.type		= MT_DEVICE,
222 	},
223 	{
224 		.virtual	= L4_44XX_VIRT,
225 		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
226 		.length		= L4_44XX_SIZE,
227 		.type		= MT_DEVICE,
228 	},
229 	{
230 		.virtual	= L4_PER_44XX_VIRT,
231 		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
232 		.length		= L4_PER_44XX_SIZE,
233 		.type		= MT_DEVICE,
234 	},
235 };
236 #endif
237 
238 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
239 static struct map_desc omap54xx_io_desc[] __initdata = {
240 	{
241 		.virtual	= L3_54XX_VIRT,
242 		.pfn		= __phys_to_pfn(L3_54XX_PHYS),
243 		.length		= L3_54XX_SIZE,
244 		.type		= MT_DEVICE,
245 	},
246 	{
247 		.virtual	= L4_54XX_VIRT,
248 		.pfn		= __phys_to_pfn(L4_54XX_PHYS),
249 		.length		= L4_54XX_SIZE,
250 		.type		= MT_DEVICE,
251 	},
252 	{
253 		.virtual	= L4_WK_54XX_VIRT,
254 		.pfn		= __phys_to_pfn(L4_WK_54XX_PHYS),
255 		.length		= L4_WK_54XX_SIZE,
256 		.type		= MT_DEVICE,
257 	},
258 	{
259 		.virtual	= L4_PER_54XX_VIRT,
260 		.pfn		= __phys_to_pfn(L4_PER_54XX_PHYS),
261 		.length		= L4_PER_54XX_SIZE,
262 		.type		= MT_DEVICE,
263 	},
264 };
265 #endif
266 
267 #ifdef CONFIG_SOC_OMAP2420
268 void __init omap242x_map_io(void)
269 {
270 	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
271 	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
272 }
273 #endif
274 
275 #ifdef CONFIG_SOC_OMAP2430
276 void __init omap243x_map_io(void)
277 {
278 	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
279 	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
280 }
281 #endif
282 
283 #ifdef CONFIG_ARCH_OMAP3
284 void __init omap3_map_io(void)
285 {
286 	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
287 }
288 #endif
289 
290 #ifdef CONFIG_SOC_TI81XX
291 void __init ti81xx_map_io(void)
292 {
293 	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
294 }
295 #endif
296 
297 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
298 void __init am33xx_map_io(void)
299 {
300 	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
301 }
302 #endif
303 
304 #ifdef CONFIG_ARCH_OMAP4
305 void __init omap4_map_io(void)
306 {
307 	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
308 }
309 #endif
310 
311 #if defined(CONFIG_SOC_OMAP5) ||  defined(CONFIG_SOC_DRA7XX)
312 void __init omap5_map_io(void)
313 {
314 	iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
315 }
316 #endif
317 /*
318  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
319  *
320  * Sets the CORE DPLL3 M2 divider to the same value that it's at
321  * currently.  This has the effect of setting the SDRC SDRAM AC timing
322  * registers to the values currently defined by the kernel.  Currently
323  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
324  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
325  * or passes along the return value of clk_set_rate().
326  */
327 static int __init _omap2_init_reprogram_sdrc(void)
328 {
329 	struct clk *dpll3_m2_ck;
330 	int v = -EINVAL;
331 	long rate;
332 
333 	if (!cpu_is_omap34xx())
334 		return 0;
335 
336 	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
337 	if (IS_ERR(dpll3_m2_ck))
338 		return -EINVAL;
339 
340 	rate = clk_get_rate(dpll3_m2_ck);
341 	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
342 	v = clk_set_rate(dpll3_m2_ck, rate);
343 	if (v)
344 		pr_err("dpll3_m2_clk rate change failed: %d\n", v);
345 
346 	clk_put(dpll3_m2_ck);
347 
348 	return v;
349 }
350 
351 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
352 {
353 	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
354 }
355 
356 static void __init omap_hwmod_init_postsetup(void)
357 {
358 	u8 postsetup_state;
359 
360 	/* Set the default postsetup state for all hwmods */
361 #ifdef CONFIG_PM
362 	postsetup_state = _HWMOD_STATE_IDLE;
363 #else
364 	postsetup_state = _HWMOD_STATE_ENABLED;
365 #endif
366 	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
367 
368 	omap_pm_if_early_init();
369 }
370 
371 static void __init __maybe_unused omap_common_late_init(void)
372 {
373 	omap_mux_late_init();
374 	omap2_common_pm_late_init();
375 	omap_soc_device_init();
376 }
377 
378 #ifdef CONFIG_SOC_OMAP2420
379 void __init omap2420_init_early(void)
380 {
381 	omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
382 	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
383 			       OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
384 	omap2_control_base_init();
385 	omap2xxx_check_revision();
386 	omap2_prcm_base_init();
387 	omap2xxx_voltagedomains_init();
388 	omap242x_powerdomains_init();
389 	omap242x_clockdomains_init();
390 	omap2420_hwmod_init();
391 	omap_hwmod_init_postsetup();
392 	omap_clk_soc_init = omap2420_dt_clk_init;
393 	rate_table = omap2420_rate_table;
394 }
395 
396 void __init omap2420_init_late(void)
397 {
398 	omap_common_late_init();
399 	omap2_pm_init();
400 	omap2_clk_enable_autoidle_all();
401 }
402 #endif
403 
404 #ifdef CONFIG_SOC_OMAP2430
405 void __init omap2430_init_early(void)
406 {
407 	omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
408 	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
409 			       OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
410 	omap2_control_base_init();
411 	omap2xxx_check_revision();
412 	omap2_prcm_base_init();
413 	omap2xxx_voltagedomains_init();
414 	omap243x_powerdomains_init();
415 	omap243x_clockdomains_init();
416 	omap2430_hwmod_init();
417 	omap_hwmod_init_postsetup();
418 	omap_clk_soc_init = omap2430_dt_clk_init;
419 	rate_table = omap2430_rate_table;
420 }
421 
422 void __init omap2430_init_late(void)
423 {
424 	omap_common_late_init();
425 	omap2_pm_init();
426 	omap2_clk_enable_autoidle_all();
427 }
428 #endif
429 
430 /*
431  * Currently only board-omap3beagle.c should call this because of the
432  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
433  */
434 #ifdef CONFIG_ARCH_OMAP3
435 void __init omap3_init_early(void)
436 {
437 	omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
438 	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
439 			       OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
440 	/* XXX: remove these once OMAP3 is DT only */
441 	if (!of_have_populated_dt()) {
442 		omap2_set_globals_control(
443 			OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
444 		omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
445 		omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
446 				     NULL);
447 	}
448 	omap2_control_base_init();
449 	omap3xxx_check_revision();
450 	omap3xxx_check_features();
451 	omap2_prcm_base_init();
452 	/* XXX: remove these once OMAP3 is DT only */
453 	if (!of_have_populated_dt()) {
454 		omap3xxx_prm_init(NULL);
455 		omap3xxx_cm_init(NULL);
456 	}
457 	omap3xxx_voltagedomains_init();
458 	omap3xxx_powerdomains_init();
459 	omap3xxx_clockdomains_init();
460 	omap3xxx_hwmod_init();
461 	omap_hwmod_init_postsetup();
462 	if (!of_have_populated_dt()) {
463 		omap3_control_legacy_iomap_init();
464 		if (soc_is_am35xx())
465 			omap_clk_soc_init = am35xx_clk_legacy_init;
466 		else if (cpu_is_omap3630())
467 			omap_clk_soc_init = omap36xx_clk_legacy_init;
468 		else if (omap_rev() == OMAP3430_REV_ES1_0)
469 			omap_clk_soc_init = omap3430es1_clk_legacy_init;
470 		else
471 			omap_clk_soc_init = omap3430_clk_legacy_init;
472 	}
473 }
474 
475 void __init omap3430_init_early(void)
476 {
477 	omap3_init_early();
478 	if (of_have_populated_dt())
479 		omap_clk_soc_init = omap3430_dt_clk_init;
480 }
481 
482 void __init omap35xx_init_early(void)
483 {
484 	omap3_init_early();
485 	if (of_have_populated_dt())
486 		omap_clk_soc_init = omap3430_dt_clk_init;
487 }
488 
489 void __init omap3630_init_early(void)
490 {
491 	omap3_init_early();
492 	if (of_have_populated_dt())
493 		omap_clk_soc_init = omap3630_dt_clk_init;
494 }
495 
496 void __init am35xx_init_early(void)
497 {
498 	omap3_init_early();
499 	if (of_have_populated_dt())
500 		omap_clk_soc_init = am35xx_dt_clk_init;
501 }
502 
503 void __init omap3_init_late(void)
504 {
505 	omap_common_late_init();
506 	omap3_pm_init();
507 	omap2_clk_enable_autoidle_all();
508 }
509 
510 void __init omap3430_init_late(void)
511 {
512 	omap_common_late_init();
513 	omap3_pm_init();
514 	omap2_clk_enable_autoidle_all();
515 }
516 
517 void __init omap35xx_init_late(void)
518 {
519 	omap_common_late_init();
520 	omap3_pm_init();
521 	omap2_clk_enable_autoidle_all();
522 }
523 
524 void __init omap3630_init_late(void)
525 {
526 	omap_common_late_init();
527 	omap3_pm_init();
528 	omap2_clk_enable_autoidle_all();
529 }
530 
531 void __init am35xx_init_late(void)
532 {
533 	omap_common_late_init();
534 	omap3_pm_init();
535 	omap2_clk_enable_autoidle_all();
536 }
537 
538 void __init ti81xx_init_late(void)
539 {
540 	omap_common_late_init();
541 	omap2_clk_enable_autoidle_all();
542 }
543 #endif
544 
545 #ifdef CONFIG_SOC_TI81XX
546 void __init ti814x_init_early(void)
547 {
548 	omap2_set_globals_tap(TI814X_CLASS,
549 			      OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
550 	omap2_control_base_init();
551 	omap3xxx_check_revision();
552 	ti81xx_check_features();
553 	omap2_prcm_base_init();
554 	omap3xxx_voltagedomains_init();
555 	omap3xxx_powerdomains_init();
556 	ti81xx_clockdomains_init();
557 	ti81xx_hwmod_init();
558 	omap_hwmod_init_postsetup();
559 	if (of_have_populated_dt())
560 		omap_clk_soc_init = ti81xx_dt_clk_init;
561 }
562 
563 void __init ti816x_init_early(void)
564 {
565 	omap2_set_globals_tap(TI816X_CLASS,
566 			      OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
567 	omap2_control_base_init();
568 	omap3xxx_check_revision();
569 	ti81xx_check_features();
570 	omap2_prcm_base_init();
571 	omap3xxx_voltagedomains_init();
572 	omap3xxx_powerdomains_init();
573 	ti81xx_clockdomains_init();
574 	ti81xx_hwmod_init();
575 	omap_hwmod_init_postsetup();
576 	if (of_have_populated_dt())
577 		omap_clk_soc_init = ti81xx_dt_clk_init;
578 }
579 #endif
580 
581 #ifdef CONFIG_SOC_AM33XX
582 void __init am33xx_init_early(void)
583 {
584 	omap2_set_globals_tap(AM335X_CLASS,
585 			      AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
586 	omap2_control_base_init();
587 	omap3xxx_check_revision();
588 	am33xx_check_features();
589 	omap2_prcm_base_init();
590 	am33xx_powerdomains_init();
591 	am33xx_clockdomains_init();
592 	am33xx_hwmod_init();
593 	omap_hwmod_init_postsetup();
594 	omap_clk_soc_init = am33xx_dt_clk_init;
595 }
596 
597 void __init am33xx_init_late(void)
598 {
599 	omap_common_late_init();
600 }
601 #endif
602 
603 #ifdef CONFIG_SOC_AM43XX
604 void __init am43xx_init_early(void)
605 {
606 	omap2_set_globals_tap(AM335X_CLASS,
607 			      AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
608 	omap2_control_base_init();
609 	omap3xxx_check_revision();
610 	am33xx_check_features();
611 	omap2_prcm_base_init();
612 	am43xx_powerdomains_init();
613 	am43xx_clockdomains_init();
614 	am43xx_hwmod_init();
615 	omap_hwmod_init_postsetup();
616 	omap_l2_cache_init();
617 	omap_clk_soc_init = am43xx_dt_clk_init;
618 }
619 
620 void __init am43xx_init_late(void)
621 {
622 	omap_common_late_init();
623 }
624 #endif
625 
626 #ifdef CONFIG_ARCH_OMAP4
627 void __init omap4430_init_early(void)
628 {
629 	omap2_set_globals_tap(OMAP443X_CLASS,
630 			      OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
631 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
632 	omap2_control_base_init();
633 	omap4xxx_check_revision();
634 	omap4xxx_check_features();
635 	omap2_prcm_base_init();
636 	omap4_pm_init_early();
637 	omap44xx_voltagedomains_init();
638 	omap44xx_powerdomains_init();
639 	omap44xx_clockdomains_init();
640 	omap44xx_hwmod_init();
641 	omap_hwmod_init_postsetup();
642 	omap_l2_cache_init();
643 	omap_clk_soc_init = omap4xxx_dt_clk_init;
644 }
645 
646 void __init omap4430_init_late(void)
647 {
648 	omap_common_late_init();
649 	omap4_pm_init();
650 	omap2_clk_enable_autoidle_all();
651 }
652 #endif
653 
654 #ifdef CONFIG_SOC_OMAP5
655 void __init omap5_init_early(void)
656 {
657 	omap2_set_globals_tap(OMAP54XX_CLASS,
658 			      OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
659 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
660 	omap2_control_base_init();
661 	omap4_pm_init_early();
662 	omap2_prcm_base_init();
663 	omap5xxx_check_revision();
664 	omap54xx_voltagedomains_init();
665 	omap54xx_powerdomains_init();
666 	omap54xx_clockdomains_init();
667 	omap54xx_hwmod_init();
668 	omap_hwmod_init_postsetup();
669 	omap_clk_soc_init = omap5xxx_dt_clk_init;
670 }
671 
672 void __init omap5_init_late(void)
673 {
674 	omap_common_late_init();
675 	omap4_pm_init();
676 	omap2_clk_enable_autoidle_all();
677 }
678 #endif
679 
680 #ifdef CONFIG_SOC_DRA7XX
681 void __init dra7xx_init_early(void)
682 {
683 	omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
684 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
685 	omap2_control_base_init();
686 	omap4_pm_init_early();
687 	omap2_prcm_base_init();
688 	dra7xxx_check_revision();
689 	dra7xx_powerdomains_init();
690 	dra7xx_clockdomains_init();
691 	dra7xx_hwmod_init();
692 	omap_hwmod_init_postsetup();
693 	omap_clk_soc_init = dra7xx_dt_clk_init;
694 }
695 
696 void __init dra7xx_init_late(void)
697 {
698 	omap_common_late_init();
699 	omap4_pm_init();
700 	omap2_clk_enable_autoidle_all();
701 }
702 #endif
703 
704 
705 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
706 				      struct omap_sdrc_params *sdrc_cs1)
707 {
708 	omap_sram_init();
709 
710 	if (cpu_is_omap24xx() || omap3_has_sdrc()) {
711 		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
712 		_omap2_init_reprogram_sdrc();
713 	}
714 }
715 
716 int __init omap_clk_init(void)
717 {
718 	int ret = 0;
719 
720 	if (!omap_clk_soc_init)
721 		return 0;
722 
723 	ti_clk_init_features();
724 
725 	omap2_clk_setup_ll_ops();
726 
727 	if (of_have_populated_dt()) {
728 		ret = omap_control_init();
729 		if (ret)
730 			return ret;
731 
732 		ret = omap_prcm_init();
733 		if (ret)
734 			return ret;
735 
736 		of_clk_init(NULL);
737 
738 		ti_dt_clk_init_retry_clks();
739 
740 		ti_dt_clockdomains_setup();
741 	}
742 
743 	ret = omap_clk_soc_init();
744 
745 	return ret;
746 }
747