1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 25 #include <asm/tlb.h> 26 #include <asm/mach/map.h> 27 28 #include <linux/omap-dma.h> 29 30 #include "omap_hwmod.h" 31 #include "soc.h" 32 #include "iomap.h" 33 #include "voltage.h" 34 #include "powerdomain.h" 35 #include "clockdomain.h" 36 #include "common.h" 37 #include "clock.h" 38 #include "clock2xxx.h" 39 #include "clock3xxx.h" 40 #include "clock44xx.h" 41 #include "omap-pm.h" 42 #include "sdrc.h" 43 #include "control.h" 44 #include "serial.h" 45 #include "sram.h" 46 #include "cm2xxx.h" 47 #include "cm3xxx.h" 48 #include "prm.h" 49 #include "cm.h" 50 #include "prcm_mpu44xx.h" 51 #include "prminst44xx.h" 52 #include "cminst44xx.h" 53 #include "prm2xxx.h" 54 #include "prm3xxx.h" 55 #include "prm44xx.h" 56 57 /* 58 * omap_clk_init: points to a function that does the SoC-specific 59 * clock initializations 60 */ 61 int (*omap_clk_init)(void); 62 63 /* 64 * The machine specific code may provide the extra mapping besides the 65 * default mapping provided here. 66 */ 67 68 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 69 static struct map_desc omap24xx_io_desc[] __initdata = { 70 { 71 .virtual = L3_24XX_VIRT, 72 .pfn = __phys_to_pfn(L3_24XX_PHYS), 73 .length = L3_24XX_SIZE, 74 .type = MT_DEVICE 75 }, 76 { 77 .virtual = L4_24XX_VIRT, 78 .pfn = __phys_to_pfn(L4_24XX_PHYS), 79 .length = L4_24XX_SIZE, 80 .type = MT_DEVICE 81 }, 82 }; 83 84 #ifdef CONFIG_SOC_OMAP2420 85 static struct map_desc omap242x_io_desc[] __initdata = { 86 { 87 .virtual = DSP_MEM_2420_VIRT, 88 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 89 .length = DSP_MEM_2420_SIZE, 90 .type = MT_DEVICE 91 }, 92 { 93 .virtual = DSP_IPI_2420_VIRT, 94 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 95 .length = DSP_IPI_2420_SIZE, 96 .type = MT_DEVICE 97 }, 98 { 99 .virtual = DSP_MMU_2420_VIRT, 100 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 101 .length = DSP_MMU_2420_SIZE, 102 .type = MT_DEVICE 103 }, 104 }; 105 106 #endif 107 108 #ifdef CONFIG_SOC_OMAP2430 109 static struct map_desc omap243x_io_desc[] __initdata = { 110 { 111 .virtual = L4_WK_243X_VIRT, 112 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 113 .length = L4_WK_243X_SIZE, 114 .type = MT_DEVICE 115 }, 116 { 117 .virtual = OMAP243X_GPMC_VIRT, 118 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 119 .length = OMAP243X_GPMC_SIZE, 120 .type = MT_DEVICE 121 }, 122 { 123 .virtual = OMAP243X_SDRC_VIRT, 124 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 125 .length = OMAP243X_SDRC_SIZE, 126 .type = MT_DEVICE 127 }, 128 { 129 .virtual = OMAP243X_SMS_VIRT, 130 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 131 .length = OMAP243X_SMS_SIZE, 132 .type = MT_DEVICE 133 }, 134 }; 135 #endif 136 #endif 137 138 #ifdef CONFIG_ARCH_OMAP3 139 static struct map_desc omap34xx_io_desc[] __initdata = { 140 { 141 .virtual = L3_34XX_VIRT, 142 .pfn = __phys_to_pfn(L3_34XX_PHYS), 143 .length = L3_34XX_SIZE, 144 .type = MT_DEVICE 145 }, 146 { 147 .virtual = L4_34XX_VIRT, 148 .pfn = __phys_to_pfn(L4_34XX_PHYS), 149 .length = L4_34XX_SIZE, 150 .type = MT_DEVICE 151 }, 152 { 153 .virtual = OMAP34XX_GPMC_VIRT, 154 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 155 .length = OMAP34XX_GPMC_SIZE, 156 .type = MT_DEVICE 157 }, 158 { 159 .virtual = OMAP343X_SMS_VIRT, 160 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 161 .length = OMAP343X_SMS_SIZE, 162 .type = MT_DEVICE 163 }, 164 { 165 .virtual = OMAP343X_SDRC_VIRT, 166 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 167 .length = OMAP343X_SDRC_SIZE, 168 .type = MT_DEVICE 169 }, 170 { 171 .virtual = L4_PER_34XX_VIRT, 172 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 173 .length = L4_PER_34XX_SIZE, 174 .type = MT_DEVICE 175 }, 176 { 177 .virtual = L4_EMU_34XX_VIRT, 178 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 179 .length = L4_EMU_34XX_SIZE, 180 .type = MT_DEVICE 181 }, 182 #if defined(CONFIG_DEBUG_LL) && \ 183 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) 184 { 185 .virtual = ZOOM_UART_VIRT, 186 .pfn = __phys_to_pfn(ZOOM_UART_BASE), 187 .length = SZ_1M, 188 .type = MT_DEVICE 189 }, 190 #endif 191 }; 192 #endif 193 194 #ifdef CONFIG_SOC_TI81XX 195 static struct map_desc omapti81xx_io_desc[] __initdata = { 196 { 197 .virtual = L4_34XX_VIRT, 198 .pfn = __phys_to_pfn(L4_34XX_PHYS), 199 .length = L4_34XX_SIZE, 200 .type = MT_DEVICE 201 } 202 }; 203 #endif 204 205 #ifdef CONFIG_SOC_AM33XX 206 static struct map_desc omapam33xx_io_desc[] __initdata = { 207 { 208 .virtual = L4_34XX_VIRT, 209 .pfn = __phys_to_pfn(L4_34XX_PHYS), 210 .length = L4_34XX_SIZE, 211 .type = MT_DEVICE 212 }, 213 { 214 .virtual = L4_WK_AM33XX_VIRT, 215 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 216 .length = L4_WK_AM33XX_SIZE, 217 .type = MT_DEVICE 218 } 219 }; 220 #endif 221 222 #ifdef CONFIG_ARCH_OMAP4 223 static struct map_desc omap44xx_io_desc[] __initdata = { 224 { 225 .virtual = L3_44XX_VIRT, 226 .pfn = __phys_to_pfn(L3_44XX_PHYS), 227 .length = L3_44XX_SIZE, 228 .type = MT_DEVICE, 229 }, 230 { 231 .virtual = L4_44XX_VIRT, 232 .pfn = __phys_to_pfn(L4_44XX_PHYS), 233 .length = L4_44XX_SIZE, 234 .type = MT_DEVICE, 235 }, 236 { 237 .virtual = L4_PER_44XX_VIRT, 238 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 239 .length = L4_PER_44XX_SIZE, 240 .type = MT_DEVICE, 241 }, 242 #ifdef CONFIG_OMAP4_ERRATA_I688 243 { 244 .virtual = OMAP4_SRAM_VA, 245 .pfn = __phys_to_pfn(OMAP4_SRAM_PA), 246 .length = PAGE_SIZE, 247 .type = MT_MEMORY_SO, 248 }, 249 #endif 250 251 }; 252 #endif 253 254 #ifdef CONFIG_SOC_OMAP5 255 static struct map_desc omap54xx_io_desc[] __initdata = { 256 { 257 .virtual = L3_54XX_VIRT, 258 .pfn = __phys_to_pfn(L3_54XX_PHYS), 259 .length = L3_54XX_SIZE, 260 .type = MT_DEVICE, 261 }, 262 { 263 .virtual = L4_54XX_VIRT, 264 .pfn = __phys_to_pfn(L4_54XX_PHYS), 265 .length = L4_54XX_SIZE, 266 .type = MT_DEVICE, 267 }, 268 { 269 .virtual = L4_WK_54XX_VIRT, 270 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 271 .length = L4_WK_54XX_SIZE, 272 .type = MT_DEVICE, 273 }, 274 { 275 .virtual = L4_PER_54XX_VIRT, 276 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 277 .length = L4_PER_54XX_SIZE, 278 .type = MT_DEVICE, 279 }, 280 }; 281 #endif 282 283 #ifdef CONFIG_SOC_OMAP2420 284 void __init omap242x_map_io(void) 285 { 286 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 287 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 288 } 289 #endif 290 291 #ifdef CONFIG_SOC_OMAP2430 292 void __init omap243x_map_io(void) 293 { 294 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 295 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 296 } 297 #endif 298 299 #ifdef CONFIG_ARCH_OMAP3 300 void __init omap3_map_io(void) 301 { 302 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 303 } 304 #endif 305 306 #ifdef CONFIG_SOC_TI81XX 307 void __init ti81xx_map_io(void) 308 { 309 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 310 } 311 #endif 312 313 #ifdef CONFIG_SOC_AM33XX 314 void __init am33xx_map_io(void) 315 { 316 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 317 } 318 #endif 319 320 #ifdef CONFIG_ARCH_OMAP4 321 void __init omap4_map_io(void) 322 { 323 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 324 omap_barriers_init(); 325 } 326 #endif 327 328 #ifdef CONFIG_SOC_OMAP5 329 void __init omap5_map_io(void) 330 { 331 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 332 } 333 #endif 334 /* 335 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 336 * 337 * Sets the CORE DPLL3 M2 divider to the same value that it's at 338 * currently. This has the effect of setting the SDRC SDRAM AC timing 339 * registers to the values currently defined by the kernel. Currently 340 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 341 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 342 * or passes along the return value of clk_set_rate(). 343 */ 344 static int __init _omap2_init_reprogram_sdrc(void) 345 { 346 struct clk *dpll3_m2_ck; 347 int v = -EINVAL; 348 long rate; 349 350 if (!cpu_is_omap34xx()) 351 return 0; 352 353 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 354 if (IS_ERR(dpll3_m2_ck)) 355 return -EINVAL; 356 357 rate = clk_get_rate(dpll3_m2_ck); 358 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 359 v = clk_set_rate(dpll3_m2_ck, rate); 360 if (v) 361 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 362 363 clk_put(dpll3_m2_ck); 364 365 return v; 366 } 367 368 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 369 { 370 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 371 } 372 373 static void __init omap_hwmod_init_postsetup(void) 374 { 375 u8 postsetup_state; 376 377 /* Set the default postsetup state for all hwmods */ 378 #ifdef CONFIG_PM_RUNTIME 379 postsetup_state = _HWMOD_STATE_IDLE; 380 #else 381 postsetup_state = _HWMOD_STATE_ENABLED; 382 #endif 383 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 384 385 omap_pm_if_early_init(); 386 } 387 388 static void __init omap_common_late_init(void) 389 { 390 omap_mux_late_init(); 391 omap2_common_pm_late_init(); 392 omap_soc_device_init(); 393 } 394 395 #ifdef CONFIG_SOC_OMAP2420 396 void __init omap2420_init_early(void) 397 { 398 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 399 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 400 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 401 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), 402 NULL); 403 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); 404 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); 405 omap2xxx_check_revision(); 406 omap2xxx_prm_init(); 407 omap2xxx_cm_init(); 408 omap2xxx_voltagedomains_init(); 409 omap242x_powerdomains_init(); 410 omap242x_clockdomains_init(); 411 omap2420_hwmod_init(); 412 omap_hwmod_init_postsetup(); 413 omap_clk_init = omap2420_clk_init; 414 } 415 416 void __init omap2420_init_late(void) 417 { 418 omap_common_late_init(); 419 omap2_pm_init(); 420 omap2_clk_enable_autoidle_all(); 421 } 422 #endif 423 424 #ifdef CONFIG_SOC_OMAP2430 425 void __init omap2430_init_early(void) 426 { 427 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 428 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 429 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 430 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), 431 NULL); 432 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); 433 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); 434 omap2xxx_check_revision(); 435 omap2xxx_prm_init(); 436 omap2xxx_cm_init(); 437 omap2xxx_voltagedomains_init(); 438 omap243x_powerdomains_init(); 439 omap243x_clockdomains_init(); 440 omap2430_hwmod_init(); 441 omap_hwmod_init_postsetup(); 442 omap_clk_init = omap2430_clk_init; 443 } 444 445 void __init omap2430_init_late(void) 446 { 447 omap_common_late_init(); 448 omap2_pm_init(); 449 omap2_clk_enable_autoidle_all(); 450 } 451 #endif 452 453 /* 454 * Currently only board-omap3beagle.c should call this because of the 455 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 456 */ 457 #ifdef CONFIG_ARCH_OMAP3 458 void __init omap3_init_early(void) 459 { 460 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 461 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 462 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 463 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), 464 NULL); 465 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); 466 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 467 omap3xxx_check_revision(); 468 omap3xxx_check_features(); 469 omap3xxx_prm_init(); 470 omap3xxx_cm_init(); 471 omap3xxx_voltagedomains_init(); 472 omap3xxx_powerdomains_init(); 473 omap3xxx_clockdomains_init(); 474 omap3xxx_hwmod_init(); 475 omap_hwmod_init_postsetup(); 476 omap_clk_init = omap3xxx_clk_init; 477 } 478 479 void __init omap3430_init_early(void) 480 { 481 omap3_init_early(); 482 } 483 484 void __init omap35xx_init_early(void) 485 { 486 omap3_init_early(); 487 } 488 489 void __init omap3630_init_early(void) 490 { 491 omap3_init_early(); 492 } 493 494 void __init am35xx_init_early(void) 495 { 496 omap3_init_early(); 497 } 498 499 void __init ti81xx_init_early(void) 500 { 501 omap2_set_globals_tap(OMAP343X_CLASS, 502 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 503 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 504 NULL); 505 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); 506 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); 507 omap3xxx_check_revision(); 508 ti81xx_check_features(); 509 omap3xxx_voltagedomains_init(); 510 omap3xxx_powerdomains_init(); 511 omap3xxx_clockdomains_init(); 512 omap3xxx_hwmod_init(); 513 omap_hwmod_init_postsetup(); 514 omap_clk_init = omap3xxx_clk_init; 515 } 516 517 void __init omap3_init_late(void) 518 { 519 omap_common_late_init(); 520 omap3_pm_init(); 521 omap2_clk_enable_autoidle_all(); 522 } 523 524 void __init omap3430_init_late(void) 525 { 526 omap_common_late_init(); 527 omap3_pm_init(); 528 omap2_clk_enable_autoidle_all(); 529 } 530 531 void __init omap35xx_init_late(void) 532 { 533 omap_common_late_init(); 534 omap3_pm_init(); 535 omap2_clk_enable_autoidle_all(); 536 } 537 538 void __init omap3630_init_late(void) 539 { 540 omap_common_late_init(); 541 omap3_pm_init(); 542 omap2_clk_enable_autoidle_all(); 543 } 544 545 void __init am35xx_init_late(void) 546 { 547 omap_common_late_init(); 548 omap3_pm_init(); 549 omap2_clk_enable_autoidle_all(); 550 } 551 552 void __init ti81xx_init_late(void) 553 { 554 omap_common_late_init(); 555 omap3_pm_init(); 556 omap2_clk_enable_autoidle_all(); 557 } 558 #endif 559 560 #ifdef CONFIG_SOC_AM33XX 561 void __init am33xx_init_early(void) 562 { 563 omap2_set_globals_tap(AM335X_CLASS, 564 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 565 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 566 NULL); 567 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); 568 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); 569 omap3xxx_check_revision(); 570 ti81xx_check_features(); 571 am33xx_voltagedomains_init(); 572 am33xx_powerdomains_init(); 573 am33xx_clockdomains_init(); 574 am33xx_hwmod_init(); 575 omap_hwmod_init_postsetup(); 576 omap_clk_init = am33xx_clk_init; 577 } 578 #endif 579 580 #ifdef CONFIG_ARCH_OMAP4 581 void __init omap4430_init_early(void) 582 { 583 omap2_set_globals_tap(OMAP443X_CLASS, 584 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 585 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 586 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); 587 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); 588 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), 589 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); 590 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 591 omap_prm_base_init(); 592 omap_cm_base_init(); 593 omap4xxx_check_revision(); 594 omap4xxx_check_features(); 595 omap44xx_prm_init(); 596 omap44xx_voltagedomains_init(); 597 omap44xx_powerdomains_init(); 598 omap44xx_clockdomains_init(); 599 omap44xx_hwmod_init(); 600 omap_hwmod_init_postsetup(); 601 omap_clk_init = omap4xxx_clk_init; 602 } 603 604 void __init omap4430_init_late(void) 605 { 606 omap_common_late_init(); 607 omap4_pm_init(); 608 omap2_clk_enable_autoidle_all(); 609 } 610 #endif 611 612 #ifdef CONFIG_SOC_OMAP5 613 void __init omap5_init_early(void) 614 { 615 omap2_set_globals_tap(OMAP54XX_CLASS, 616 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 617 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 618 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); 619 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 620 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), 621 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 622 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 623 omap_prm_base_init(); 624 omap_cm_base_init(); 625 omap5xxx_check_revision(); 626 } 627 #endif 628 629 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 630 struct omap_sdrc_params *sdrc_cs1) 631 { 632 omap_sram_init(); 633 634 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 635 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 636 _omap2_init_reprogram_sdrc(); 637 } 638 } 639