1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-omap2/io.c 4 * 5 * OMAP2 I/O mapping code 6 * 7 * Copyright (C) 2005 Nokia Corporation 8 * Copyright (C) 2007-2009 Texas Instruments 9 * 10 * Author: 11 * Juha Yrjola <juha.yrjola@nokia.com> 12 * Syed Khasim <x0khasim@ti.com> 13 * 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 15 */ 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/clk.h> 21 22 #include <asm/tlb.h> 23 #include <asm/mach/map.h> 24 25 #include <linux/omap-dma.h> 26 27 #include "omap_hwmod.h" 28 #include "soc.h" 29 #include "iomap.h" 30 #include "voltage.h" 31 #include "powerdomain.h" 32 #include "clockdomain.h" 33 #include "common.h" 34 #include "clock.h" 35 #include "clock2xxx.h" 36 #include "sdrc.h" 37 #include "control.h" 38 #include "sram.h" 39 #include "cm2xxx.h" 40 #include "cm3xxx.h" 41 #include "cm33xx.h" 42 #include "cm44xx.h" 43 #include "prm.h" 44 #include "cm.h" 45 #include "prcm_mpu44xx.h" 46 #include "prminst44xx.h" 47 #include "prm2xxx.h" 48 #include "prm3xxx.h" 49 #include "prm33xx.h" 50 #include "prm44xx.h" 51 #include "opp2xxx.h" 52 #include "omap-secure.h" 53 54 /* 55 * omap_clk_soc_init: points to a function that does the SoC-specific 56 * clock initializations 57 */ 58 static int (*omap_clk_soc_init)(void); 59 60 /* 61 * The machine specific code may provide the extra mapping besides the 62 * default mapping provided here. 63 */ 64 65 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 66 static struct map_desc omap24xx_io_desc[] __initdata = { 67 { 68 .virtual = L3_24XX_VIRT, 69 .pfn = __phys_to_pfn(L3_24XX_PHYS), 70 .length = L3_24XX_SIZE, 71 .type = MT_DEVICE 72 }, 73 { 74 .virtual = L4_24XX_VIRT, 75 .pfn = __phys_to_pfn(L4_24XX_PHYS), 76 .length = L4_24XX_SIZE, 77 .type = MT_DEVICE 78 }, 79 }; 80 81 #ifdef CONFIG_SOC_OMAP2420 82 static struct map_desc omap242x_io_desc[] __initdata = { 83 { 84 .virtual = DSP_MEM_2420_VIRT, 85 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 86 .length = DSP_MEM_2420_SIZE, 87 .type = MT_DEVICE 88 }, 89 { 90 .virtual = DSP_IPI_2420_VIRT, 91 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 92 .length = DSP_IPI_2420_SIZE, 93 .type = MT_DEVICE 94 }, 95 { 96 .virtual = DSP_MMU_2420_VIRT, 97 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 98 .length = DSP_MMU_2420_SIZE, 99 .type = MT_DEVICE 100 }, 101 }; 102 103 #endif 104 105 #ifdef CONFIG_SOC_OMAP2430 106 static struct map_desc omap243x_io_desc[] __initdata = { 107 { 108 .virtual = L4_WK_243X_VIRT, 109 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 110 .length = L4_WK_243X_SIZE, 111 .type = MT_DEVICE 112 }, 113 { 114 .virtual = OMAP243X_GPMC_VIRT, 115 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 116 .length = OMAP243X_GPMC_SIZE, 117 .type = MT_DEVICE 118 }, 119 { 120 .virtual = OMAP243X_SDRC_VIRT, 121 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 122 .length = OMAP243X_SDRC_SIZE, 123 .type = MT_DEVICE 124 }, 125 { 126 .virtual = OMAP243X_SMS_VIRT, 127 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 128 .length = OMAP243X_SMS_SIZE, 129 .type = MT_DEVICE 130 }, 131 }; 132 #endif 133 #endif 134 135 #ifdef CONFIG_ARCH_OMAP3 136 static struct map_desc omap34xx_io_desc[] __initdata = { 137 { 138 .virtual = L3_34XX_VIRT, 139 .pfn = __phys_to_pfn(L3_34XX_PHYS), 140 .length = L3_34XX_SIZE, 141 .type = MT_DEVICE 142 }, 143 { 144 .virtual = L4_34XX_VIRT, 145 .pfn = __phys_to_pfn(L4_34XX_PHYS), 146 .length = L4_34XX_SIZE, 147 .type = MT_DEVICE 148 }, 149 { 150 .virtual = OMAP34XX_GPMC_VIRT, 151 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 152 .length = OMAP34XX_GPMC_SIZE, 153 .type = MT_DEVICE 154 }, 155 { 156 .virtual = OMAP343X_SMS_VIRT, 157 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 158 .length = OMAP343X_SMS_SIZE, 159 .type = MT_DEVICE 160 }, 161 { 162 .virtual = OMAP343X_SDRC_VIRT, 163 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 164 .length = OMAP343X_SDRC_SIZE, 165 .type = MT_DEVICE 166 }, 167 { 168 .virtual = L4_PER_34XX_VIRT, 169 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 170 .length = L4_PER_34XX_SIZE, 171 .type = MT_DEVICE 172 }, 173 { 174 .virtual = L4_EMU_34XX_VIRT, 175 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 176 .length = L4_EMU_34XX_SIZE, 177 .type = MT_DEVICE 178 }, 179 }; 180 #endif 181 182 #ifdef CONFIG_SOC_TI81XX 183 static struct map_desc omapti81xx_io_desc[] __initdata = { 184 { 185 .virtual = L4_34XX_VIRT, 186 .pfn = __phys_to_pfn(L4_34XX_PHYS), 187 .length = L4_34XX_SIZE, 188 .type = MT_DEVICE 189 } 190 }; 191 #endif 192 193 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 194 static struct map_desc omapam33xx_io_desc[] __initdata = { 195 { 196 .virtual = L4_34XX_VIRT, 197 .pfn = __phys_to_pfn(L4_34XX_PHYS), 198 .length = L4_34XX_SIZE, 199 .type = MT_DEVICE 200 }, 201 { 202 .virtual = L4_WK_AM33XX_VIRT, 203 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 204 .length = L4_WK_AM33XX_SIZE, 205 .type = MT_DEVICE 206 } 207 }; 208 #endif 209 210 #ifdef CONFIG_ARCH_OMAP4 211 static struct map_desc omap44xx_io_desc[] __initdata = { 212 { 213 .virtual = L3_44XX_VIRT, 214 .pfn = __phys_to_pfn(L3_44XX_PHYS), 215 .length = L3_44XX_SIZE, 216 .type = MT_DEVICE, 217 }, 218 { 219 .virtual = L4_44XX_VIRT, 220 .pfn = __phys_to_pfn(L4_44XX_PHYS), 221 .length = L4_44XX_SIZE, 222 .type = MT_DEVICE, 223 }, 224 { 225 .virtual = L4_PER_44XX_VIRT, 226 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 227 .length = L4_PER_44XX_SIZE, 228 .type = MT_DEVICE, 229 }, 230 }; 231 #endif 232 233 #ifdef CONFIG_SOC_OMAP5 234 static struct map_desc omap54xx_io_desc[] __initdata = { 235 { 236 .virtual = L3_54XX_VIRT, 237 .pfn = __phys_to_pfn(L3_54XX_PHYS), 238 .length = L3_54XX_SIZE, 239 .type = MT_DEVICE, 240 }, 241 { 242 .virtual = L4_54XX_VIRT, 243 .pfn = __phys_to_pfn(L4_54XX_PHYS), 244 .length = L4_54XX_SIZE, 245 .type = MT_DEVICE, 246 }, 247 { 248 .virtual = L4_WK_54XX_VIRT, 249 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 250 .length = L4_WK_54XX_SIZE, 251 .type = MT_DEVICE, 252 }, 253 { 254 .virtual = L4_PER_54XX_VIRT, 255 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 256 .length = L4_PER_54XX_SIZE, 257 .type = MT_DEVICE, 258 }, 259 }; 260 #endif 261 262 #ifdef CONFIG_SOC_DRA7XX 263 static struct map_desc dra7xx_io_desc[] __initdata = { 264 { 265 .virtual = L4_CFG_MPU_DRA7XX_VIRT, 266 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS), 267 .length = L4_CFG_MPU_DRA7XX_SIZE, 268 .type = MT_DEVICE, 269 }, 270 { 271 .virtual = L3_MAIN_SN_DRA7XX_VIRT, 272 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS), 273 .length = L3_MAIN_SN_DRA7XX_SIZE, 274 .type = MT_DEVICE, 275 }, 276 { 277 .virtual = L4_PER1_DRA7XX_VIRT, 278 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS), 279 .length = L4_PER1_DRA7XX_SIZE, 280 .type = MT_DEVICE, 281 }, 282 { 283 .virtual = L4_PER2_DRA7XX_VIRT, 284 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS), 285 .length = L4_PER2_DRA7XX_SIZE, 286 .type = MT_DEVICE, 287 }, 288 { 289 .virtual = L4_PER3_DRA7XX_VIRT, 290 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS), 291 .length = L4_PER3_DRA7XX_SIZE, 292 .type = MT_DEVICE, 293 }, 294 { 295 .virtual = L4_CFG_DRA7XX_VIRT, 296 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS), 297 .length = L4_CFG_DRA7XX_SIZE, 298 .type = MT_DEVICE, 299 }, 300 { 301 .virtual = L4_WKUP_DRA7XX_VIRT, 302 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS), 303 .length = L4_WKUP_DRA7XX_SIZE, 304 .type = MT_DEVICE, 305 }, 306 }; 307 #endif 308 309 #ifdef CONFIG_SOC_OMAP2420 310 void __init omap242x_map_io(void) 311 { 312 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 313 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 314 } 315 #endif 316 317 #ifdef CONFIG_SOC_OMAP2430 318 void __init omap243x_map_io(void) 319 { 320 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 321 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 322 } 323 #endif 324 325 #ifdef CONFIG_ARCH_OMAP3 326 void __init omap3_map_io(void) 327 { 328 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 329 } 330 #endif 331 332 #ifdef CONFIG_SOC_TI81XX 333 void __init ti81xx_map_io(void) 334 { 335 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 336 } 337 #endif 338 339 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 340 void __init am33xx_map_io(void) 341 { 342 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 343 } 344 #endif 345 346 #ifdef CONFIG_ARCH_OMAP4 347 void __init omap4_map_io(void) 348 { 349 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 350 omap_barriers_init(); 351 } 352 #endif 353 354 #ifdef CONFIG_SOC_OMAP5 355 void __init omap5_map_io(void) 356 { 357 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 358 omap_barriers_init(); 359 } 360 #endif 361 362 #ifdef CONFIG_SOC_DRA7XX 363 void __init dra7xx_map_io(void) 364 { 365 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); 366 omap_barriers_init(); 367 } 368 #endif 369 /* 370 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 371 * 372 * Sets the CORE DPLL3 M2 divider to the same value that it's at 373 * currently. This has the effect of setting the SDRC SDRAM AC timing 374 * registers to the values currently defined by the kernel. Currently 375 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 376 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 377 * or passes along the return value of clk_set_rate(). 378 */ 379 static int __init _omap2_init_reprogram_sdrc(void) 380 { 381 struct clk *dpll3_m2_ck; 382 int v = -EINVAL; 383 long rate; 384 385 if (!cpu_is_omap34xx()) 386 return 0; 387 388 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 389 if (IS_ERR(dpll3_m2_ck)) 390 return -EINVAL; 391 392 rate = clk_get_rate(dpll3_m2_ck); 393 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 394 v = clk_set_rate(dpll3_m2_ck, rate); 395 if (v) 396 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 397 398 clk_put(dpll3_m2_ck); 399 400 return v; 401 } 402 403 #ifdef CONFIG_OMAP_HWMOD 404 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 405 { 406 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 407 } 408 409 static void __init __maybe_unused omap_hwmod_init_postsetup(void) 410 { 411 u8 postsetup_state = _HWMOD_STATE_DEFAULT; 412 413 /* Set the default postsetup state for all hwmods */ 414 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 415 } 416 #else 417 static inline void omap_hwmod_init_postsetup(void) 418 { 419 } 420 #endif 421 422 #ifdef CONFIG_SOC_OMAP2420 423 void __init omap2420_init_early(void) 424 { 425 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 426 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 427 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 428 omap2_control_base_init(); 429 omap2xxx_check_revision(); 430 omap2_prcm_base_init(); 431 omap2xxx_voltagedomains_init(); 432 omap242x_powerdomains_init(); 433 omap242x_clockdomains_init(); 434 omap2420_hwmod_init(); 435 omap_hwmod_init_postsetup(); 436 omap_clk_soc_init = omap2420_dt_clk_init; 437 rate_table = omap2420_rate_table; 438 } 439 440 void __init omap2420_init_late(void) 441 { 442 omap_pm_soc_init = omap2_pm_init; 443 } 444 #endif 445 446 #ifdef CONFIG_SOC_OMAP2430 447 void __init omap2430_init_early(void) 448 { 449 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 450 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 451 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 452 omap2_control_base_init(); 453 omap2xxx_check_revision(); 454 omap2_prcm_base_init(); 455 omap2xxx_voltagedomains_init(); 456 omap243x_powerdomains_init(); 457 omap243x_clockdomains_init(); 458 omap2430_hwmod_init(); 459 omap_hwmod_init_postsetup(); 460 omap_clk_soc_init = omap2430_dt_clk_init; 461 rate_table = omap2430_rate_table; 462 } 463 464 void __init omap2430_init_late(void) 465 { 466 omap_pm_soc_init = omap2_pm_init; 467 } 468 #endif 469 470 /* 471 * Currently only board-omap3beagle.c should call this because of the 472 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 473 */ 474 #ifdef CONFIG_ARCH_OMAP3 475 void __init omap3_init_early(void) 476 { 477 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 478 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 479 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 480 omap2_control_base_init(); 481 omap3xxx_check_revision(); 482 omap3xxx_check_features(); 483 omap2_prcm_base_init(); 484 omap3xxx_voltagedomains_init(); 485 omap3xxx_powerdomains_init(); 486 omap3xxx_clockdomains_init(); 487 omap3xxx_hwmod_init(); 488 omap_hwmod_init_postsetup(); 489 omap_secure_init(); 490 } 491 492 void __init omap3430_init_early(void) 493 { 494 omap3_init_early(); 495 omap_clk_soc_init = omap3430_dt_clk_init; 496 } 497 498 void __init omap35xx_init_early(void) 499 { 500 omap3_init_early(); 501 omap_clk_soc_init = omap3430_dt_clk_init; 502 } 503 504 void __init omap3630_init_early(void) 505 { 506 omap3_init_early(); 507 omap_clk_soc_init = omap3630_dt_clk_init; 508 } 509 510 void __init am35xx_init_early(void) 511 { 512 omap3_init_early(); 513 omap_clk_soc_init = am35xx_dt_clk_init; 514 } 515 516 void __init omap3_init_late(void) 517 { 518 omap_pm_soc_init = omap3_pm_init; 519 } 520 521 void __init ti81xx_init_late(void) 522 { 523 omap_pm_soc_init = omap_pm_nop_init; 524 } 525 #endif 526 527 #ifdef CONFIG_SOC_TI81XX 528 void __init ti814x_init_early(void) 529 { 530 omap2_set_globals_tap(TI814X_CLASS, 531 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 532 omap2_control_base_init(); 533 omap3xxx_check_revision(); 534 ti81xx_check_features(); 535 omap2_prcm_base_init(); 536 omap3xxx_voltagedomains_init(); 537 omap3xxx_powerdomains_init(); 538 ti814x_clockdomains_init(); 539 dm814x_hwmod_init(); 540 omap_hwmod_init_postsetup(); 541 omap_clk_soc_init = dm814x_dt_clk_init; 542 omap_secure_init(); 543 } 544 545 void __init ti816x_init_early(void) 546 { 547 omap2_set_globals_tap(TI816X_CLASS, 548 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 549 omap2_control_base_init(); 550 omap3xxx_check_revision(); 551 ti81xx_check_features(); 552 omap2_prcm_base_init(); 553 omap3xxx_voltagedomains_init(); 554 omap3xxx_powerdomains_init(); 555 ti816x_clockdomains_init(); 556 dm816x_hwmod_init(); 557 omap_hwmod_init_postsetup(); 558 omap_clk_soc_init = dm816x_dt_clk_init; 559 omap_secure_init(); 560 } 561 #endif 562 563 #ifdef CONFIG_SOC_AM33XX 564 void __init am33xx_init_early(void) 565 { 566 omap2_set_globals_tap(AM335X_CLASS, 567 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 568 omap2_control_base_init(); 569 omap3xxx_check_revision(); 570 am33xx_check_features(); 571 omap2_prcm_base_init(); 572 am33xx_powerdomains_init(); 573 am33xx_clockdomains_init(); 574 omap_clk_soc_init = am33xx_dt_clk_init; 575 omap_secure_init(); 576 } 577 578 void __init am33xx_init_late(void) 579 { 580 omap_pm_soc_init = amx3_common_pm_init; 581 } 582 #endif 583 584 #ifdef CONFIG_SOC_AM43XX 585 void __init am43xx_init_early(void) 586 { 587 omap2_set_globals_tap(AM335X_CLASS, 588 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 589 omap2_control_base_init(); 590 omap3xxx_check_revision(); 591 am33xx_check_features(); 592 omap2_prcm_base_init(); 593 am43xx_powerdomains_init(); 594 am43xx_clockdomains_init(); 595 omap_l2_cache_init(); 596 omap_clk_soc_init = am43xx_dt_clk_init; 597 omap_secure_init(); 598 } 599 600 void __init am43xx_init_late(void) 601 { 602 omap_pm_soc_init = amx3_common_pm_init; 603 } 604 #endif 605 606 #ifdef CONFIG_ARCH_OMAP4 607 void __init omap4430_init_early(void) 608 { 609 omap2_set_globals_tap(OMAP443X_CLASS, 610 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 611 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 612 omap2_control_base_init(); 613 omap4xxx_check_revision(); 614 omap4xxx_check_features(); 615 omap2_prcm_base_init(); 616 omap4_sar_ram_init(); 617 omap4_mpuss_early_init(); 618 omap4_pm_init_early(); 619 omap44xx_voltagedomains_init(); 620 omap44xx_powerdomains_init(); 621 omap44xx_clockdomains_init(); 622 omap_l2_cache_init(); 623 omap_clk_soc_init = omap4xxx_dt_clk_init; 624 omap_secure_init(); 625 } 626 627 void __init omap4430_init_late(void) 628 { 629 omap_pm_soc_init = omap4_pm_init; 630 } 631 #endif 632 633 #ifdef CONFIG_SOC_OMAP5 634 void __init omap5_init_early(void) 635 { 636 omap2_set_globals_tap(OMAP54XX_CLASS, 637 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 638 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 639 omap2_control_base_init(); 640 omap2_prcm_base_init(); 641 omap5xxx_check_revision(); 642 omap4_sar_ram_init(); 643 omap4_mpuss_early_init(); 644 omap4_pm_init_early(); 645 omap54xx_voltagedomains_init(); 646 omap54xx_powerdomains_init(); 647 omap54xx_clockdomains_init(); 648 omap_clk_soc_init = omap5xxx_dt_clk_init; 649 omap_secure_init(); 650 } 651 652 void __init omap5_init_late(void) 653 { 654 omap_pm_soc_init = omap4_pm_init; 655 } 656 #endif 657 658 #ifdef CONFIG_SOC_DRA7XX 659 void __init dra7xx_init_early(void) 660 { 661 omap2_set_globals_tap(DRA7XX_CLASS, 662 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 663 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 664 omap2_control_base_init(); 665 omap4_pm_init_early(); 666 omap2_prcm_base_init(); 667 dra7xxx_check_revision(); 668 dra7xx_powerdomains_init(); 669 dra7xx_clockdomains_init(); 670 omap_clk_soc_init = dra7xx_dt_clk_init; 671 omap_secure_init(); 672 } 673 674 void __init dra7xx_init_late(void) 675 { 676 omap_pm_soc_init = omap4_pm_init; 677 } 678 #endif 679 680 681 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 682 struct omap_sdrc_params *sdrc_cs1) 683 { 684 omap_sram_init(); 685 686 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 687 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 688 _omap2_init_reprogram_sdrc(); 689 } 690 } 691 692 int __init omap_clk_init(void) 693 { 694 int ret = 0; 695 696 if (!omap_clk_soc_init) 697 return 0; 698 699 ti_clk_init_features(); 700 701 omap2_clk_setup_ll_ops(); 702 703 ret = omap_control_init(); 704 if (ret) 705 return ret; 706 707 ret = omap_prcm_init(); 708 if (ret) 709 return ret; 710 711 of_clk_init(NULL); 712 713 ti_dt_clk_init_retry_clks(); 714 715 ti_dt_clockdomains_setup(); 716 717 ret = omap_clk_soc_init(); 718 719 return ret; 720 } 721