1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/omapfb.h> 25 26 #include <asm/tlb.h> 27 28 #include <asm/mach/map.h> 29 30 #include <plat/sram.h> 31 #include <plat/sdrc.h> 32 #include <plat/serial.h> 33 34 #include "clock2xxx.h" 35 #include "clock3xxx.h" 36 #include "clock44xx.h" 37 38 #include "common.h" 39 #include <plat/omap-pm.h> 40 #include "voltage.h" 41 #include "powerdomain.h" 42 43 #include "clockdomain.h" 44 #include <plat/omap_hwmod.h> 45 #include <plat/multi.h> 46 #include "common.h" 47 48 /* 49 * The machine specific code may provide the extra mapping besides the 50 * default mapping provided here. 51 */ 52 53 #ifdef CONFIG_ARCH_OMAP2 54 static struct map_desc omap24xx_io_desc[] __initdata = { 55 { 56 .virtual = L3_24XX_VIRT, 57 .pfn = __phys_to_pfn(L3_24XX_PHYS), 58 .length = L3_24XX_SIZE, 59 .type = MT_DEVICE 60 }, 61 { 62 .virtual = L4_24XX_VIRT, 63 .pfn = __phys_to_pfn(L4_24XX_PHYS), 64 .length = L4_24XX_SIZE, 65 .type = MT_DEVICE 66 }, 67 }; 68 69 #ifdef CONFIG_SOC_OMAP2420 70 static struct map_desc omap242x_io_desc[] __initdata = { 71 { 72 .virtual = DSP_MEM_2420_VIRT, 73 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 74 .length = DSP_MEM_2420_SIZE, 75 .type = MT_DEVICE 76 }, 77 { 78 .virtual = DSP_IPI_2420_VIRT, 79 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 80 .length = DSP_IPI_2420_SIZE, 81 .type = MT_DEVICE 82 }, 83 { 84 .virtual = DSP_MMU_2420_VIRT, 85 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 86 .length = DSP_MMU_2420_SIZE, 87 .type = MT_DEVICE 88 }, 89 }; 90 91 #endif 92 93 #ifdef CONFIG_SOC_OMAP2430 94 static struct map_desc omap243x_io_desc[] __initdata = { 95 { 96 .virtual = L4_WK_243X_VIRT, 97 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 98 .length = L4_WK_243X_SIZE, 99 .type = MT_DEVICE 100 }, 101 { 102 .virtual = OMAP243X_GPMC_VIRT, 103 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 104 .length = OMAP243X_GPMC_SIZE, 105 .type = MT_DEVICE 106 }, 107 { 108 .virtual = OMAP243X_SDRC_VIRT, 109 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 110 .length = OMAP243X_SDRC_SIZE, 111 .type = MT_DEVICE 112 }, 113 { 114 .virtual = OMAP243X_SMS_VIRT, 115 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 116 .length = OMAP243X_SMS_SIZE, 117 .type = MT_DEVICE 118 }, 119 }; 120 #endif 121 #endif 122 123 #ifdef CONFIG_ARCH_OMAP3 124 static struct map_desc omap34xx_io_desc[] __initdata = { 125 { 126 .virtual = L3_34XX_VIRT, 127 .pfn = __phys_to_pfn(L3_34XX_PHYS), 128 .length = L3_34XX_SIZE, 129 .type = MT_DEVICE 130 }, 131 { 132 .virtual = L4_34XX_VIRT, 133 .pfn = __phys_to_pfn(L4_34XX_PHYS), 134 .length = L4_34XX_SIZE, 135 .type = MT_DEVICE 136 }, 137 { 138 .virtual = OMAP34XX_GPMC_VIRT, 139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 140 .length = OMAP34XX_GPMC_SIZE, 141 .type = MT_DEVICE 142 }, 143 { 144 .virtual = OMAP343X_SMS_VIRT, 145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 146 .length = OMAP343X_SMS_SIZE, 147 .type = MT_DEVICE 148 }, 149 { 150 .virtual = OMAP343X_SDRC_VIRT, 151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 152 .length = OMAP343X_SDRC_SIZE, 153 .type = MT_DEVICE 154 }, 155 { 156 .virtual = L4_PER_34XX_VIRT, 157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 158 .length = L4_PER_34XX_SIZE, 159 .type = MT_DEVICE 160 }, 161 { 162 .virtual = L4_EMU_34XX_VIRT, 163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 164 .length = L4_EMU_34XX_SIZE, 165 .type = MT_DEVICE 166 }, 167 #if defined(CONFIG_DEBUG_LL) && \ 168 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) 169 { 170 .virtual = ZOOM_UART_VIRT, 171 .pfn = __phys_to_pfn(ZOOM_UART_BASE), 172 .length = SZ_1M, 173 .type = MT_DEVICE 174 }, 175 #endif 176 }; 177 #endif 178 179 #ifdef CONFIG_SOC_OMAPTI816X 180 static struct map_desc omapti816x_io_desc[] __initdata = { 181 { 182 .virtual = L4_34XX_VIRT, 183 .pfn = __phys_to_pfn(L4_34XX_PHYS), 184 .length = L4_34XX_SIZE, 185 .type = MT_DEVICE 186 } 187 }; 188 #endif 189 190 #ifdef CONFIG_SOC_OMAPAM33XX 191 static struct map_desc omapam33xx_io_desc[] __initdata = { 192 { 193 .virtual = L4_34XX_VIRT, 194 .pfn = __phys_to_pfn(L4_34XX_PHYS), 195 .length = L4_34XX_SIZE, 196 .type = MT_DEVICE 197 }, 198 { 199 .virtual = L4_WK_AM33XX_VIRT, 200 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 201 .length = L4_WK_AM33XX_SIZE, 202 .type = MT_DEVICE 203 } 204 }; 205 #endif 206 207 #ifdef CONFIG_ARCH_OMAP4 208 static struct map_desc omap44xx_io_desc[] __initdata = { 209 { 210 .virtual = L3_44XX_VIRT, 211 .pfn = __phys_to_pfn(L3_44XX_PHYS), 212 .length = L3_44XX_SIZE, 213 .type = MT_DEVICE, 214 }, 215 { 216 .virtual = L4_44XX_VIRT, 217 .pfn = __phys_to_pfn(L4_44XX_PHYS), 218 .length = L4_44XX_SIZE, 219 .type = MT_DEVICE, 220 }, 221 { 222 .virtual = OMAP44XX_GPMC_VIRT, 223 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), 224 .length = OMAP44XX_GPMC_SIZE, 225 .type = MT_DEVICE, 226 }, 227 { 228 .virtual = OMAP44XX_EMIF1_VIRT, 229 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), 230 .length = OMAP44XX_EMIF1_SIZE, 231 .type = MT_DEVICE, 232 }, 233 { 234 .virtual = OMAP44XX_EMIF2_VIRT, 235 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), 236 .length = OMAP44XX_EMIF2_SIZE, 237 .type = MT_DEVICE, 238 }, 239 { 240 .virtual = OMAP44XX_DMM_VIRT, 241 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), 242 .length = OMAP44XX_DMM_SIZE, 243 .type = MT_DEVICE, 244 }, 245 { 246 .virtual = L4_PER_44XX_VIRT, 247 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 248 .length = L4_PER_44XX_SIZE, 249 .type = MT_DEVICE, 250 }, 251 { 252 .virtual = L4_EMU_44XX_VIRT, 253 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), 254 .length = L4_EMU_44XX_SIZE, 255 .type = MT_DEVICE, 256 }, 257 }; 258 #endif 259 260 #ifdef CONFIG_SOC_OMAP2420 261 void __init omap242x_map_common_io(void) 262 { 263 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 264 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 265 } 266 #endif 267 268 #ifdef CONFIG_SOC_OMAP2430 269 void __init omap243x_map_common_io(void) 270 { 271 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 272 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 273 } 274 #endif 275 276 #ifdef CONFIG_ARCH_OMAP3 277 void __init omap34xx_map_common_io(void) 278 { 279 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 280 } 281 #endif 282 283 #ifdef CONFIG_SOC_OMAPTI816X 284 void __init omapti816x_map_common_io(void) 285 { 286 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); 287 } 288 #endif 289 290 #ifdef CONFIG_SOC_OMAPAM33XX 291 void __init omapam33xx_map_common_io(void) 292 { 293 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 294 } 295 #endif 296 297 #ifdef CONFIG_ARCH_OMAP4 298 void __init omap44xx_map_common_io(void) 299 { 300 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 301 } 302 #endif 303 304 /* 305 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 306 * 307 * Sets the CORE DPLL3 M2 divider to the same value that it's at 308 * currently. This has the effect of setting the SDRC SDRAM AC timing 309 * registers to the values currently defined by the kernel. Currently 310 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 311 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 312 * or passes along the return value of clk_set_rate(). 313 */ 314 static int __init _omap2_init_reprogram_sdrc(void) 315 { 316 struct clk *dpll3_m2_ck; 317 int v = -EINVAL; 318 long rate; 319 320 if (!cpu_is_omap34xx()) 321 return 0; 322 323 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 324 if (IS_ERR(dpll3_m2_ck)) 325 return -EINVAL; 326 327 rate = clk_get_rate(dpll3_m2_ck); 328 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 329 v = clk_set_rate(dpll3_m2_ck, rate); 330 if (v) 331 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 332 333 clk_put(dpll3_m2_ck); 334 335 return v; 336 } 337 338 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 339 { 340 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 341 } 342 343 static void __init omap_common_init_early(void) 344 { 345 omap2_check_revision(); 346 omap_init_consistent_dma_size(); 347 } 348 349 static void __init omap_hwmod_init_postsetup(void) 350 { 351 u8 postsetup_state; 352 353 /* Set the default postsetup state for all hwmods */ 354 #ifdef CONFIG_PM_RUNTIME 355 postsetup_state = _HWMOD_STATE_IDLE; 356 #else 357 postsetup_state = _HWMOD_STATE_ENABLED; 358 #endif 359 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 360 361 /* 362 * Set the default postsetup state for unusual modules (like 363 * MPU WDT). 364 * 365 * The postsetup_state is not actually used until 366 * omap_hwmod_late_init(), so boards that desire full watchdog 367 * coverage of kernel initialization can reprogram the 368 * postsetup_state between the calls to 369 * omap2_init_common_infra() and omap_sdrc_init(). 370 * 371 * XXX ideally we could detect whether the MPU WDT was currently 372 * enabled here and make this conditional 373 */ 374 postsetup_state = _HWMOD_STATE_DISABLED; 375 omap_hwmod_for_each_by_class("wd_timer", 376 _set_hwmod_postsetup_state, 377 &postsetup_state); 378 379 omap_pm_if_early_init(); 380 } 381 382 #ifdef CONFIG_ARCH_OMAP2 383 void __init omap2420_init_early(void) 384 { 385 omap2_set_globals_242x(); 386 omap_common_init_early(); 387 omap2xxx_voltagedomains_init(); 388 omap242x_powerdomains_init(); 389 omap242x_clockdomains_init(); 390 omap2420_hwmod_init(); 391 omap_hwmod_init_postsetup(); 392 omap2420_clk_init(); 393 } 394 395 void __init omap2430_init_early(void) 396 { 397 omap2_set_globals_243x(); 398 omap_common_init_early(); 399 omap2xxx_voltagedomains_init(); 400 omap243x_powerdomains_init(); 401 omap243x_clockdomains_init(); 402 omap2430_hwmod_init(); 403 omap_hwmod_init_postsetup(); 404 omap2430_clk_init(); 405 } 406 #endif 407 408 /* 409 * Currently only board-omap3beagle.c should call this because of the 410 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 411 */ 412 #ifdef CONFIG_ARCH_OMAP3 413 void __init omap3_init_early(void) 414 { 415 omap2_set_globals_3xxx(); 416 omap_common_init_early(); 417 omap3xxx_voltagedomains_init(); 418 omap3xxx_powerdomains_init(); 419 omap3xxx_clockdomains_init(); 420 omap3xxx_hwmod_init(); 421 omap_hwmod_init_postsetup(); 422 omap3xxx_clk_init(); 423 } 424 425 void __init omap3430_init_early(void) 426 { 427 omap3_init_early(); 428 } 429 430 void __init omap35xx_init_early(void) 431 { 432 omap3_init_early(); 433 } 434 435 void __init omap3630_init_early(void) 436 { 437 omap3_init_early(); 438 } 439 440 void __init am35xx_init_early(void) 441 { 442 omap3_init_early(); 443 } 444 445 void __init ti816x_init_early(void) 446 { 447 omap2_set_globals_ti816x(); 448 omap_common_init_early(); 449 omap3xxx_voltagedomains_init(); 450 omap3xxx_powerdomains_init(); 451 omap3xxx_clockdomains_init(); 452 omap3xxx_hwmod_init(); 453 omap_hwmod_init_postsetup(); 454 omap3xxx_clk_init(); 455 } 456 #endif 457 458 #ifdef CONFIG_ARCH_OMAP4 459 void __init omap4430_init_early(void) 460 { 461 omap2_set_globals_443x(); 462 omap_common_init_early(); 463 omap44xx_voltagedomains_init(); 464 omap44xx_powerdomains_init(); 465 omap44xx_clockdomains_init(); 466 omap44xx_hwmod_init(); 467 omap_hwmod_init_postsetup(); 468 omap4xxx_clk_init(); 469 } 470 #endif 471 472 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 473 struct omap_sdrc_params *sdrc_cs1) 474 { 475 omap_sram_init(); 476 477 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 478 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 479 _omap2_init_reprogram_sdrc(); 480 } 481 } 482 483 /* 484 * NOTE: Please use ioremap + __raw_read/write where possible instead of these 485 */ 486 487 u8 omap_readb(u32 pa) 488 { 489 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); 490 } 491 EXPORT_SYMBOL(omap_readb); 492 493 u16 omap_readw(u32 pa) 494 { 495 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); 496 } 497 EXPORT_SYMBOL(omap_readw); 498 499 u32 omap_readl(u32 pa) 500 { 501 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); 502 } 503 EXPORT_SYMBOL(omap_readl); 504 505 void omap_writeb(u8 v, u32 pa) 506 { 507 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); 508 } 509 EXPORT_SYMBOL(omap_writeb); 510 511 void omap_writew(u16 v, u32 pa) 512 { 513 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); 514 } 515 EXPORT_SYMBOL(omap_writew); 516 517 void omap_writel(u32 v, u32 pa) 518 { 519 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); 520 } 521 EXPORT_SYMBOL(omap_writel); 522