1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/omapfb.h> 26 27 #include <asm/tlb.h> 28 29 #include <asm/mach/map.h> 30 31 #include <plat/mux.h> 32 #include <plat/sram.h> 33 #include <plat/sdrc.h> 34 #include <plat/gpmc.h> 35 #include <plat/serial.h> 36 #include <plat/vram.h> 37 38 #include "clock2xxx.h" 39 #include "clock34xx.h" 40 #include "clock44xx.h" 41 42 #include <plat/omap-pm.h> 43 #include <plat/powerdomain.h> 44 #include "powerdomains.h" 45 46 #include <plat/clockdomain.h> 47 #include "clockdomains.h" 48 #include <plat/omap_hwmod.h> 49 #include "omap_hwmod_2420.h" 50 #include "omap_hwmod_2430.h" 51 #include "omap_hwmod_34xx.h" 52 53 /* 54 * The machine specific code may provide the extra mapping besides the 55 * default mapping provided here. 56 */ 57 58 #ifdef CONFIG_ARCH_OMAP2 59 static struct map_desc omap24xx_io_desc[] __initdata = { 60 { 61 .virtual = L3_24XX_VIRT, 62 .pfn = __phys_to_pfn(L3_24XX_PHYS), 63 .length = L3_24XX_SIZE, 64 .type = MT_DEVICE 65 }, 66 { 67 .virtual = L4_24XX_VIRT, 68 .pfn = __phys_to_pfn(L4_24XX_PHYS), 69 .length = L4_24XX_SIZE, 70 .type = MT_DEVICE 71 }, 72 }; 73 74 #ifdef CONFIG_ARCH_OMAP2420 75 static struct map_desc omap242x_io_desc[] __initdata = { 76 { 77 .virtual = DSP_MEM_2420_VIRT, 78 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 79 .length = DSP_MEM_2420_SIZE, 80 .type = MT_DEVICE 81 }, 82 { 83 .virtual = DSP_IPI_2420_VIRT, 84 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 85 .length = DSP_IPI_2420_SIZE, 86 .type = MT_DEVICE 87 }, 88 { 89 .virtual = DSP_MMU_2420_VIRT, 90 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 91 .length = DSP_MMU_2420_SIZE, 92 .type = MT_DEVICE 93 }, 94 }; 95 96 #endif 97 98 #ifdef CONFIG_ARCH_OMAP2430 99 static struct map_desc omap243x_io_desc[] __initdata = { 100 { 101 .virtual = L4_WK_243X_VIRT, 102 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 103 .length = L4_WK_243X_SIZE, 104 .type = MT_DEVICE 105 }, 106 { 107 .virtual = OMAP243X_GPMC_VIRT, 108 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 109 .length = OMAP243X_GPMC_SIZE, 110 .type = MT_DEVICE 111 }, 112 { 113 .virtual = OMAP243X_SDRC_VIRT, 114 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 115 .length = OMAP243X_SDRC_SIZE, 116 .type = MT_DEVICE 117 }, 118 { 119 .virtual = OMAP243X_SMS_VIRT, 120 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 121 .length = OMAP243X_SMS_SIZE, 122 .type = MT_DEVICE 123 }, 124 }; 125 #endif 126 #endif 127 128 #ifdef CONFIG_ARCH_OMAP34XX 129 static struct map_desc omap34xx_io_desc[] __initdata = { 130 { 131 .virtual = L3_34XX_VIRT, 132 .pfn = __phys_to_pfn(L3_34XX_PHYS), 133 .length = L3_34XX_SIZE, 134 .type = MT_DEVICE 135 }, 136 { 137 .virtual = L4_34XX_VIRT, 138 .pfn = __phys_to_pfn(L4_34XX_PHYS), 139 .length = L4_34XX_SIZE, 140 .type = MT_DEVICE 141 }, 142 { 143 .virtual = L4_WK_34XX_VIRT, 144 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS), 145 .length = L4_WK_34XX_SIZE, 146 .type = MT_DEVICE 147 }, 148 { 149 .virtual = OMAP34XX_GPMC_VIRT, 150 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 151 .length = OMAP34XX_GPMC_SIZE, 152 .type = MT_DEVICE 153 }, 154 { 155 .virtual = OMAP343X_SMS_VIRT, 156 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 157 .length = OMAP343X_SMS_SIZE, 158 .type = MT_DEVICE 159 }, 160 { 161 .virtual = OMAP343X_SDRC_VIRT, 162 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 163 .length = OMAP343X_SDRC_SIZE, 164 .type = MT_DEVICE 165 }, 166 { 167 .virtual = L4_PER_34XX_VIRT, 168 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 169 .length = L4_PER_34XX_SIZE, 170 .type = MT_DEVICE 171 }, 172 { 173 .virtual = L4_EMU_34XX_VIRT, 174 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 175 .length = L4_EMU_34XX_SIZE, 176 .type = MT_DEVICE 177 }, 178 }; 179 #endif 180 #ifdef CONFIG_ARCH_OMAP4 181 static struct map_desc omap44xx_io_desc[] __initdata = { 182 { 183 .virtual = L3_44XX_VIRT, 184 .pfn = __phys_to_pfn(L3_44XX_PHYS), 185 .length = L3_44XX_SIZE, 186 .type = MT_DEVICE, 187 }, 188 { 189 .virtual = L4_44XX_VIRT, 190 .pfn = __phys_to_pfn(L4_44XX_PHYS), 191 .length = L4_44XX_SIZE, 192 .type = MT_DEVICE, 193 }, 194 { 195 .virtual = L4_WK_44XX_VIRT, 196 .pfn = __phys_to_pfn(L4_WK_44XX_PHYS), 197 .length = L4_WK_44XX_SIZE, 198 .type = MT_DEVICE, 199 }, 200 { 201 .virtual = OMAP44XX_GPMC_VIRT, 202 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), 203 .length = OMAP44XX_GPMC_SIZE, 204 .type = MT_DEVICE, 205 }, 206 { 207 .virtual = OMAP44XX_EMIF1_VIRT, 208 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), 209 .length = OMAP44XX_EMIF1_SIZE, 210 .type = MT_DEVICE, 211 }, 212 { 213 .virtual = OMAP44XX_EMIF2_VIRT, 214 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), 215 .length = OMAP44XX_EMIF2_SIZE, 216 .type = MT_DEVICE, 217 }, 218 { 219 .virtual = OMAP44XX_DMM_VIRT, 220 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), 221 .length = OMAP44XX_DMM_SIZE, 222 .type = MT_DEVICE, 223 }, 224 { 225 .virtual = L4_PER_44XX_VIRT, 226 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 227 .length = L4_PER_44XX_SIZE, 228 .type = MT_DEVICE, 229 }, 230 { 231 .virtual = L4_EMU_44XX_VIRT, 232 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), 233 .length = L4_EMU_44XX_SIZE, 234 .type = MT_DEVICE, 235 }, 236 }; 237 #endif 238 239 static void __init _omap2_map_common_io(void) 240 { 241 /* Normally devicemaps_init() would flush caches and tlb after 242 * mdesc->map_io(), but we must also do it here because of the CPU 243 * revision check below. 244 */ 245 local_flush_tlb_all(); 246 flush_cache_all(); 247 248 omap2_check_revision(); 249 omap_sram_init(); 250 omapfb_reserve_sdram(); 251 omap_vram_reserve_sdram(); 252 } 253 254 #ifdef CONFIG_ARCH_OMAP2420 255 void __init omap242x_map_common_io() 256 { 257 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 258 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 259 _omap2_map_common_io(); 260 } 261 #endif 262 263 #ifdef CONFIG_ARCH_OMAP2430 264 void __init omap243x_map_common_io() 265 { 266 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 267 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 268 _omap2_map_common_io(); 269 } 270 #endif 271 272 #ifdef CONFIG_ARCH_OMAP34XX 273 void __init omap34xx_map_common_io() 274 { 275 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 276 _omap2_map_common_io(); 277 } 278 #endif 279 280 #ifdef CONFIG_ARCH_OMAP4 281 void __init omap44xx_map_common_io() 282 { 283 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 284 _omap2_map_common_io(); 285 } 286 #endif 287 288 /* 289 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 290 * 291 * Sets the CORE DPLL3 M2 divider to the same value that it's at 292 * currently. This has the effect of setting the SDRC SDRAM AC timing 293 * registers to the values currently defined by the kernel. Currently 294 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 295 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 296 * or passes along the return value of clk_set_rate(). 297 */ 298 static int __init _omap2_init_reprogram_sdrc(void) 299 { 300 struct clk *dpll3_m2_ck; 301 int v = -EINVAL; 302 long rate; 303 304 if (!cpu_is_omap34xx()) 305 return 0; 306 307 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 308 if (!dpll3_m2_ck) 309 return -EINVAL; 310 311 rate = clk_get_rate(dpll3_m2_ck); 312 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 313 v = clk_set_rate(dpll3_m2_ck, rate); 314 if (v) 315 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 316 317 clk_put(dpll3_m2_ck); 318 319 return v; 320 } 321 322 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, 323 struct omap_sdrc_params *sdrc_cs1) 324 { 325 struct omap_hwmod **hwmods = NULL; 326 327 if (cpu_is_omap2420()) 328 hwmods = omap2420_hwmods; 329 else if (cpu_is_omap2430()) 330 hwmods = omap2430_hwmods; 331 else if (cpu_is_omap34xx()) 332 hwmods = omap34xx_hwmods; 333 334 pwrdm_init(powerdomains_omap); 335 clkdm_init(clockdomains_omap, clkdm_autodeps); 336 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ 337 /* The OPP tables have to be registered before a clk init */ 338 omap_hwmod_init(hwmods); 339 omap2_mux_init(); 340 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); 341 #endif 342 343 if (cpu_is_omap24xx()) 344 omap2xxx_clk_init(); 345 else if (cpu_is_omap34xx()) 346 omap3xxx_clk_init(); 347 else if (cpu_is_omap44xx()) 348 omap4xxx_clk_init(); 349 else 350 pr_err("Could not init clock framework - unknown CPU\n"); 351 352 omap_serial_early_init(); 353 #ifndef CONFIG_ARCH_OMAP4 354 omap_hwmod_late_init(); 355 omap_pm_if_init(); 356 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 357 _omap2_init_reprogram_sdrc(); 358 #endif 359 gpmc_init(); 360 } 361