1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-omap2/id.c 4 * 5 * OMAP2 CPU identification code 6 * 7 * Copyright (C) 2005 Nokia Corporation 8 * Written by Tony Lindgren <tony@atomide.com> 9 * 10 * Copyright (C) 2009-11 Texas Instruments 11 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/random.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 22 #ifdef CONFIG_SOC_BUS 23 #include <linux/sys_soc.h> 24 #endif 25 26 #include <asm/cputype.h> 27 28 #include "common.h" 29 30 #include "id.h" 31 32 #include "soc.h" 33 #include "control.h" 34 35 #define OMAP4_SILICON_TYPE_STANDARD 0x01 36 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 37 38 #define OMAP_SOC_MAX_NAME_LENGTH 16 39 40 static unsigned int omap_revision; 41 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; 42 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; 43 u32 omap_features; 44 45 unsigned int omap_rev(void) 46 { 47 return omap_revision; 48 } 49 EXPORT_SYMBOL(omap_rev); 50 51 int omap_type(void) 52 { 53 static u32 val = OMAP2_DEVICETYPE_MASK; 54 55 if (val < OMAP2_DEVICETYPE_MASK) 56 return val; 57 58 if (soc_is_omap24xx()) { 59 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 60 } else if (soc_is_ti81xx()) { 61 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); 62 } else if (soc_is_am33xx() || soc_is_am43xx()) { 63 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 64 } else if (soc_is_omap34xx()) { 65 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 66 } else if (soc_is_omap44xx()) { 67 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 68 } else if (soc_is_omap54xx() || soc_is_dra7xx()) { 69 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); 70 val &= OMAP5_DEVICETYPE_MASK; 71 val >>= 6; 72 goto out; 73 } else { 74 pr_err("Cannot detect omap type!\n"); 75 goto out; 76 } 77 78 val &= OMAP2_DEVICETYPE_MASK; 79 val >>= 8; 80 81 out: 82 return val; 83 } 84 EXPORT_SYMBOL(omap_type); 85 86 87 /*----------------------------------------------------------------------------*/ 88 89 #define OMAP_TAP_IDCODE 0x0204 90 #define OMAP_TAP_DIE_ID_0 0x0218 91 #define OMAP_TAP_DIE_ID_1 0x021C 92 #define OMAP_TAP_DIE_ID_2 0x0220 93 #define OMAP_TAP_DIE_ID_3 0x0224 94 95 #define OMAP_TAP_DIE_ID_44XX_0 0x0200 96 #define OMAP_TAP_DIE_ID_44XX_1 0x0208 97 #define OMAP_TAP_DIE_ID_44XX_2 0x020c 98 #define OMAP_TAP_DIE_ID_44XX_3 0x0210 99 100 #define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) 101 102 struct omap_id { 103 u16 hawkeye; /* Silicon type (Hawkeye id) */ 104 u8 dev; /* Device type from production_id reg */ 105 u32 type; /* Combined type id copied to omap_revision */ 106 }; 107 108 /* Register values to detect the OMAP version */ 109 static struct omap_id omap_ids[] __initdata = { 110 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 111 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 112 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 113 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 114 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 115 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 116 }; 117 118 static void __iomem *tap_base; 119 static u16 tap_prod_id; 120 121 static void omap_get_die_id(struct omap_die_id *odi) 122 { 123 if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { 124 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 125 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 126 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 127 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); 128 129 return; 130 } 131 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 132 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 133 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 134 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 135 } 136 137 static int __init omap_feed_randpool(void) 138 { 139 struct omap_die_id odi; 140 141 /* Throw the die ID into the entropy pool at boot */ 142 omap_get_die_id(&odi); 143 add_device_randomness(&odi, sizeof(odi)); 144 return 0; 145 } 146 omap_device_initcall(omap_feed_randpool); 147 148 void __init omap2xxx_check_revision(void) 149 { 150 int i, j; 151 u32 idcode, prod_id; 152 u16 hawkeye; 153 u8 dev_type, rev; 154 struct omap_die_id odi; 155 156 idcode = read_tap_reg(OMAP_TAP_IDCODE); 157 prod_id = read_tap_reg(tap_prod_id); 158 hawkeye = (idcode >> 12) & 0xffff; 159 rev = (idcode >> 28) & 0x0f; 160 dev_type = (prod_id >> 16) & 0x0f; 161 omap_get_die_id(&odi); 162 163 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 164 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 165 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 166 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 167 odi.id_1, (odi.id_1 >> 28) & 0xf); 168 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 169 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 170 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 171 prod_id, dev_type); 172 173 /* Check hawkeye ids */ 174 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 175 if (hawkeye == omap_ids[i].hawkeye) 176 break; 177 } 178 179 if (i == ARRAY_SIZE(omap_ids)) { 180 printk(KERN_ERR "Unknown OMAP CPU id\n"); 181 return; 182 } 183 184 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 185 if (dev_type == omap_ids[j].dev) 186 break; 187 } 188 189 if (j == ARRAY_SIZE(omap_ids)) { 190 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", 191 omap_ids[i].type >> 16); 192 j = i; 193 } 194 195 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 196 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); 197 198 pr_info("%s", soc_name); 199 if ((omap_rev() >> 8) & 0x0f) 200 pr_cont("%s", soc_rev); 201 pr_cont("\n"); 202 } 203 204 #define OMAP3_SHOW_FEATURE(feat) \ 205 if (omap3_has_ ##feat()) \ 206 n += scnprintf(buf + n, sizeof(buf) - n, #feat " "); 207 208 static void __init omap3_cpuinfo(void) 209 { 210 const char *cpu_name; 211 char buf[64]; 212 int n = 0; 213 214 memset(buf, 0, sizeof(buf)); 215 216 /* 217 * OMAP3430 and OMAP3530 are assumed to be same. 218 * 219 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 220 * on available features. Upon detection, update the CPU id 221 * and CPU class bits. 222 */ 223 if (soc_is_omap3630()) { 224 if (omap3_has_iva() && omap3_has_sgx()) { 225 cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621"; 226 } else if (omap3_has_iva()) { 227 cpu_name = "DM3725"; 228 } else if (omap3_has_sgx()) { 229 cpu_name = "OMAP3615/AM3715"; 230 } else { 231 cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611"; 232 } 233 } else if (soc_is_am35xx()) { 234 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 235 } else if (soc_is_ti816x()) { 236 cpu_name = "TI816X"; 237 } else if (soc_is_am335x()) { 238 cpu_name = "AM335X"; 239 } else if (soc_is_am437x()) { 240 cpu_name = "AM437x"; 241 } else if (soc_is_ti814x()) { 242 cpu_name = "TI814X"; 243 } else if (omap3_has_iva() && omap3_has_sgx()) { 244 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 245 cpu_name = "OMAP3430/3530"; 246 } else if (omap3_has_iva()) { 247 cpu_name = "OMAP3525"; 248 } else if (omap3_has_sgx()) { 249 cpu_name = "OMAP3515"; 250 } else { 251 cpu_name = "OMAP3503"; 252 } 253 254 strscpy(soc_name, cpu_name); 255 256 /* Print verbose information */ 257 n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev); 258 259 OMAP3_SHOW_FEATURE(l2cache); 260 OMAP3_SHOW_FEATURE(iva); 261 OMAP3_SHOW_FEATURE(sgx); 262 OMAP3_SHOW_FEATURE(neon); 263 OMAP3_SHOW_FEATURE(isp); 264 OMAP3_SHOW_FEATURE(192mhz_clk); 265 if (*(buf + n - 1) == ' ') 266 n--; 267 n += scnprintf(buf + n, sizeof(buf) - n, ")\n"); 268 pr_info("%s", buf); 269 } 270 271 #define OMAP3_CHECK_FEATURE(status,feat) \ 272 if (((status & OMAP3_ ##feat## _MASK) \ 273 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 274 omap_features |= OMAP3_HAS_ ##feat; \ 275 } 276 277 void __init omap3xxx_check_features(void) 278 { 279 u32 status; 280 281 omap_features = 0; 282 283 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 284 285 OMAP3_CHECK_FEATURE(status, L2CACHE); 286 OMAP3_CHECK_FEATURE(status, IVA); 287 OMAP3_CHECK_FEATURE(status, SGX); 288 OMAP3_CHECK_FEATURE(status, NEON); 289 OMAP3_CHECK_FEATURE(status, ISP); 290 if (soc_is_omap3630()) 291 omap_features |= OMAP3_HAS_192MHZ_CLK; 292 if (soc_is_omap3430() || soc_is_omap3630()) 293 omap_features |= OMAP3_HAS_IO_WAKEUP; 294 if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || 295 omap_rev() == OMAP3430_REV_ES3_1_2) 296 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; 297 298 omap_features |= OMAP3_HAS_SDRC; 299 300 /* 301 * am35x fixups: 302 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as 303 * reserved and therefore return 0 when read. Unfortunately, 304 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to 305 * mean that a feature is present even though it isn't so clear 306 * the incorrectly set feature bits. 307 */ 308 if (soc_is_am35xx()) 309 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); 310 311 /* 312 * TODO: Get additional info (where applicable) 313 * e.g. Size of L2 cache. 314 */ 315 316 omap3_cpuinfo(); 317 } 318 319 void __init omap4xxx_check_features(void) 320 { 321 u32 si_type; 322 323 si_type = 324 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; 325 326 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) 327 omap_features = OMAP4_HAS_PERF_SILICON; 328 } 329 330 void __init ti81xx_check_features(void) 331 { 332 omap_features = OMAP3_HAS_NEON; 333 omap3_cpuinfo(); 334 } 335 336 void __init am33xx_check_features(void) 337 { 338 u32 status; 339 340 omap_features = OMAP3_HAS_NEON; 341 342 status = omap_ctrl_readl(AM33XX_DEV_FEATURE); 343 if (status & AM33XX_SGX_MASK) 344 omap_features |= OMAP3_HAS_SGX; 345 346 omap3_cpuinfo(); 347 } 348 349 void __init omap3xxx_check_revision(void) 350 { 351 const char *cpu_rev; 352 u32 cpuid, idcode; 353 u16 hawkeye; 354 u8 rev; 355 356 /* 357 * We cannot access revision registers on ES1.0. 358 * If the processor type is Cortex-A8 and the revision is 0x0 359 * it means its Cortex r0p0 which is 3430 ES1.0. 360 */ 361 cpuid = read_cpuid_id(); 362 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 363 omap_revision = OMAP3430_REV_ES1_0; 364 cpu_rev = "1.0"; 365 return; 366 } 367 368 /* 369 * Detection for 34xx ES2.0 and above can be done with just 370 * hawkeye and rev. See TRM 1.5.2 Device Identification. 371 * Note that rev does not map directly to our defined processor 372 * revision numbers as ES1.0 uses value 0. 373 */ 374 idcode = read_tap_reg(OMAP_TAP_IDCODE); 375 hawkeye = (idcode >> 12) & 0xffff; 376 rev = (idcode >> 28) & 0xff; 377 378 switch (hawkeye) { 379 case 0xb7ae: 380 /* Handle 34xx/35xx devices */ 381 switch (rev) { 382 case 0: /* Take care of early samples */ 383 case 1: 384 omap_revision = OMAP3430_REV_ES2_0; 385 cpu_rev = "2.0"; 386 break; 387 case 2: 388 omap_revision = OMAP3430_REV_ES2_1; 389 cpu_rev = "2.1"; 390 break; 391 case 3: 392 omap_revision = OMAP3430_REV_ES3_0; 393 cpu_rev = "3.0"; 394 break; 395 case 4: 396 omap_revision = OMAP3430_REV_ES3_1; 397 cpu_rev = "3.1"; 398 break; 399 case 7: 400 default: 401 /* Use the latest known revision as default */ 402 omap_revision = OMAP3430_REV_ES3_1_2; 403 cpu_rev = "3.1.2"; 404 } 405 break; 406 case 0xb868: 407 /* 408 * Handle OMAP/AM 3505/3517 devices 409 * 410 * Set the device to be OMAP3517 here. Actual device 411 * is identified later based on the features. 412 */ 413 switch (rev) { 414 case 0: 415 omap_revision = AM35XX_REV_ES1_0; 416 cpu_rev = "1.0"; 417 break; 418 case 1: 419 default: 420 omap_revision = AM35XX_REV_ES1_1; 421 cpu_rev = "1.1"; 422 } 423 break; 424 case 0xb891: 425 /* Handle 36xx devices */ 426 427 switch(rev) { 428 case 0: /* Take care of early samples */ 429 omap_revision = OMAP3630_REV_ES1_0; 430 cpu_rev = "1.0"; 431 break; 432 case 1: 433 omap_revision = OMAP3630_REV_ES1_1; 434 cpu_rev = "1.1"; 435 break; 436 case 2: 437 default: 438 omap_revision = OMAP3630_REV_ES1_2; 439 cpu_rev = "1.2"; 440 } 441 break; 442 case 0xb81e: 443 switch (rev) { 444 case 0: 445 omap_revision = TI8168_REV_ES1_0; 446 cpu_rev = "1.0"; 447 break; 448 case 1: 449 omap_revision = TI8168_REV_ES1_1; 450 cpu_rev = "1.1"; 451 break; 452 case 2: 453 omap_revision = TI8168_REV_ES2_0; 454 cpu_rev = "2.0"; 455 break; 456 case 3: 457 default: 458 omap_revision = TI8168_REV_ES2_1; 459 cpu_rev = "2.1"; 460 } 461 break; 462 case 0xb944: 463 switch (rev) { 464 case 0: 465 omap_revision = AM335X_REV_ES1_0; 466 cpu_rev = "1.0"; 467 break; 468 case 1: 469 omap_revision = AM335X_REV_ES2_0; 470 cpu_rev = "2.0"; 471 break; 472 case 2: 473 default: 474 omap_revision = AM335X_REV_ES2_1; 475 cpu_rev = "2.1"; 476 break; 477 } 478 break; 479 case 0xb98c: 480 switch (rev) { 481 case 0: 482 omap_revision = AM437X_REV_ES1_0; 483 cpu_rev = "1.0"; 484 break; 485 case 1: 486 omap_revision = AM437X_REV_ES1_1; 487 cpu_rev = "1.1"; 488 break; 489 case 2: 490 default: 491 omap_revision = AM437X_REV_ES1_2; 492 cpu_rev = "1.2"; 493 break; 494 } 495 break; 496 case 0xb8f2: 497 case 0xb968: 498 switch (rev) { 499 case 0: 500 case 1: 501 omap_revision = TI8148_REV_ES1_0; 502 cpu_rev = "1.0"; 503 break; 504 case 2: 505 omap_revision = TI8148_REV_ES2_0; 506 cpu_rev = "2.0"; 507 break; 508 case 3: 509 default: 510 omap_revision = TI8148_REV_ES2_1; 511 cpu_rev = "2.1"; 512 break; 513 } 514 break; 515 default: 516 /* Unknown default to latest silicon rev as default */ 517 omap_revision = OMAP3630_REV_ES1_2; 518 cpu_rev = "1.2"; 519 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n", 520 hawkeye); 521 } 522 sprintf(soc_rev, "ES%s", cpu_rev); 523 } 524 525 void __init omap4xxx_check_revision(void) 526 { 527 u32 idcode; 528 u16 hawkeye; 529 u8 rev; 530 531 /* 532 * The IC rev detection is done with hawkeye and rev. 533 * Note that rev does not map directly to defined processor 534 * revision numbers as ES1.0 uses value 0. 535 */ 536 idcode = read_tap_reg(OMAP_TAP_IDCODE); 537 hawkeye = (idcode >> 12) & 0xffff; 538 rev = (idcode >> 28) & 0xf; 539 540 /* 541 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 542 * Use ARM register to detect the correct ES version 543 */ 544 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { 545 idcode = read_cpuid_id(); 546 rev = (idcode & 0xf) - 1; 547 } 548 549 switch (hawkeye) { 550 case 0xb852: 551 switch (rev) { 552 case 0: 553 omap_revision = OMAP4430_REV_ES1_0; 554 break; 555 case 1: 556 default: 557 omap_revision = OMAP4430_REV_ES2_0; 558 } 559 break; 560 case 0xb95c: 561 switch (rev) { 562 case 3: 563 omap_revision = OMAP4430_REV_ES2_1; 564 break; 565 case 4: 566 omap_revision = OMAP4430_REV_ES2_2; 567 break; 568 case 6: 569 default: 570 omap_revision = OMAP4430_REV_ES2_3; 571 } 572 break; 573 case 0xb94e: 574 switch (rev) { 575 case 0: 576 omap_revision = OMAP4460_REV_ES1_0; 577 break; 578 case 2: 579 default: 580 omap_revision = OMAP4460_REV_ES1_1; 581 break; 582 } 583 break; 584 case 0xb975: 585 switch (rev) { 586 case 0: 587 default: 588 omap_revision = OMAP4470_REV_ES1_0; 589 break; 590 } 591 break; 592 default: 593 /* Unknown default to latest silicon rev as default */ 594 omap_revision = OMAP4430_REV_ES2_3; 595 } 596 597 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 598 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 599 (omap_rev() >> 8) & 0xf); 600 pr_info("%s %s\n", soc_name, soc_rev); 601 } 602 603 void __init omap5xxx_check_revision(void) 604 { 605 u32 idcode; 606 u16 hawkeye; 607 u8 rev; 608 609 idcode = read_tap_reg(OMAP_TAP_IDCODE); 610 hawkeye = (idcode >> 12) & 0xffff; 611 rev = (idcode >> 28) & 0xff; 612 switch (hawkeye) { 613 case 0xb942: 614 switch (rev) { 615 case 0: 616 /* No support for ES1.0 Test chip */ 617 BUG(); 618 case 1: 619 default: 620 omap_revision = OMAP5430_REV_ES2_0; 621 } 622 break; 623 624 case 0xb998: 625 switch (rev) { 626 case 0: 627 /* No support for ES1.0 Test chip */ 628 BUG(); 629 case 1: 630 default: 631 omap_revision = OMAP5432_REV_ES2_0; 632 } 633 break; 634 635 default: 636 /* Unknown default to latest silicon rev as default*/ 637 omap_revision = OMAP5430_REV_ES2_0; 638 } 639 640 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 641 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); 642 643 pr_info("%s %s\n", soc_name, soc_rev); 644 } 645 646 void __init dra7xxx_check_revision(void) 647 { 648 u32 idcode; 649 u16 hawkeye; 650 u8 rev, package; 651 struct omap_die_id odi; 652 653 omap_get_die_id(&odi); 654 package = (odi.id_2 >> 16) & 0x3; 655 idcode = read_tap_reg(OMAP_TAP_IDCODE); 656 hawkeye = (idcode >> 12) & 0xffff; 657 rev = (idcode >> 28) & 0xff; 658 switch (hawkeye) { 659 case 0xbb50: 660 switch (rev) { 661 case 0: 662 default: 663 switch (package) { 664 case 0x2: 665 omap_revision = DRA762_ABZ_REV_ES1_0; 666 break; 667 case 0x3: 668 omap_revision = DRA762_ACD_REV_ES1_0; 669 break; 670 default: 671 omap_revision = DRA762_REV_ES1_0; 672 break; 673 } 674 break; 675 } 676 break; 677 678 case 0xb990: 679 switch (rev) { 680 case 0: 681 omap_revision = DRA752_REV_ES1_0; 682 break; 683 case 1: 684 omap_revision = DRA752_REV_ES1_1; 685 break; 686 case 2: 687 default: 688 omap_revision = DRA752_REV_ES2_0; 689 break; 690 } 691 break; 692 693 case 0xb9bc: 694 switch (rev) { 695 case 0: 696 omap_revision = DRA722_REV_ES1_0; 697 break; 698 case 1: 699 omap_revision = DRA722_REV_ES2_0; 700 break; 701 case 2: 702 default: 703 omap_revision = DRA722_REV_ES2_1; 704 break; 705 } 706 break; 707 708 default: 709 /* Unknown default to latest silicon rev as default*/ 710 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", 711 __func__, idcode, hawkeye, rev); 712 omap_revision = DRA752_REV_ES2_0; 713 } 714 715 sprintf(soc_name, "DRA%03x", omap_rev() >> 16); 716 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 717 (omap_rev() >> 8) & 0xf); 718 719 pr_info("%s %s\n", soc_name, soc_rev); 720 } 721 722 /* 723 * Set up things for map_io and processor detection later on. Gets called 724 * pretty much first thing from board init. For multi-omap, this gets 725 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 726 * detect the exact revision later on in omap2_detect_revision() once map_io 727 * is done. 728 */ 729 void __init omap2_set_globals_tap(u32 class, void __iomem *tap) 730 { 731 omap_revision = class; 732 tap_base = tap; 733 734 /* XXX What is this intended to do? */ 735 if (soc_is_omap34xx()) 736 tap_prod_id = 0x0210; 737 else 738 tap_prod_id = 0x0208; 739 } 740 741 #ifdef CONFIG_SOC_BUS 742 743 static const char * const omap_types[] = { 744 [OMAP2_DEVICE_TYPE_TEST] = "TST", 745 [OMAP2_DEVICE_TYPE_EMU] = "EMU", 746 [OMAP2_DEVICE_TYPE_SEC] = "HS", 747 [OMAP2_DEVICE_TYPE_GP] = "GP", 748 [OMAP2_DEVICE_TYPE_BAD] = "BAD", 749 }; 750 751 static const char * __init omap_get_family(void) 752 { 753 if (soc_is_omap24xx()) 754 return kasprintf(GFP_KERNEL, "OMAP2"); 755 else if (soc_is_omap34xx()) 756 return kasprintf(GFP_KERNEL, "OMAP3"); 757 else if (soc_is_omap44xx()) 758 return kasprintf(GFP_KERNEL, "OMAP4"); 759 else if (soc_is_omap54xx()) 760 return kasprintf(GFP_KERNEL, "OMAP5"); 761 else if (soc_is_am33xx() || soc_is_am335x()) 762 return kasprintf(GFP_KERNEL, "AM33xx"); 763 else if (soc_is_am43xx()) 764 return kasprintf(GFP_KERNEL, "AM43xx"); 765 else if (soc_is_dra7xx()) 766 return kasprintf(GFP_KERNEL, "DRA7"); 767 else 768 return kasprintf(GFP_KERNEL, "Unknown"); 769 } 770 771 static ssize_t 772 type_show(struct device *dev, struct device_attribute *attr, char *buf) 773 { 774 return sprintf(buf, "%s\n", omap_types[omap_type()]); 775 } 776 777 static DEVICE_ATTR_RO(type); 778 779 static struct attribute *omap_soc_attrs[] = { 780 &dev_attr_type.attr, 781 NULL 782 }; 783 784 ATTRIBUTE_GROUPS(omap_soc); 785 786 void __init omap_soc_device_init(void) 787 { 788 struct soc_device *soc_dev; 789 struct soc_device_attribute *soc_dev_attr; 790 791 soc_dev_attr = kzalloc_obj(*soc_dev_attr); 792 if (!soc_dev_attr) 793 return; 794 795 soc_dev_attr->machine = soc_name; 796 soc_dev_attr->family = omap_get_family(); 797 if (!soc_dev_attr->family) { 798 kfree(soc_dev_attr); 799 return; 800 } 801 soc_dev_attr->revision = soc_rev; 802 soc_dev_attr->custom_attr_group = omap_soc_groups[0]; 803 804 soc_dev = soc_device_register(soc_dev_attr); 805 if (IS_ERR(soc_dev)) { 806 kfree(soc_dev_attr->family); 807 kfree(soc_dev_attr); 808 return; 809 } 810 } 811 #endif /* CONFIG_SOC_BUS */ 812