1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009-11 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <asm/cputype.h> 23 24 #include "common.h" 25 26 #include "id.h" 27 28 #include "soc.h" 29 #include "control.h" 30 31 #define OMAP4_SILICON_TYPE_STANDARD 0x01 32 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 33 34 #define OMAP_SOC_MAX_NAME_LENGTH 16 35 36 static unsigned int omap_revision; 37 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; 38 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; 39 u32 omap_features; 40 41 unsigned int omap_rev(void) 42 { 43 return omap_revision; 44 } 45 EXPORT_SYMBOL(omap_rev); 46 47 int omap_type(void) 48 { 49 u32 val = 0; 50 51 if (cpu_is_omap24xx()) { 52 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 53 } else if (soc_is_am33xx()) { 54 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 55 } else if (cpu_is_omap34xx()) { 56 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 57 } else if (cpu_is_omap44xx()) { 58 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 59 } else if (soc_is_omap54xx()) { 60 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); 61 val &= OMAP5_DEVICETYPE_MASK; 62 val >>= 6; 63 goto out; 64 } else { 65 pr_err("Cannot detect omap type!\n"); 66 goto out; 67 } 68 69 val &= OMAP2_DEVICETYPE_MASK; 70 val >>= 8; 71 72 out: 73 return val; 74 } 75 EXPORT_SYMBOL(omap_type); 76 77 78 /*----------------------------------------------------------------------------*/ 79 80 #define OMAP_TAP_IDCODE 0x0204 81 #define OMAP_TAP_DIE_ID_0 0x0218 82 #define OMAP_TAP_DIE_ID_1 0x021C 83 #define OMAP_TAP_DIE_ID_2 0x0220 84 #define OMAP_TAP_DIE_ID_3 0x0224 85 86 #define OMAP_TAP_DIE_ID_44XX_0 0x0200 87 #define OMAP_TAP_DIE_ID_44XX_1 0x0208 88 #define OMAP_TAP_DIE_ID_44XX_2 0x020c 89 #define OMAP_TAP_DIE_ID_44XX_3 0x0210 90 91 #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) 92 93 struct omap_id { 94 u16 hawkeye; /* Silicon type (Hawkeye id) */ 95 u8 dev; /* Device type from production_id reg */ 96 u32 type; /* Combined type id copied to omap_revision */ 97 }; 98 99 /* Register values to detect the OMAP version */ 100 static struct omap_id omap_ids[] __initdata = { 101 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 102 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 103 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 104 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 105 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 106 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 107 }; 108 109 static void __iomem *tap_base; 110 static u16 tap_prod_id; 111 112 void omap_get_die_id(struct omap_die_id *odi) 113 { 114 if (cpu_is_omap44xx() || soc_is_omap54xx()) { 115 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 116 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 117 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 118 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); 119 120 return; 121 } 122 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 123 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 124 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 125 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 126 } 127 128 void __init omap2xxx_check_revision(void) 129 { 130 int i, j; 131 u32 idcode, prod_id; 132 u16 hawkeye; 133 u8 dev_type, rev; 134 struct omap_die_id odi; 135 136 idcode = read_tap_reg(OMAP_TAP_IDCODE); 137 prod_id = read_tap_reg(tap_prod_id); 138 hawkeye = (idcode >> 12) & 0xffff; 139 rev = (idcode >> 28) & 0x0f; 140 dev_type = (prod_id >> 16) & 0x0f; 141 omap_get_die_id(&odi); 142 143 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 144 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 145 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 146 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 147 odi.id_1, (odi.id_1 >> 28) & 0xf); 148 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 149 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 150 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 151 prod_id, dev_type); 152 153 /* Check hawkeye ids */ 154 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 155 if (hawkeye == omap_ids[i].hawkeye) 156 break; 157 } 158 159 if (i == ARRAY_SIZE(omap_ids)) { 160 printk(KERN_ERR "Unknown OMAP CPU id\n"); 161 return; 162 } 163 164 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 165 if (dev_type == omap_ids[j].dev) 166 break; 167 } 168 169 if (j == ARRAY_SIZE(omap_ids)) { 170 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", 171 omap_ids[i].type >> 16); 172 j = i; 173 } 174 175 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 176 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); 177 178 pr_info("%s", soc_name); 179 if ((omap_rev() >> 8) & 0x0f) 180 pr_info("%s", soc_rev); 181 pr_info("\n"); 182 } 183 184 #define OMAP3_SHOW_FEATURE(feat) \ 185 if (omap3_has_ ##feat()) \ 186 printk(#feat" "); 187 188 static void __init omap3_cpuinfo(void) 189 { 190 const char *cpu_name; 191 192 /* 193 * OMAP3430 and OMAP3530 are assumed to be same. 194 * 195 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 196 * on available features. Upon detection, update the CPU id 197 * and CPU class bits. 198 */ 199 if (cpu_is_omap3630()) { 200 cpu_name = "OMAP3630"; 201 } else if (soc_is_am35xx()) { 202 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 203 } else if (cpu_is_ti816x()) { 204 cpu_name = "TI816X"; 205 } else if (soc_is_am335x()) { 206 cpu_name = "AM335X"; 207 } else if (cpu_is_ti814x()) { 208 cpu_name = "TI814X"; 209 } else if (omap3_has_iva() && omap3_has_sgx()) { 210 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 211 cpu_name = "OMAP3430/3530"; 212 } else if (omap3_has_iva()) { 213 cpu_name = "OMAP3525"; 214 } else if (omap3_has_sgx()) { 215 cpu_name = "OMAP3515"; 216 } else { 217 cpu_name = "OMAP3503"; 218 } 219 220 sprintf(soc_name, "%s", cpu_name); 221 222 /* Print verbose information */ 223 pr_info("%s %s (", soc_name, soc_rev); 224 225 OMAP3_SHOW_FEATURE(l2cache); 226 OMAP3_SHOW_FEATURE(iva); 227 OMAP3_SHOW_FEATURE(sgx); 228 OMAP3_SHOW_FEATURE(neon); 229 OMAP3_SHOW_FEATURE(isp); 230 OMAP3_SHOW_FEATURE(192mhz_clk); 231 232 printk(")\n"); 233 } 234 235 #define OMAP3_CHECK_FEATURE(status,feat) \ 236 if (((status & OMAP3_ ##feat## _MASK) \ 237 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 238 omap_features |= OMAP3_HAS_ ##feat; \ 239 } 240 241 void __init omap3xxx_check_features(void) 242 { 243 u32 status; 244 245 omap_features = 0; 246 247 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 248 249 OMAP3_CHECK_FEATURE(status, L2CACHE); 250 OMAP3_CHECK_FEATURE(status, IVA); 251 OMAP3_CHECK_FEATURE(status, SGX); 252 OMAP3_CHECK_FEATURE(status, NEON); 253 OMAP3_CHECK_FEATURE(status, ISP); 254 if (cpu_is_omap3630()) 255 omap_features |= OMAP3_HAS_192MHZ_CLK; 256 if (cpu_is_omap3430() || cpu_is_omap3630()) 257 omap_features |= OMAP3_HAS_IO_WAKEUP; 258 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || 259 omap_rev() == OMAP3430_REV_ES3_1_2) 260 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; 261 262 omap_features |= OMAP3_HAS_SDRC; 263 264 /* 265 * am35x fixups: 266 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as 267 * reserved and therefore return 0 when read. Unfortunately, 268 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to 269 * mean that a feature is present even though it isn't so clear 270 * the incorrectly set feature bits. 271 */ 272 if (soc_is_am35xx()) 273 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); 274 275 /* 276 * TODO: Get additional info (where applicable) 277 * e.g. Size of L2 cache. 278 */ 279 280 omap3_cpuinfo(); 281 } 282 283 void __init omap4xxx_check_features(void) 284 { 285 u32 si_type; 286 287 si_type = 288 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; 289 290 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) 291 omap_features = OMAP4_HAS_PERF_SILICON; 292 } 293 294 void __init ti81xx_check_features(void) 295 { 296 omap_features = OMAP3_HAS_NEON; 297 omap3_cpuinfo(); 298 } 299 300 void __init omap3xxx_check_revision(void) 301 { 302 const char *cpu_rev; 303 u32 cpuid, idcode; 304 u16 hawkeye; 305 u8 rev; 306 307 /* 308 * We cannot access revision registers on ES1.0. 309 * If the processor type is Cortex-A8 and the revision is 0x0 310 * it means its Cortex r0p0 which is 3430 ES1.0. 311 */ 312 cpuid = read_cpuid(CPUID_ID); 313 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 314 omap_revision = OMAP3430_REV_ES1_0; 315 cpu_rev = "1.0"; 316 return; 317 } 318 319 /* 320 * Detection for 34xx ES2.0 and above can be done with just 321 * hawkeye and rev. See TRM 1.5.2 Device Identification. 322 * Note that rev does not map directly to our defined processor 323 * revision numbers as ES1.0 uses value 0. 324 */ 325 idcode = read_tap_reg(OMAP_TAP_IDCODE); 326 hawkeye = (idcode >> 12) & 0xffff; 327 rev = (idcode >> 28) & 0xff; 328 329 switch (hawkeye) { 330 case 0xb7ae: 331 /* Handle 34xx/35xx devices */ 332 switch (rev) { 333 case 0: /* Take care of early samples */ 334 case 1: 335 omap_revision = OMAP3430_REV_ES2_0; 336 cpu_rev = "2.0"; 337 break; 338 case 2: 339 omap_revision = OMAP3430_REV_ES2_1; 340 cpu_rev = "2.1"; 341 break; 342 case 3: 343 omap_revision = OMAP3430_REV_ES3_0; 344 cpu_rev = "3.0"; 345 break; 346 case 4: 347 omap_revision = OMAP3430_REV_ES3_1; 348 cpu_rev = "3.1"; 349 break; 350 case 7: 351 /* FALLTHROUGH */ 352 default: 353 /* Use the latest known revision as default */ 354 omap_revision = OMAP3430_REV_ES3_1_2; 355 cpu_rev = "3.1.2"; 356 } 357 break; 358 case 0xb868: 359 /* 360 * Handle OMAP/AM 3505/3517 devices 361 * 362 * Set the device to be OMAP3517 here. Actual device 363 * is identified later based on the features. 364 */ 365 switch (rev) { 366 case 0: 367 omap_revision = AM35XX_REV_ES1_0; 368 cpu_rev = "1.0"; 369 break; 370 case 1: 371 /* FALLTHROUGH */ 372 default: 373 omap_revision = AM35XX_REV_ES1_1; 374 cpu_rev = "1.1"; 375 } 376 break; 377 case 0xb891: 378 /* Handle 36xx devices */ 379 380 switch(rev) { 381 case 0: /* Take care of early samples */ 382 omap_revision = OMAP3630_REV_ES1_0; 383 cpu_rev = "1.0"; 384 break; 385 case 1: 386 omap_revision = OMAP3630_REV_ES1_1; 387 cpu_rev = "1.1"; 388 break; 389 case 2: 390 /* FALLTHROUGH */ 391 default: 392 omap_revision = OMAP3630_REV_ES1_2; 393 cpu_rev = "1.2"; 394 } 395 break; 396 case 0xb81e: 397 switch (rev) { 398 case 0: 399 omap_revision = TI8168_REV_ES1_0; 400 cpu_rev = "1.0"; 401 break; 402 case 1: 403 /* FALLTHROUGH */ 404 default: 405 omap_revision = TI8168_REV_ES1_1; 406 cpu_rev = "1.1"; 407 break; 408 } 409 break; 410 case 0xb944: 411 switch (rev) { 412 case 0: 413 omap_revision = AM335X_REV_ES1_0; 414 cpu_rev = "1.0"; 415 break; 416 case 1: 417 /* FALLTHROUGH */ 418 default: 419 omap_revision = AM335X_REV_ES2_0; 420 cpu_rev = "2.0"; 421 break; 422 } 423 break; 424 case 0xb8f2: 425 switch (rev) { 426 case 0: 427 /* FALLTHROUGH */ 428 case 1: 429 omap_revision = TI8148_REV_ES1_0; 430 cpu_rev = "1.0"; 431 break; 432 case 2: 433 omap_revision = TI8148_REV_ES2_0; 434 cpu_rev = "2.0"; 435 break; 436 case 3: 437 /* FALLTHROUGH */ 438 default: 439 omap_revision = TI8148_REV_ES2_1; 440 cpu_rev = "2.1"; 441 break; 442 } 443 break; 444 default: 445 /* Unknown default to latest silicon rev as default */ 446 omap_revision = OMAP3630_REV_ES1_2; 447 cpu_rev = "1.2"; 448 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); 449 } 450 sprintf(soc_rev, "ES%s", cpu_rev); 451 } 452 453 void __init omap4xxx_check_revision(void) 454 { 455 u32 idcode; 456 u16 hawkeye; 457 u8 rev; 458 459 /* 460 * The IC rev detection is done with hawkeye and rev. 461 * Note that rev does not map directly to defined processor 462 * revision numbers as ES1.0 uses value 0. 463 */ 464 idcode = read_tap_reg(OMAP_TAP_IDCODE); 465 hawkeye = (idcode >> 12) & 0xffff; 466 rev = (idcode >> 28) & 0xf; 467 468 /* 469 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 470 * Use ARM register to detect the correct ES version 471 */ 472 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { 473 idcode = read_cpuid(CPUID_ID); 474 rev = (idcode & 0xf) - 1; 475 } 476 477 switch (hawkeye) { 478 case 0xb852: 479 switch (rev) { 480 case 0: 481 omap_revision = OMAP4430_REV_ES1_0; 482 break; 483 case 1: 484 default: 485 omap_revision = OMAP4430_REV_ES2_0; 486 } 487 break; 488 case 0xb95c: 489 switch (rev) { 490 case 3: 491 omap_revision = OMAP4430_REV_ES2_1; 492 break; 493 case 4: 494 omap_revision = OMAP4430_REV_ES2_2; 495 break; 496 case 6: 497 default: 498 omap_revision = OMAP4430_REV_ES2_3; 499 } 500 break; 501 case 0xb94e: 502 switch (rev) { 503 case 0: 504 omap_revision = OMAP4460_REV_ES1_0; 505 break; 506 case 2: 507 default: 508 omap_revision = OMAP4460_REV_ES1_1; 509 break; 510 } 511 break; 512 case 0xb975: 513 switch (rev) { 514 case 0: 515 default: 516 omap_revision = OMAP4470_REV_ES1_0; 517 break; 518 } 519 break; 520 default: 521 /* Unknown default to latest silicon rev as default */ 522 omap_revision = OMAP4430_REV_ES2_3; 523 } 524 525 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 526 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 527 (omap_rev() >> 8) & 0xf); 528 pr_info("%s %s\n", soc_name, soc_rev); 529 } 530 531 void __init omap5xxx_check_revision(void) 532 { 533 u32 idcode; 534 u16 hawkeye; 535 u8 rev; 536 537 idcode = read_tap_reg(OMAP_TAP_IDCODE); 538 hawkeye = (idcode >> 12) & 0xffff; 539 rev = (idcode >> 28) & 0xff; 540 switch (hawkeye) { 541 case 0xb942: 542 switch (rev) { 543 case 0: 544 default: 545 omap_revision = OMAP5430_REV_ES1_0; 546 } 547 break; 548 549 case 0xb998: 550 switch (rev) { 551 case 0: 552 default: 553 omap_revision = OMAP5432_REV_ES1_0; 554 } 555 break; 556 557 default: 558 /* Unknown default to latest silicon rev as default*/ 559 omap_revision = OMAP5430_REV_ES1_0; 560 } 561 562 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 563 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); 564 565 pr_info("%s %s\n", soc_name, soc_rev); 566 } 567 568 /* 569 * Set up things for map_io and processor detection later on. Gets called 570 * pretty much first thing from board init. For multi-omap, this gets 571 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 572 * detect the exact revision later on in omap2_detect_revision() once map_io 573 * is done. 574 */ 575 void __init omap2_set_globals_tap(u32 class, void __iomem *tap) 576 { 577 omap_revision = class; 578 tap_base = tap; 579 580 /* XXX What is this intended to do? */ 581 if (cpu_is_omap34xx()) 582 tap_prod_id = 0x0210; 583 else 584 tap_prod_id = 0x0208; 585 } 586