1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 19 #include <asm/cputype.h> 20 21 #include <mach/common.h> 22 #include <mach/control.h> 23 #include <mach/cpu.h> 24 25 static u32 class; 26 static void __iomem *tap_base; 27 static u16 tap_prod_id; 28 29 #define OMAP_TAP_IDCODE 0x0204 30 #define OMAP_TAP_DIE_ID_0 0x0218 31 #define OMAP_TAP_DIE_ID_1 0x021C 32 #define OMAP_TAP_DIE_ID_2 0x0220 33 #define OMAP_TAP_DIE_ID_3 0x0224 34 35 /* system_rev fields for OMAP2 processors: 36 * CPU id bits [31:16], 37 * CPU device type [15:12], (unprg,normal,POP) 38 * CPU revision [11:08] 39 * CPU class bits [07:00] 40 */ 41 42 struct omap_id { 43 u16 hawkeye; /* Silicon type (Hawkeye id) */ 44 u8 dev; /* Device type from production_id reg */ 45 u32 type; /* combined type id copied to system_rev */ 46 }; 47 48 /* Register values to detect the OMAP version */ 49 static struct omap_id omap_ids[] __initdata = { 50 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 }, 51 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 }, 52 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 }, 53 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 }, 54 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 }, 55 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 }, 56 }; 57 58 static struct omap_chip_id omap_chip; 59 60 /** 61 * omap_chip_is - test whether currently running OMAP matches a chip type 62 * @oc: omap_chip_t to test against 63 * 64 * Test whether the currently-running OMAP chip matches the supplied 65 * chip type 'oc'. Returns 1 upon a match; 0 upon failure. 66 */ 67 int omap_chip_is(struct omap_chip_id oci) 68 { 69 return (oci.oc & omap_chip.oc) ? 1 : 0; 70 } 71 EXPORT_SYMBOL(omap_chip_is); 72 73 static u32 __init read_tap_reg(int reg) 74 { 75 unsigned int regval = 0; 76 u32 cpuid; 77 78 /* Reading the IDCODE register on 3430 ES1 results in a 79 * data abort as the register is not exposed on the OCP 80 * Hence reading the Cortex Rev 81 */ 82 cpuid = read_cpuid(CPUID_ID); 83 84 /* If the processor type is Cortex-A8 and the revision is 0x0 85 * it means its Cortex r0p0 which is 3430 ES1 86 */ 87 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { 88 89 if (reg == tap_prod_id) { 90 regval = 0x000F00F0; 91 goto out; 92 } 93 94 switch (reg) { 95 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; 96 /* Making DevType as 0xF in ES1 to differ from ES2 */ 97 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; 98 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; 99 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; 100 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; 101 } 102 } else 103 regval = __raw_readl(tap_base + reg); 104 105 out: 106 return regval; 107 108 } 109 110 /* 111 * _set_system_rev - set the system_rev global based on current OMAP chip type 112 * 113 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() 114 * macros. 115 */ 116 static void __init _set_system_rev(u32 type, u8 rev) 117 { 118 u32 i, ctrl_status; 119 120 /* 121 * system_rev encoding is as follows 122 * system_rev & 0xff000000 -> Omap Class (24xx/34xx) 123 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x) 124 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430) 125 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 ) 126 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD ) 127 * system_rev & 0x000000c0 -> IDCODE revision[6:7] 128 * system_rev & 0x0000003f -> sys_boot[0:5] 129 */ 130 /* Embedding the ES revision info in type field */ 131 system_rev = type; 132 /* Also add IDCODE revision info only two lower bits */ 133 system_rev |= ((rev & 0x3) << 6); 134 135 /* Add in the device type and sys_boot fields (see above) */ 136 if (cpu_is_omap24xx()) { 137 i = OMAP24XX_CONTROL_STATUS; 138 } else if (cpu_is_omap343x()) { 139 i = OMAP343X_CONTROL_STATUS; 140 } else { 141 printk(KERN_ERR "id: unknown CPU type\n"); 142 BUG(); 143 } 144 ctrl_status = omap_ctrl_readl(i); 145 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK | 146 OMAP2_SYSBOOT_4_MASK | 147 OMAP2_SYSBOOT_3_MASK | 148 OMAP2_SYSBOOT_2_MASK | 149 OMAP2_SYSBOOT_1_MASK | 150 OMAP2_SYSBOOT_0_MASK)); 151 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK); 152 } 153 154 155 /* 156 * _set_omap_chip - set the omap_chip global based on OMAP chip type 157 * 158 * Build the omap_chip bits. This variable is used by powerdomain and 159 * clockdomain code to indicate whether structures are applicable for 160 * the current OMAP chip type by ANDing it against a 'platform' bitfield 161 * in the structure. 162 */ 163 static void __init _set_omap_chip(void) 164 { 165 if (cpu_is_omap343x()) { 166 167 omap_chip.oc = CHIP_IS_OMAP3430; 168 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) 169 omap_chip.oc |= CHIP_IS_OMAP3430ES1; 170 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) 171 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 172 173 } else if (cpu_is_omap243x()) { 174 175 /* Currently only supports 2430ES2.1 and 2430-all */ 176 omap_chip.oc |= CHIP_IS_OMAP2430; 177 178 } else if (cpu_is_omap242x()) { 179 180 /* Currently only supports 2420ES2.1.1 and 2420-all */ 181 omap_chip.oc |= CHIP_IS_OMAP2420; 182 183 } else { 184 185 /* Current CPU not supported by this code. */ 186 printk(KERN_WARNING "OMAP chip type code does not yet support " 187 "this CPU type.\n"); 188 WARN_ON(1); 189 190 } 191 192 } 193 194 void __init omap2_check_revision(void) 195 { 196 int i, j; 197 u32 idcode; 198 u32 prod_id; 199 u16 hawkeye; 200 u8 dev_type; 201 u8 rev; 202 203 idcode = read_tap_reg(OMAP_TAP_IDCODE); 204 prod_id = read_tap_reg(tap_prod_id); 205 hawkeye = (idcode >> 12) & 0xffff; 206 rev = (idcode >> 28) & 0x0f; 207 dev_type = (prod_id >> 16) & 0x0f; 208 209 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 210 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 211 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", 212 read_tap_reg(OMAP_TAP_DIE_ID_0)); 213 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 214 read_tap_reg(OMAP_TAP_DIE_ID_1), 215 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); 216 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", 217 read_tap_reg(OMAP_TAP_DIE_ID_2)); 218 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", 219 read_tap_reg(OMAP_TAP_DIE_ID_3)); 220 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 221 prod_id, dev_type); 222 223 /* 224 * Detection for 34xx ES2.0 and above can be done with just 225 * hawkeye and rev. See TRM 1.5.2 Device Identification. 226 * Note that rev cannot be used directly as ES1.0 uses value 0. 227 */ 228 if (hawkeye == 0xb7ae) { 229 system_rev = 0x34300000 | ((1 + rev) << 12); 230 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev); 231 _set_omap_chip(); 232 return; 233 } 234 235 /* Check hawkeye ids */ 236 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 237 if (hawkeye == omap_ids[i].hawkeye) 238 break; 239 } 240 241 if (i == ARRAY_SIZE(omap_ids)) { 242 printk(KERN_ERR "Unknown OMAP CPU id\n"); 243 return; 244 } 245 246 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 247 if (dev_type == omap_ids[j].dev) 248 break; 249 } 250 251 if (j == ARRAY_SIZE(omap_ids)) { 252 printk(KERN_ERR "Unknown OMAP device type. " 253 "Handling it as OMAP%04x\n", 254 omap_ids[i].type >> 16); 255 j = i; 256 } 257 258 _set_system_rev(omap_ids[j].type, rev); 259 260 _set_omap_chip(); 261 262 pr_info("OMAP%04x", system_rev >> 16); 263 if ((system_rev >> 8) & 0x0f) 264 pr_info("ES%x", (system_rev >> 12) & 0xf); 265 pr_info("\n"); 266 267 } 268 269 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 270 { 271 class = omap2_globals->class; 272 tap_base = omap2_globals->tap; 273 274 if (class == 0x3430) 275 tap_prod_id = 0x0210; 276 else 277 tap_prod_id = 0x0208; 278 } 279