1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009-11 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <asm/cputype.h> 23 24 #include "common.h" 25 #include <plat/cpu.h> 26 27 #include <mach/id.h> 28 29 #include "control.h" 30 31 static unsigned int omap_revision; 32 static const char *cpu_rev; 33 u32 omap_features; 34 35 unsigned int omap_rev(void) 36 { 37 return omap_revision; 38 } 39 EXPORT_SYMBOL(omap_rev); 40 41 int omap_type(void) 42 { 43 u32 val = 0; 44 45 if (cpu_is_omap24xx()) { 46 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 47 } else if (cpu_is_am33xx()) { 48 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 49 } else if (cpu_is_omap34xx()) { 50 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 51 } else if (cpu_is_omap44xx()) { 52 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 53 } else { 54 pr_err("Cannot detect omap type!\n"); 55 goto out; 56 } 57 58 val &= OMAP2_DEVICETYPE_MASK; 59 val >>= 8; 60 61 out: 62 return val; 63 } 64 EXPORT_SYMBOL(omap_type); 65 66 67 /*----------------------------------------------------------------------------*/ 68 69 #define OMAP_TAP_IDCODE 0x0204 70 #define OMAP_TAP_DIE_ID_0 0x0218 71 #define OMAP_TAP_DIE_ID_1 0x021C 72 #define OMAP_TAP_DIE_ID_2 0x0220 73 #define OMAP_TAP_DIE_ID_3 0x0224 74 75 #define OMAP_TAP_DIE_ID_44XX_0 0x0200 76 #define OMAP_TAP_DIE_ID_44XX_1 0x0208 77 #define OMAP_TAP_DIE_ID_44XX_2 0x020c 78 #define OMAP_TAP_DIE_ID_44XX_3 0x0210 79 80 #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) 81 82 struct omap_id { 83 u16 hawkeye; /* Silicon type (Hawkeye id) */ 84 u8 dev; /* Device type from production_id reg */ 85 u32 type; /* Combined type id copied to omap_revision */ 86 }; 87 88 /* Register values to detect the OMAP version */ 89 static struct omap_id omap_ids[] __initdata = { 90 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 91 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 92 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 93 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 94 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 95 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 96 }; 97 98 static void __iomem *tap_base; 99 static u16 tap_prod_id; 100 101 void omap_get_die_id(struct omap_die_id *odi) 102 { 103 if (cpu_is_omap44xx()) { 104 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 105 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 106 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 107 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); 108 109 return; 110 } 111 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 112 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 113 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 114 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 115 } 116 117 void __init omap2xxx_check_revision(void) 118 { 119 int i, j; 120 u32 idcode, prod_id; 121 u16 hawkeye; 122 u8 dev_type, rev; 123 struct omap_die_id odi; 124 125 idcode = read_tap_reg(OMAP_TAP_IDCODE); 126 prod_id = read_tap_reg(tap_prod_id); 127 hawkeye = (idcode >> 12) & 0xffff; 128 rev = (idcode >> 28) & 0x0f; 129 dev_type = (prod_id >> 16) & 0x0f; 130 omap_get_die_id(&odi); 131 132 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 133 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 134 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 135 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 136 odi.id_1, (odi.id_1 >> 28) & 0xf); 137 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 138 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 139 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 140 prod_id, dev_type); 141 142 /* Check hawkeye ids */ 143 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 144 if (hawkeye == omap_ids[i].hawkeye) 145 break; 146 } 147 148 if (i == ARRAY_SIZE(omap_ids)) { 149 printk(KERN_ERR "Unknown OMAP CPU id\n"); 150 return; 151 } 152 153 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 154 if (dev_type == omap_ids[j].dev) 155 break; 156 } 157 158 if (j == ARRAY_SIZE(omap_ids)) { 159 printk(KERN_ERR "Unknown OMAP device type. " 160 "Handling it as OMAP%04x\n", 161 omap_ids[i].type >> 16); 162 j = i; 163 } 164 165 pr_info("OMAP%04x", omap_rev() >> 16); 166 if ((omap_rev() >> 8) & 0x0f) 167 pr_info("ES%x", (omap_rev() >> 12) & 0xf); 168 pr_info("\n"); 169 } 170 171 #define OMAP3_SHOW_FEATURE(feat) \ 172 if (omap3_has_ ##feat()) \ 173 printk(#feat" "); 174 175 static void __init omap3_cpuinfo(void) 176 { 177 const char *cpu_name; 178 179 /* 180 * OMAP3430 and OMAP3530 are assumed to be same. 181 * 182 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 183 * on available features. Upon detection, update the CPU id 184 * and CPU class bits. 185 */ 186 if (cpu_is_omap3630()) { 187 cpu_name = "OMAP3630"; 188 } else if (soc_is_am35xx()) { 189 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 190 } else if (cpu_is_ti816x()) { 191 cpu_name = "TI816X"; 192 } else if (cpu_is_am335x()) { 193 cpu_name = "AM335X"; 194 } else if (cpu_is_ti814x()) { 195 cpu_name = "TI814X"; 196 } else if (omap3_has_iva() && omap3_has_sgx()) { 197 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 198 cpu_name = "OMAP3430/3530"; 199 } else if (omap3_has_iva()) { 200 cpu_name = "OMAP3525"; 201 } else if (omap3_has_sgx()) { 202 cpu_name = "OMAP3515"; 203 } else { 204 cpu_name = "OMAP3503"; 205 } 206 207 /* Print verbose information */ 208 pr_info("%s ES%s (", cpu_name, cpu_rev); 209 210 OMAP3_SHOW_FEATURE(l2cache); 211 OMAP3_SHOW_FEATURE(iva); 212 OMAP3_SHOW_FEATURE(sgx); 213 OMAP3_SHOW_FEATURE(neon); 214 OMAP3_SHOW_FEATURE(isp); 215 OMAP3_SHOW_FEATURE(192mhz_clk); 216 217 printk(")\n"); 218 } 219 220 #define OMAP3_CHECK_FEATURE(status,feat) \ 221 if (((status & OMAP3_ ##feat## _MASK) \ 222 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 223 omap_features |= OMAP3_HAS_ ##feat; \ 224 } 225 226 void __init omap3xxx_check_features(void) 227 { 228 u32 status; 229 230 omap_features = 0; 231 232 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 233 234 OMAP3_CHECK_FEATURE(status, L2CACHE); 235 OMAP3_CHECK_FEATURE(status, IVA); 236 OMAP3_CHECK_FEATURE(status, SGX); 237 OMAP3_CHECK_FEATURE(status, NEON); 238 OMAP3_CHECK_FEATURE(status, ISP); 239 if (cpu_is_omap3630()) 240 omap_features |= OMAP3_HAS_192MHZ_CLK; 241 if (cpu_is_omap3430() || cpu_is_omap3630()) 242 omap_features |= OMAP3_HAS_IO_WAKEUP; 243 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || 244 omap_rev() == OMAP3430_REV_ES3_1_2) 245 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; 246 247 omap_features |= OMAP3_HAS_SDRC; 248 249 /* 250 * am35x fixups: 251 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as 252 * reserved and therefore return 0 when read. Unfortunately, 253 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to 254 * mean that a feature is present even though it isn't so clear 255 * the incorrectly set feature bits. 256 */ 257 if (soc_is_am35xx()) 258 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); 259 260 /* 261 * TODO: Get additional info (where applicable) 262 * e.g. Size of L2 cache. 263 */ 264 265 omap3_cpuinfo(); 266 } 267 268 void __init omap4xxx_check_features(void) 269 { 270 u32 si_type; 271 272 if (cpu_is_omap443x()) 273 omap_features |= OMAP4_HAS_MPU_1GHZ; 274 275 276 if (cpu_is_omap446x()) { 277 si_type = 278 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1); 279 switch ((si_type & (3 << 16)) >> 16) { 280 case 2: 281 /* High performance device */ 282 omap_features |= OMAP4_HAS_MPU_1_5GHZ; 283 break; 284 case 1: 285 default: 286 /* Standard device */ 287 omap_features |= OMAP4_HAS_MPU_1_2GHZ; 288 break; 289 } 290 } 291 } 292 293 void __init ti81xx_check_features(void) 294 { 295 omap_features = OMAP3_HAS_NEON; 296 omap3_cpuinfo(); 297 } 298 299 void __init omap3xxx_check_revision(void) 300 { 301 u32 cpuid, idcode; 302 u16 hawkeye; 303 u8 rev; 304 305 /* 306 * We cannot access revision registers on ES1.0. 307 * If the processor type is Cortex-A8 and the revision is 0x0 308 * it means its Cortex r0p0 which is 3430 ES1.0. 309 */ 310 cpuid = read_cpuid(CPUID_ID); 311 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 312 omap_revision = OMAP3430_REV_ES1_0; 313 cpu_rev = "1.0"; 314 return; 315 } 316 317 /* 318 * Detection for 34xx ES2.0 and above can be done with just 319 * hawkeye and rev. See TRM 1.5.2 Device Identification. 320 * Note that rev does not map directly to our defined processor 321 * revision numbers as ES1.0 uses value 0. 322 */ 323 idcode = read_tap_reg(OMAP_TAP_IDCODE); 324 hawkeye = (idcode >> 12) & 0xffff; 325 rev = (idcode >> 28) & 0xff; 326 327 switch (hawkeye) { 328 case 0xb7ae: 329 /* Handle 34xx/35xx devices */ 330 switch (rev) { 331 case 0: /* Take care of early samples */ 332 case 1: 333 omap_revision = OMAP3430_REV_ES2_0; 334 cpu_rev = "2.0"; 335 break; 336 case 2: 337 omap_revision = OMAP3430_REV_ES2_1; 338 cpu_rev = "2.1"; 339 break; 340 case 3: 341 omap_revision = OMAP3430_REV_ES3_0; 342 cpu_rev = "3.0"; 343 break; 344 case 4: 345 omap_revision = OMAP3430_REV_ES3_1; 346 cpu_rev = "3.1"; 347 break; 348 case 7: 349 /* FALLTHROUGH */ 350 default: 351 /* Use the latest known revision as default */ 352 omap_revision = OMAP3430_REV_ES3_1_2; 353 cpu_rev = "3.1.2"; 354 } 355 break; 356 case 0xb868: 357 /* 358 * Handle OMAP/AM 3505/3517 devices 359 * 360 * Set the device to be OMAP3517 here. Actual device 361 * is identified later based on the features. 362 */ 363 switch (rev) { 364 case 0: 365 omap_revision = AM35XX_REV_ES1_0; 366 cpu_rev = "1.0"; 367 break; 368 case 1: 369 /* FALLTHROUGH */ 370 default: 371 omap_revision = AM35XX_REV_ES1_1; 372 cpu_rev = "1.1"; 373 } 374 break; 375 case 0xb891: 376 /* Handle 36xx devices */ 377 378 switch(rev) { 379 case 0: /* Take care of early samples */ 380 omap_revision = OMAP3630_REV_ES1_0; 381 cpu_rev = "1.0"; 382 break; 383 case 1: 384 omap_revision = OMAP3630_REV_ES1_1; 385 cpu_rev = "1.1"; 386 break; 387 case 2: 388 /* FALLTHROUGH */ 389 default: 390 omap_revision = OMAP3630_REV_ES1_2; 391 cpu_rev = "1.2"; 392 } 393 break; 394 case 0xb81e: 395 switch (rev) { 396 case 0: 397 omap_revision = TI8168_REV_ES1_0; 398 cpu_rev = "1.0"; 399 break; 400 case 1: 401 /* FALLTHROUGH */ 402 default: 403 omap_revision = TI8168_REV_ES1_1; 404 cpu_rev = "1.1"; 405 break; 406 } 407 break; 408 case 0xb944: 409 omap_revision = AM335X_REV_ES1_0; 410 cpu_rev = "1.0"; 411 break; 412 case 0xb8f2: 413 switch (rev) { 414 case 0: 415 /* FALLTHROUGH */ 416 case 1: 417 omap_revision = TI8148_REV_ES1_0; 418 cpu_rev = "1.0"; 419 break; 420 case 2: 421 omap_revision = TI8148_REV_ES2_0; 422 cpu_rev = "2.0"; 423 break; 424 case 3: 425 /* FALLTHROUGH */ 426 default: 427 omap_revision = TI8148_REV_ES2_1; 428 cpu_rev = "2.1"; 429 break; 430 } 431 break; 432 default: 433 /* Unknown default to latest silicon rev as default */ 434 omap_revision = OMAP3630_REV_ES1_2; 435 cpu_rev = "1.2"; 436 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); 437 } 438 } 439 440 void __init omap4xxx_check_revision(void) 441 { 442 u32 idcode; 443 u16 hawkeye; 444 u8 rev; 445 446 /* 447 * The IC rev detection is done with hawkeye and rev. 448 * Note that rev does not map directly to defined processor 449 * revision numbers as ES1.0 uses value 0. 450 */ 451 idcode = read_tap_reg(OMAP_TAP_IDCODE); 452 hawkeye = (idcode >> 12) & 0xffff; 453 rev = (idcode >> 28) & 0xf; 454 455 /* 456 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 457 * Use ARM register to detect the correct ES version 458 */ 459 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { 460 idcode = read_cpuid(CPUID_ID); 461 rev = (idcode & 0xf) - 1; 462 } 463 464 switch (hawkeye) { 465 case 0xb852: 466 switch (rev) { 467 case 0: 468 omap_revision = OMAP4430_REV_ES1_0; 469 break; 470 case 1: 471 default: 472 omap_revision = OMAP4430_REV_ES2_0; 473 } 474 break; 475 case 0xb95c: 476 switch (rev) { 477 case 3: 478 omap_revision = OMAP4430_REV_ES2_1; 479 break; 480 case 4: 481 omap_revision = OMAP4430_REV_ES2_2; 482 break; 483 case 6: 484 default: 485 omap_revision = OMAP4430_REV_ES2_3; 486 } 487 break; 488 case 0xb94e: 489 switch (rev) { 490 case 0: 491 omap_revision = OMAP4460_REV_ES1_0; 492 break; 493 case 2: 494 default: 495 omap_revision = OMAP4460_REV_ES1_1; 496 break; 497 } 498 break; 499 case 0xb975: 500 switch (rev) { 501 case 0: 502 default: 503 omap_revision = OMAP4470_REV_ES1_0; 504 break; 505 } 506 break; 507 default: 508 /* Unknown default to latest silicon rev as default */ 509 omap_revision = OMAP4430_REV_ES2_3; 510 } 511 512 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, 513 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); 514 } 515 516 /* 517 * Set up things for map_io and processor detection later on. Gets called 518 * pretty much first thing from board init. For multi-omap, this gets 519 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 520 * detect the exact revision later on in omap2_detect_revision() once map_io 521 * is done. 522 */ 523 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 524 { 525 omap_revision = omap2_globals->class; 526 tap_base = omap2_globals->tap; 527 528 if (cpu_is_omap34xx()) 529 tap_prod_id = 0x0210; 530 else 531 tap_prod_id = 0x0208; 532 } 533