1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 259de3cf1SG, Manjunath Kondaiah /* 359de3cf1SG, Manjunath Kondaiah * OMAP2+ DMA driver 459de3cf1SG, Manjunath Kondaiah * 559de3cf1SG, Manjunath Kondaiah * Copyright (C) 2003 - 2008 Nokia Corporation 659de3cf1SG, Manjunath Kondaiah * Author: Juha Yrjölä <juha.yrjola@nokia.com> 759de3cf1SG, Manjunath Kondaiah * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 859de3cf1SG, Manjunath Kondaiah * Graphics DMA and LCD DMA graphics tranformations 959de3cf1SG, Manjunath Kondaiah * by Imre Deak <imre.deak@nokia.com> 1059de3cf1SG, Manjunath Kondaiah * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. 1159de3cf1SG, Manjunath Kondaiah * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 1259de3cf1SG, Manjunath Kondaiah * 1359de3cf1SG, Manjunath Kondaiah * Copyright (C) 2009 Texas Instruments 1459de3cf1SG, Manjunath Kondaiah * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 1559de3cf1SG, Manjunath Kondaiah * 1659de3cf1SG, Manjunath Kondaiah * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 1759de3cf1SG, Manjunath Kondaiah * Converted DMA library into platform driver 1859de3cf1SG, Manjunath Kondaiah * - G, Manjunath Kondaiah <manjugk@ti.com> 1959de3cf1SG, Manjunath Kondaiah */ 2059de3cf1SG, Manjunath Kondaiah 2159de3cf1SG, Manjunath Kondaiah #include <linux/err.h> 2259de3cf1SG, Manjunath Kondaiah #include <linux/io.h> 2359de3cf1SG, Manjunath Kondaiah #include <linux/slab.h> 2459de3cf1SG, Manjunath Kondaiah #include <linux/module.h> 2559de3cf1SG, Manjunath Kondaiah #include <linux/init.h> 2659de3cf1SG, Manjunath Kondaiah #include <linux/device.h> 27be1f9481STony Lindgren #include <linux/dma-mapping.h> 28731ec4d8SPeter Ujfalusi #include <linux/dmaengine.h> 298d30662aSJon Hunter #include <linux/of.h> 3045c3eb7dSTony Lindgren #include <linux/omap-dma.h> 3159de3cf1SG, Manjunath Kondaiah 32e4c060dbSTony Lindgren #include "soc.h" 332a296c8fSTony Lindgren #include "omap_hwmod.h" 3425c7d49eSTony Lindgren #include "omap_device.h" 3525c7d49eSTony Lindgren 36ad0c381aSRussell King static enum omap_reg_offsets dma_common_ch_end; 37f31cc962SG, Manjunath Kondaiah 3864a2dc3dSRussell King static const struct omap_dma_reg reg_map[] = { 3964a2dc3dSRussell King [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT }, 4064a2dc3dSRussell King [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT }, 4164a2dc3dSRussell King [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT }, 4264a2dc3dSRussell King [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT }, 4364a2dc3dSRussell King [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT }, 4464a2dc3dSRussell King [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT }, 4564a2dc3dSRussell King [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT }, 4664a2dc3dSRussell King [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT }, 4764a2dc3dSRussell King [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT }, 4864a2dc3dSRussell King [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT }, 4964a2dc3dSRussell King [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT }, 5064a2dc3dSRussell King [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT }, 5164a2dc3dSRussell King [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT }, 5264a2dc3dSRussell King [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT }, 5364a2dc3dSRussell King [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT }, 5464a2dc3dSRussell King [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT }, 55f31cc962SG, Manjunath Kondaiah 56f31cc962SG, Manjunath Kondaiah /* Common register offsets */ 5764a2dc3dSRussell King [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT }, 5864a2dc3dSRussell King [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT }, 5964a2dc3dSRussell King [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT }, 6064a2dc3dSRussell King [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT }, 6164a2dc3dSRussell King [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT }, 6264a2dc3dSRussell King [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT }, 6364a2dc3dSRussell King [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT }, 6464a2dc3dSRussell King [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT }, 6564a2dc3dSRussell King [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT }, 6664a2dc3dSRussell King [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT }, 6764a2dc3dSRussell King [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT }, 6864a2dc3dSRussell King [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT }, 6964a2dc3dSRussell King [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT }, 70f31cc962SG, Manjunath Kondaiah 71f31cc962SG, Manjunath Kondaiah /* Channel specific register offsets */ 7264a2dc3dSRussell King [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT }, 7364a2dc3dSRussell King [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT }, 7464a2dc3dSRussell King [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT }, 7564a2dc3dSRussell King [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT }, 7664a2dc3dSRussell King [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT }, 77f31cc962SG, Manjunath Kondaiah 78f31cc962SG, Manjunath Kondaiah /* OMAP4 specific registers */ 7964a2dc3dSRussell King [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT }, 8064a2dc3dSRussell King [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT }, 8164a2dc3dSRussell King [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT }, 82f31cc962SG, Manjunath Kondaiah }; 83f31cc962SG, Manjunath Kondaiah 84f31cc962SG, Manjunath Kondaiah static void __iomem *dma_base; 85f31cc962SG, Manjunath Kondaiah static inline void dma_write(u32 val, int reg, int lch) 86f31cc962SG, Manjunath Kondaiah { 8764a2dc3dSRussell King void __iomem *addr = dma_base; 88f31cc962SG, Manjunath Kondaiah 8964a2dc3dSRussell King addr += reg_map[reg].offset; 9064a2dc3dSRussell King addr += reg_map[reg].stride * lch; 9164a2dc3dSRussell King 92edfaf05cSVictor Kamensky writel_relaxed(val, addr); 93f31cc962SG, Manjunath Kondaiah } 94f31cc962SG, Manjunath Kondaiah 95f31cc962SG, Manjunath Kondaiah static inline u32 dma_read(int reg, int lch) 96f31cc962SG, Manjunath Kondaiah { 9764a2dc3dSRussell King void __iomem *addr = dma_base; 98f31cc962SG, Manjunath Kondaiah 9964a2dc3dSRussell King addr += reg_map[reg].offset; 10064a2dc3dSRussell King addr += reg_map[reg].stride * lch; 10164a2dc3dSRussell King 102edfaf05cSVictor Kamensky return readl_relaxed(addr); 103f31cc962SG, Manjunath Kondaiah } 104f31cc962SG, Manjunath Kondaiah 105f31cc962SG, Manjunath Kondaiah static void omap2_clear_dma(int lch) 106f31cc962SG, Manjunath Kondaiah { 107ad0c381aSRussell King int i; 108f31cc962SG, Manjunath Kondaiah 109ad0c381aSRussell King for (i = CSDP; i <= dma_common_ch_end; i += 1) 110f31cc962SG, Manjunath Kondaiah dma_write(0, i, lch); 111f31cc962SG, Manjunath Kondaiah } 112f31cc962SG, Manjunath Kondaiah 113f31cc962SG, Manjunath Kondaiah static void omap2_show_dma_caps(void) 114f31cc962SG, Manjunath Kondaiah { 115f31cc962SG, Manjunath Kondaiah u8 revision = dma_read(REVISION, 0) & 0xff; 116f31cc962SG, Manjunath Kondaiah printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 117f31cc962SG, Manjunath Kondaiah revision >> 4, revision & 0xf); 118f31cc962SG, Manjunath Kondaiah } 119f31cc962SG, Manjunath Kondaiah 1200ef64986SRussell King static unsigned configure_dma_errata(void) 121f31cc962SG, Manjunath Kondaiah { 1220ef64986SRussell King unsigned errata = 0; 123f31cc962SG, Manjunath Kondaiah 124f31cc962SG, Manjunath Kondaiah /* 125f31cc962SG, Manjunath Kondaiah * Errata applicable for OMAP2430ES1.0 and all omap2420 126f31cc962SG, Manjunath Kondaiah * 127f31cc962SG, Manjunath Kondaiah * I. 128f31cc962SG, Manjunath Kondaiah * Erratum ID: Not Available 129f31cc962SG, Manjunath Kondaiah * Inter Frame DMA buffering issue DMA will wrongly 130f31cc962SG, Manjunath Kondaiah * buffer elements if packing and bursting is enabled. This might 131f31cc962SG, Manjunath Kondaiah * result in data gets stalled in FIFO at the end of the block. 132f31cc962SG, Manjunath Kondaiah * Workaround: DMA channels must have BUFFERING_DISABLED bit set to 133f31cc962SG, Manjunath Kondaiah * guarantee no data will stay in the DMA FIFO in case inter frame 134f31cc962SG, Manjunath Kondaiah * buffering occurs 135f31cc962SG, Manjunath Kondaiah * 136f31cc962SG, Manjunath Kondaiah * II. 137f31cc962SG, Manjunath Kondaiah * Erratum ID: Not Available 138f31cc962SG, Manjunath Kondaiah * DMA may hang when several channels are used in parallel 139f31cc962SG, Manjunath Kondaiah * In the following configuration, DMA channel hanging can occur: 140f31cc962SG, Manjunath Kondaiah * a. Channel i, hardware synchronized, is enabled 141f31cc962SG, Manjunath Kondaiah * b. Another channel (Channel x), software synchronized, is enabled. 142f31cc962SG, Manjunath Kondaiah * c. Channel i is disabled before end of transfer 143f31cc962SG, Manjunath Kondaiah * d. Channel i is reenabled. 144f31cc962SG, Manjunath Kondaiah * e. Steps 1 to 4 are repeated a certain number of times. 145f31cc962SG, Manjunath Kondaiah * f. A third channel (Channel y), software synchronized, is enabled. 146f31cc962SG, Manjunath Kondaiah * Channel x and Channel y may hang immediately after step 'f'. 147f31cc962SG, Manjunath Kondaiah * Workaround: 148f31cc962SG, Manjunath Kondaiah * For any channel used - make sure NextLCH_ID is set to the value j. 149f31cc962SG, Manjunath Kondaiah */ 150f31cc962SG, Manjunath Kondaiah if (cpu_is_omap2420() || (cpu_is_omap2430() && 151f31cc962SG, Manjunath Kondaiah (omap_type() == OMAP2430_REV_ES1_0))) { 152f31cc962SG, Manjunath Kondaiah 153f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING); 154f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS); 155f31cc962SG, Manjunath Kondaiah } 156f31cc962SG, Manjunath Kondaiah 157f31cc962SG, Manjunath Kondaiah /* 158f31cc962SG, Manjunath Kondaiah * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled 159f31cc962SG, Manjunath Kondaiah * after a transaction error. 160f31cc962SG, Manjunath Kondaiah * Workaround: SW should explicitely disable the channel. 161f31cc962SG, Manjunath Kondaiah */ 162f31cc962SG, Manjunath Kondaiah if (cpu_class_is_omap2()) 163f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ERRATA_i378); 164f31cc962SG, Manjunath Kondaiah 165f31cc962SG, Manjunath Kondaiah /* 166f31cc962SG, Manjunath Kondaiah * Erratum ID: i541: sDMA FIFO draining does not finish 167f31cc962SG, Manjunath Kondaiah * If sDMA channel is disabled on the fly, sDMA enters standby even 168f31cc962SG, Manjunath Kondaiah * through FIFO Drain is still in progress 169f31cc962SG, Manjunath Kondaiah * Workaround: Put sDMA in NoStandby more before a logical channel is 170f31cc962SG, Manjunath Kondaiah * disabled, then put it back to SmartStandby right after the channel 171f31cc962SG, Manjunath Kondaiah * finishes FIFO draining. 172f31cc962SG, Manjunath Kondaiah */ 173f31cc962SG, Manjunath Kondaiah if (cpu_is_omap34xx()) 174f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ERRATA_i541); 175f31cc962SG, Manjunath Kondaiah 176f31cc962SG, Manjunath Kondaiah /* 177f31cc962SG, Manjunath Kondaiah * Erratum ID: i88 : Special programming model needed to disable DMA 178f31cc962SG, Manjunath Kondaiah * before end of block. 179f31cc962SG, Manjunath Kondaiah * Workaround: software must ensure that the DMA is configured in No 180f31cc962SG, Manjunath Kondaiah * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01") 181f31cc962SG, Manjunath Kondaiah */ 182f31cc962SG, Manjunath Kondaiah if (omap_type() == OMAP3430_REV_ES1_0) 183f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ERRATA_i88); 184f31cc962SG, Manjunath Kondaiah 185f31cc962SG, Manjunath Kondaiah /* 186f31cc962SG, Manjunath Kondaiah * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is 187f31cc962SG, Manjunath Kondaiah * read before the DMA controller finished disabling the channel. 188f31cc962SG, Manjunath Kondaiah */ 189f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ERRATA_3_3); 190f31cc962SG, Manjunath Kondaiah 191f31cc962SG, Manjunath Kondaiah /* 192f31cc962SG, Manjunath Kondaiah * Erratum ID: Not Available 193f31cc962SG, Manjunath Kondaiah * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared 194f31cc962SG, Manjunath Kondaiah * after secure sram context save and restore. 195f31cc962SG, Manjunath Kondaiah * Work around: Hence we need to manually clear those IRQs to avoid 196f31cc962SG, Manjunath Kondaiah * spurious interrupts. This affects only secure devices. 197f31cc962SG, Manjunath Kondaiah */ 198f31cc962SG, Manjunath Kondaiah if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 199f31cc962SG, Manjunath Kondaiah SET_DMA_ERRATA(DMA_ROMCODE_BUG); 200f31cc962SG, Manjunath Kondaiah 201f31cc962SG, Manjunath Kondaiah return errata; 202f31cc962SG, Manjunath Kondaiah } 203f31cc962SG, Manjunath Kondaiah 204868772d8SPeter Ujfalusi static const struct dma_slave_map omap24xx_sdma_dt_map[] = { 205868772d8SPeter Ujfalusi /* external DMA requests when tusb6010 is used */ 206868772d8SPeter Ujfalusi { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) }, 207868772d8SPeter Ujfalusi { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) }, 208868772d8SPeter Ujfalusi { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */ 209868772d8SPeter Ujfalusi { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */ 210868772d8SPeter Ujfalusi { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */ 211868772d8SPeter Ujfalusi { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ 212731ec4d8SPeter Ujfalusi }; 213731ec4d8SPeter Ujfalusi 214c6797bcdSTony Lindgren static struct omap_dma_dev_attr dma_attr = { 215c6797bcdSTony Lindgren .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 216c6797bcdSTony Lindgren IS_CSSA_32 | IS_CDSA_32, 217c6797bcdSTony Lindgren .lch_count = 32, 218c6797bcdSTony Lindgren }; 219c6797bcdSTony Lindgren 220*211010aeSTony Lindgren struct omap_system_dma_plat_info dma_plat_info = { 221596c471bSRussell King .reg_map = reg_map, 222596c471bSRussell King .channel_stride = 0x60, 223c6797bcdSTony Lindgren .dma_attr = &dma_attr, 22434a378fcSRussell King .show_dma_caps = omap2_show_dma_caps, 22534a378fcSRussell King .clear_dma = omap2_clear_dma, 22634a378fcSRussell King .dma_write = dma_write, 22734a378fcSRussell King .dma_read = dma_read, 22834a378fcSRussell King }; 22934a378fcSRussell King 23010e998ffSBhumika Goyal static struct platform_device_info omap_dma_dev_info __initdata = { 231596c471bSRussell King .name = "omap-dma-engine", 232596c471bSRussell King .id = -1, 233596c471bSRussell King .dma_mask = DMA_BIT_MASK(32), 234596c471bSRussell King }; 235596c471bSRussell King 23659de3cf1SG, Manjunath Kondaiah /* One time initializations */ 23759de3cf1SG, Manjunath Kondaiah static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) 23859de3cf1SG, Manjunath Kondaiah { 2393528c58eSKevin Hilman struct platform_device *pdev; 240f31cc962SG, Manjunath Kondaiah struct resource *mem; 24159de3cf1SG, Manjunath Kondaiah char *name = "omap_dma_system"; 24259de3cf1SG, Manjunath Kondaiah 243c6797bcdSTony Lindgren dma_plat_info.errata = configure_dma_errata(); 24459de3cf1SG, Manjunath Kondaiah 245868772d8SPeter Ujfalusi if (soc_is_omap24xx()) { 246868772d8SPeter Ujfalusi /* DMA slave map for drivers not yet converted to DT */ 247c6797bcdSTony Lindgren dma_plat_info.slave_map = omap24xx_sdma_dt_map; 248c6797bcdSTony Lindgren dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); 249868772d8SPeter Ujfalusi } 250731ec4d8SPeter Ujfalusi 251c6797bcdSTony Lindgren if (!soc_is_omap242x()) 252c6797bcdSTony Lindgren dma_attr.dev_caps |= IS_RW_PRIORITY; 253c6797bcdSTony Lindgren 254c6797bcdSTony Lindgren if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 255c6797bcdSTony Lindgren dma_attr.dev_caps |= HS_CHANNELS_RESERVED; 256c6797bcdSTony Lindgren 257c6797bcdSTony Lindgren pdev = omap_device_build(name, 0, oh, &dma_plat_info, 258c6797bcdSTony Lindgren sizeof(dma_plat_info)); 2593528c58eSKevin Hilman if (IS_ERR(pdev)) { 26025985edcSLucas De Marchi pr_err("%s: Can't build omap_device for %s:%s.\n", 26159de3cf1SG, Manjunath Kondaiah __func__, name, oh->name); 2623528c58eSKevin Hilman return PTR_ERR(pdev); 26359de3cf1SG, Manjunath Kondaiah } 26459de3cf1SG, Manjunath Kondaiah 265596c471bSRussell King omap_dma_dev_info.res = pdev->resource; 266596c471bSRussell King omap_dma_dev_info.num_res = pdev->num_resources; 267596c471bSRussell King 2683528c58eSKevin Hilman mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 269f31cc962SG, Manjunath Kondaiah if (!mem) { 2703528c58eSKevin Hilman dev_err(&pdev->dev, "%s: no mem resource\n", __func__); 271f31cc962SG, Manjunath Kondaiah return -EINVAL; 272f31cc962SG, Manjunath Kondaiah } 273596c471bSRussell King 274f31cc962SG, Manjunath Kondaiah dma_base = ioremap(mem->start, resource_size(mem)); 275f31cc962SG, Manjunath Kondaiah if (!dma_base) { 2763528c58eSKevin Hilman dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); 277f31cc962SG, Manjunath Kondaiah return -ENOMEM; 278f31cc962SG, Manjunath Kondaiah } 279f31cc962SG, Manjunath Kondaiah 280f6d5e079SR Sricharan /* Check the capabilities register for descriptor loading feature */ 281f002180cSTony Lindgren if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx()) 282f6d5e079SR Sricharan dma_common_ch_end = CCFN; 283f002180cSTony Lindgren else 284f002180cSTony Lindgren dma_common_ch_end = CCDN; 285f6d5e079SR Sricharan 28659de3cf1SG, Manjunath Kondaiah return 0; 28759de3cf1SG, Manjunath Kondaiah } 28859de3cf1SG, Manjunath Kondaiah 28959de3cf1SG, Manjunath Kondaiah static int __init omap2_system_dma_init(void) 29059de3cf1SG, Manjunath Kondaiah { 2910278bad1STony Lindgren return omap_hwmod_for_each_by_class("dma", 29259de3cf1SG, Manjunath Kondaiah omap2_system_dma_init_dev, NULL); 29359de3cf1SG, Manjunath Kondaiah } 294b76c8b19STony Lindgren omap_arch_initcall(omap2_system_dma_init); 295