1 /* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/err.h> 25 #include <linux/delay.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/slab.h> 29 #include <linux/mfd/syscon.h> 30 #include <linux/regmap.h> 31 32 #include <linux/platform_data/omapdss.h> 33 #include "omap_hwmod.h" 34 #include "omap_device.h" 35 #include "omap-pm.h" 36 #include "common.h" 37 38 #include "soc.h" 39 #include "iomap.h" 40 #include "control.h" 41 #include "display.h" 42 #include "prm.h" 43 44 #define DISPC_CONTROL 0x0040 45 #define DISPC_CONTROL2 0x0238 46 #define DISPC_CONTROL3 0x0848 47 #define DISPC_IRQSTATUS 0x0018 48 49 #define DSS_CONTROL 0x40 50 #define DSS_SDI_CONTROL 0x44 51 #define DSS_PLL_CONTROL 0x48 52 53 #define LCD_EN_MASK (0x1 << 0) 54 #define DIGIT_EN_MASK (0x1 << 1) 55 56 #define FRAMEDONE_IRQ_SHIFT 0 57 #define EVSYNC_EVEN_IRQ_SHIFT 2 58 #define EVSYNC_ODD_IRQ_SHIFT 3 59 #define FRAMEDONE2_IRQ_SHIFT 22 60 #define FRAMEDONE3_IRQ_SHIFT 30 61 #define FRAMEDONETV_IRQ_SHIFT 24 62 63 /* 64 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 65 * reset before deciding that something has gone wrong 66 */ 67 #define FRAMEDONE_IRQ_TIMEOUT 100 68 69 static struct platform_device omap_display_device = { 70 .name = "omapdss", 71 .id = -1, 72 .dev = { 73 .platform_data = NULL, 74 }, 75 }; 76 77 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 78 79 static struct regmap *omap4_dsi_mux_syscon; 80 81 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 82 { 83 u32 enable_mask, enable_shift; 84 u32 pipd_mask, pipd_shift; 85 u32 reg; 86 87 if (dsi_id == 0) { 88 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 89 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 90 pipd_mask = OMAP4_DSI1_PIPD_MASK; 91 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 92 } else if (dsi_id == 1) { 93 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 94 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 95 pipd_mask = OMAP4_DSI2_PIPD_MASK; 96 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 97 } else { 98 return -ENODEV; 99 } 100 101 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, ®); 102 103 reg &= ~enable_mask; 104 reg &= ~pipd_mask; 105 106 reg |= (lanes << enable_shift) & enable_mask; 107 reg |= (lanes << pipd_shift) & pipd_mask; 108 109 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg); 110 111 return 0; 112 } 113 114 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 115 { 116 if (cpu_is_omap44xx()) 117 return omap4_dsi_mux_pads(dsi_id, lane_mask); 118 119 return 0; 120 } 121 122 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 123 { 124 if (cpu_is_omap44xx()) 125 omap4_dsi_mux_pads(dsi_id, 0); 126 } 127 128 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 129 { 130 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); 131 } 132 133 static enum omapdss_version __init omap_display_get_version(void) 134 { 135 if (cpu_is_omap24xx()) 136 return OMAPDSS_VER_OMAP24xx; 137 else if (cpu_is_omap3630()) 138 return OMAPDSS_VER_OMAP3630; 139 else if (cpu_is_omap34xx()) { 140 if (soc_is_am35xx()) { 141 return OMAPDSS_VER_AM35xx; 142 } else { 143 if (omap_rev() < OMAP3430_REV_ES3_0) 144 return OMAPDSS_VER_OMAP34xx_ES1; 145 else 146 return OMAPDSS_VER_OMAP34xx_ES3; 147 } 148 } else if (omap_rev() == OMAP4430_REV_ES1_0) 149 return OMAPDSS_VER_OMAP4430_ES1; 150 else if (omap_rev() == OMAP4430_REV_ES2_0 || 151 omap_rev() == OMAP4430_REV_ES2_1 || 152 omap_rev() == OMAP4430_REV_ES2_2) 153 return OMAPDSS_VER_OMAP4430_ES2; 154 else if (cpu_is_omap44xx()) 155 return OMAPDSS_VER_OMAP4; 156 else if (soc_is_omap54xx()) 157 return OMAPDSS_VER_OMAP5; 158 else if (soc_is_am43xx()) 159 return OMAPDSS_VER_AM43xx; 160 else if (soc_is_dra7xx()) 161 return OMAPDSS_VER_DRA7xx; 162 else 163 return OMAPDSS_VER_UNKNOWN; 164 } 165 166 static void dispc_disable_outputs(void) 167 { 168 u32 v, irq_mask = 0; 169 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 170 int i; 171 struct omap_dss_dispc_dev_attr *da; 172 struct omap_hwmod *oh; 173 174 oh = omap_hwmod_lookup("dss_dispc"); 175 if (!oh) { 176 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 177 return; 178 } 179 180 if (!oh->dev_attr) { 181 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 182 return; 183 } 184 185 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 186 187 /* store value of LCDENABLE and DIGITENABLE bits */ 188 v = omap_hwmod_read(oh, DISPC_CONTROL); 189 lcd_en = v & LCD_EN_MASK; 190 digit_en = v & DIGIT_EN_MASK; 191 192 /* store value of LCDENABLE for LCD2 */ 193 if (da->manager_count > 2) { 194 v = omap_hwmod_read(oh, DISPC_CONTROL2); 195 lcd2_en = v & LCD_EN_MASK; 196 } 197 198 /* store value of LCDENABLE for LCD3 */ 199 if (da->manager_count > 3) { 200 v = omap_hwmod_read(oh, DISPC_CONTROL3); 201 lcd3_en = v & LCD_EN_MASK; 202 } 203 204 if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) 205 return; /* no managers currently enabled */ 206 207 /* 208 * If any manager was enabled, we need to disable it before 209 * DSS clocks are disabled or DISPC module is reset 210 */ 211 if (lcd_en) 212 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 213 214 if (digit_en) { 215 if (da->has_framedonetv_irq) { 216 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 217 } else { 218 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 219 1 << EVSYNC_ODD_IRQ_SHIFT; 220 } 221 } 222 223 if (lcd2_en) 224 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 225 if (lcd3_en) 226 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; 227 228 /* 229 * clear any previous FRAMEDONE, FRAMEDONETV, 230 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts 231 */ 232 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 233 234 /* disable LCD and TV managers */ 235 v = omap_hwmod_read(oh, DISPC_CONTROL); 236 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 237 omap_hwmod_write(v, oh, DISPC_CONTROL); 238 239 /* disable LCD2 manager */ 240 if (da->manager_count > 2) { 241 v = omap_hwmod_read(oh, DISPC_CONTROL2); 242 v &= ~LCD_EN_MASK; 243 omap_hwmod_write(v, oh, DISPC_CONTROL2); 244 } 245 246 /* disable LCD3 manager */ 247 if (da->manager_count > 3) { 248 v = omap_hwmod_read(oh, DISPC_CONTROL3); 249 v &= ~LCD_EN_MASK; 250 omap_hwmod_write(v, oh, DISPC_CONTROL3); 251 } 252 253 i = 0; 254 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 255 irq_mask) { 256 i++; 257 if (i > FRAMEDONE_IRQ_TIMEOUT) { 258 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); 259 break; 260 } 261 mdelay(1); 262 } 263 } 264 265 int omap_dss_reset(struct omap_hwmod *oh) 266 { 267 struct omap_hwmod_opt_clk *oc; 268 int c = 0; 269 int i, r; 270 271 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 272 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 273 return -EINVAL; 274 } 275 276 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 277 if (oc->_clk) 278 clk_prepare_enable(oc->_clk); 279 280 dispc_disable_outputs(); 281 282 /* clear SDI registers */ 283 if (cpu_is_omap3430()) { 284 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 285 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 286 } 287 288 /* 289 * clear DSS_CONTROL register to switch DSS clock sources to 290 * PRCM clock, if any 291 */ 292 omap_hwmod_write(0x0, oh, DSS_CONTROL); 293 294 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 295 & SYSS_RESETDONE_MASK), 296 MAX_MODULE_SOFTRESET_WAIT, c); 297 298 if (c == MAX_MODULE_SOFTRESET_WAIT) 299 pr_warn("dss_core: waiting for reset to finish failed\n"); 300 else 301 pr_debug("dss_core: softreset done\n"); 302 303 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 304 if (oc->_clk) 305 clk_disable_unprepare(oc->_clk); 306 307 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 308 309 return r; 310 } 311 312 static const char * const omapdss_compat_names[] __initconst = { 313 "ti,omap2-dss", 314 "ti,omap3-dss", 315 "ti,omap4-dss", 316 "ti,omap5-dss", 317 "ti,dra7-dss", 318 }; 319 320 static struct device_node * __init omapdss_find_dss_of_node(void) 321 { 322 struct device_node *node; 323 int i; 324 325 for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) { 326 node = of_find_compatible_node(NULL, NULL, 327 omapdss_compat_names[i]); 328 if (node) 329 return node; 330 } 331 332 return NULL; 333 } 334 335 int __init omapdss_init_of(void) 336 { 337 int r; 338 enum omapdss_version ver; 339 struct device_node *node; 340 struct platform_device *pdev; 341 342 static struct omap_dss_board_info board_data = { 343 .dsi_enable_pads = omap_dsi_enable_pads, 344 .dsi_disable_pads = omap_dsi_disable_pads, 345 .set_min_bus_tput = omap_dss_set_min_bus_tput, 346 }; 347 348 /* only create dss helper devices if dss is enabled in the .dts */ 349 350 node = omapdss_find_dss_of_node(); 351 if (!node) 352 return 0; 353 354 if (!of_device_is_available(node)) 355 return 0; 356 357 ver = omap_display_get_version(); 358 359 if (ver == OMAPDSS_VER_UNKNOWN) { 360 pr_err("DSS not supported on this SoC\n"); 361 return -ENODEV; 362 } 363 364 pdev = of_find_device_by_node(node); 365 366 if (!pdev) { 367 pr_err("Unable to find DSS platform device\n"); 368 return -ENODEV; 369 } 370 371 r = of_platform_populate(node, NULL, NULL, &pdev->dev); 372 if (r) { 373 pr_err("Unable to populate DSS submodule devices\n"); 374 return r; 375 } 376 377 board_data.version = ver; 378 379 omap_display_device.dev.platform_data = &board_data; 380 381 r = platform_device_register(&omap_display_device); 382 if (r < 0) { 383 pr_err("Unable to register omapdss device\n"); 384 return r; 385 } 386 387 /* create DRM device */ 388 r = omap_init_drm(); 389 if (r < 0) { 390 pr_err("Unable to register omapdrm device\n"); 391 return r; 392 } 393 394 /* create vrfb device */ 395 r = omap_init_vrfb(); 396 if (r < 0) { 397 pr_err("Unable to register omapvrfb device\n"); 398 return r; 399 } 400 401 /* create FB device */ 402 r = omap_init_fb(); 403 if (r < 0) { 404 pr_err("Unable to register omapfb device\n"); 405 return r; 406 } 407 408 /* create V4L2 display device */ 409 r = omap_init_vout(); 410 if (r < 0) { 411 pr_err("Unable to register omap_vout device\n"); 412 return r; 413 } 414 415 /* add DSI info for omap4 */ 416 node = of_find_node_by_name(NULL, "omap4_padconf_global"); 417 if (node) 418 omap4_dsi_mux_syscon = syscon_node_to_regmap(node); 419 420 return 0; 421 } 422