1 /* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/err.h> 25 #include <linux/delay.h> 26 27 #include <video/omapdss.h> 28 #include "omap_hwmod.h" 29 #include "omap_device.h" 30 #include "omap-pm.h" 31 #include "common.h" 32 33 #include "soc.h" 34 #include "iomap.h" 35 #include "control.h" 36 #include "display.h" 37 #include "prm.h" 38 39 #define DISPC_CONTROL 0x0040 40 #define DISPC_CONTROL2 0x0238 41 #define DISPC_CONTROL3 0x0848 42 #define DISPC_IRQSTATUS 0x0018 43 44 #define DSS_SYSCONFIG 0x10 45 #define DSS_SYSSTATUS 0x14 46 #define DSS_CONTROL 0x40 47 #define DSS_SDI_CONTROL 0x44 48 #define DSS_PLL_CONTROL 0x48 49 50 #define LCD_EN_MASK (0x1 << 0) 51 #define DIGIT_EN_MASK (0x1 << 1) 52 53 #define FRAMEDONE_IRQ_SHIFT 0 54 #define EVSYNC_EVEN_IRQ_SHIFT 2 55 #define EVSYNC_ODD_IRQ_SHIFT 3 56 #define FRAMEDONE2_IRQ_SHIFT 22 57 #define FRAMEDONE3_IRQ_SHIFT 30 58 #define FRAMEDONETV_IRQ_SHIFT 24 59 60 /* 61 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 62 * reset before deciding that something has gone wrong 63 */ 64 #define FRAMEDONE_IRQ_TIMEOUT 100 65 66 static struct platform_device omap_display_device = { 67 .name = "omapdss", 68 .id = -1, 69 .dev = { 70 .platform_data = NULL, 71 }, 72 }; 73 74 struct omap_dss_hwmod_data { 75 const char *oh_name; 76 const char *dev_name; 77 const int id; 78 }; 79 80 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = { 81 { "dss_core", "omapdss_dss", -1 }, 82 { "dss_dispc", "omapdss_dispc", -1 }, 83 { "dss_rfbi", "omapdss_rfbi", -1 }, 84 { "dss_venc", "omapdss_venc", -1 }, 85 }; 86 87 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = { 88 { "dss_core", "omapdss_dss", -1 }, 89 { "dss_dispc", "omapdss_dispc", -1 }, 90 { "dss_rfbi", "omapdss_rfbi", -1 }, 91 { "dss_venc", "omapdss_venc", -1 }, 92 { "dss_dsi1", "omapdss_dsi", 0 }, 93 }; 94 95 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { 96 { "dss_core", "omapdss_dss", -1 }, 97 { "dss_dispc", "omapdss_dispc", -1 }, 98 { "dss_rfbi", "omapdss_rfbi", -1 }, 99 { "dss_dsi1", "omapdss_dsi", 0 }, 100 { "dss_dsi2", "omapdss_dsi", 1 }, 101 { "dss_hdmi", "omapdss_hdmi", -1 }, 102 }; 103 104 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 105 { 106 u32 enable_mask, enable_shift; 107 u32 pipd_mask, pipd_shift; 108 u32 reg; 109 110 if (dsi_id == 0) { 111 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 112 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 113 pipd_mask = OMAP4_DSI1_PIPD_MASK; 114 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 115 } else if (dsi_id == 1) { 116 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 117 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 118 pipd_mask = OMAP4_DSI2_PIPD_MASK; 119 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 120 } else { 121 return -ENODEV; 122 } 123 124 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 125 126 reg &= ~enable_mask; 127 reg &= ~pipd_mask; 128 129 reg |= (lanes << enable_shift) & enable_mask; 130 reg |= (lanes << pipd_shift) & pipd_mask; 131 132 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 133 134 return 0; 135 } 136 137 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 138 { 139 if (cpu_is_omap44xx()) 140 return omap4_dsi_mux_pads(dsi_id, lane_mask); 141 142 return 0; 143 } 144 145 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 146 { 147 if (cpu_is_omap44xx()) 148 omap4_dsi_mux_pads(dsi_id, 0); 149 } 150 151 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 152 { 153 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); 154 } 155 156 static struct platform_device *create_dss_pdev(const char *pdev_name, 157 int pdev_id, const char *oh_name, void *pdata, int pdata_len, 158 struct platform_device *parent) 159 { 160 struct platform_device *pdev; 161 struct omap_device *od; 162 struct omap_hwmod *ohs[1]; 163 struct omap_hwmod *oh; 164 int r; 165 166 oh = omap_hwmod_lookup(oh_name); 167 if (!oh) { 168 pr_err("Could not look up %s\n", oh_name); 169 r = -ENODEV; 170 goto err; 171 } 172 173 pdev = platform_device_alloc(pdev_name, pdev_id); 174 if (!pdev) { 175 pr_err("Could not create pdev for %s\n", pdev_name); 176 r = -ENOMEM; 177 goto err; 178 } 179 180 if (parent != NULL) 181 pdev->dev.parent = &parent->dev; 182 183 if (pdev->id != -1) 184 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 185 else 186 dev_set_name(&pdev->dev, "%s", pdev->name); 187 188 ohs[0] = oh; 189 od = omap_device_alloc(pdev, ohs, 1); 190 if (IS_ERR(od)) { 191 pr_err("Could not alloc omap_device for %s\n", pdev_name); 192 r = -ENOMEM; 193 goto err; 194 } 195 196 r = platform_device_add_data(pdev, pdata, pdata_len); 197 if (r) { 198 pr_err("Could not set pdata for %s\n", pdev_name); 199 goto err; 200 } 201 202 r = omap_device_register(pdev); 203 if (r) { 204 pr_err("Could not register omap_device for %s\n", pdev_name); 205 goto err; 206 } 207 208 return pdev; 209 210 err: 211 return ERR_PTR(r); 212 } 213 214 static struct platform_device *create_simple_dss_pdev(const char *pdev_name, 215 int pdev_id, void *pdata, int pdata_len, 216 struct platform_device *parent) 217 { 218 struct platform_device *pdev; 219 int r; 220 221 pdev = platform_device_alloc(pdev_name, pdev_id); 222 if (!pdev) { 223 pr_err("Could not create pdev for %s\n", pdev_name); 224 r = -ENOMEM; 225 goto err; 226 } 227 228 if (parent != NULL) 229 pdev->dev.parent = &parent->dev; 230 231 if (pdev->id != -1) 232 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 233 else 234 dev_set_name(&pdev->dev, "%s", pdev->name); 235 236 r = platform_device_add_data(pdev, pdata, pdata_len); 237 if (r) { 238 pr_err("Could not set pdata for %s\n", pdev_name); 239 goto err; 240 } 241 242 r = platform_device_add(pdev); 243 if (r) { 244 pr_err("Could not register platform_device for %s\n", pdev_name); 245 goto err; 246 } 247 248 return pdev; 249 250 err: 251 return ERR_PTR(r); 252 } 253 254 static enum omapdss_version __init omap_display_get_version(void) 255 { 256 if (cpu_is_omap24xx()) 257 return OMAPDSS_VER_OMAP24xx; 258 else if (cpu_is_omap3630()) 259 return OMAPDSS_VER_OMAP3630; 260 else if (cpu_is_omap34xx()) { 261 if (soc_is_am35xx()) { 262 return OMAPDSS_VER_AM35xx; 263 } else { 264 if (omap_rev() < OMAP3430_REV_ES3_0) 265 return OMAPDSS_VER_OMAP34xx_ES1; 266 else 267 return OMAPDSS_VER_OMAP34xx_ES3; 268 } 269 } else if (omap_rev() == OMAP4430_REV_ES1_0) 270 return OMAPDSS_VER_OMAP4430_ES1; 271 else if (omap_rev() == OMAP4430_REV_ES2_0 || 272 omap_rev() == OMAP4430_REV_ES2_1 || 273 omap_rev() == OMAP4430_REV_ES2_2) 274 return OMAPDSS_VER_OMAP4430_ES2; 275 else if (cpu_is_omap44xx()) 276 return OMAPDSS_VER_OMAP4; 277 else if (soc_is_omap54xx()) 278 return OMAPDSS_VER_OMAP5; 279 else 280 return OMAPDSS_VER_UNKNOWN; 281 } 282 283 int __init omap_display_init(struct omap_dss_board_info *board_data) 284 { 285 int r = 0; 286 struct platform_device *pdev; 287 int i, oh_count; 288 const struct omap_dss_hwmod_data *curr_dss_hwmod; 289 struct platform_device *dss_pdev; 290 enum omapdss_version ver; 291 292 /* create omapdss device */ 293 294 ver = omap_display_get_version(); 295 296 if (ver == OMAPDSS_VER_UNKNOWN) { 297 pr_err("DSS not supported on this SoC\n"); 298 return -ENODEV; 299 } 300 301 board_data->version = ver; 302 board_data->dsi_enable_pads = omap_dsi_enable_pads; 303 board_data->dsi_disable_pads = omap_dsi_disable_pads; 304 board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count; 305 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput; 306 307 omap_display_device.dev.platform_data = board_data; 308 309 r = platform_device_register(&omap_display_device); 310 if (r < 0) { 311 pr_err("Unable to register omapdss device\n"); 312 return r; 313 } 314 315 /* create devices for dss hwmods */ 316 317 if (cpu_is_omap24xx()) { 318 curr_dss_hwmod = omap2_dss_hwmod_data; 319 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data); 320 } else if (cpu_is_omap34xx()) { 321 curr_dss_hwmod = omap3_dss_hwmod_data; 322 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data); 323 } else { 324 curr_dss_hwmod = omap4_dss_hwmod_data; 325 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); 326 } 327 328 /* 329 * First create the pdev for dss_core, which is used as a parent device 330 * by the other dss pdevs. Note: dss_core has to be the first item in 331 * the hwmod list. 332 */ 333 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name, 334 curr_dss_hwmod[0].id, 335 curr_dss_hwmod[0].oh_name, 336 board_data, sizeof(*board_data), 337 NULL); 338 339 if (IS_ERR(dss_pdev)) { 340 pr_err("Could not build omap_device for %s\n", 341 curr_dss_hwmod[0].oh_name); 342 343 return PTR_ERR(dss_pdev); 344 } 345 346 for (i = 1; i < oh_count; i++) { 347 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name, 348 curr_dss_hwmod[i].id, 349 curr_dss_hwmod[i].oh_name, 350 board_data, sizeof(*board_data), 351 dss_pdev); 352 353 if (IS_ERR(pdev)) { 354 pr_err("Could not build omap_device for %s\n", 355 curr_dss_hwmod[i].oh_name); 356 357 return PTR_ERR(pdev); 358 } 359 } 360 361 /* Create devices for DPI and SDI */ 362 363 pdev = create_simple_dss_pdev("omapdss_dpi", 0, 364 board_data, sizeof(*board_data), dss_pdev); 365 if (IS_ERR(pdev)) { 366 pr_err("Could not build platform_device for omapdss_dpi\n"); 367 return PTR_ERR(pdev); 368 } 369 370 if (cpu_is_omap34xx()) { 371 pdev = create_simple_dss_pdev("omapdss_sdi", 0, 372 board_data, sizeof(*board_data), dss_pdev); 373 if (IS_ERR(pdev)) { 374 pr_err("Could not build platform_device for omapdss_sdi\n"); 375 return PTR_ERR(pdev); 376 } 377 } 378 379 /* create DRM device */ 380 r = omap_init_drm(); 381 if (r < 0) { 382 pr_err("Unable to register omapdrm device\n"); 383 return r; 384 } 385 386 /* create vrfb device */ 387 r = omap_init_vrfb(); 388 if (r < 0) { 389 pr_err("Unable to register omapvrfb device\n"); 390 return r; 391 } 392 393 /* create FB device */ 394 r = omap_init_fb(); 395 if (r < 0) { 396 pr_err("Unable to register omapfb device\n"); 397 return r; 398 } 399 400 /* create V4L2 display device */ 401 r = omap_init_vout(); 402 if (r < 0) { 403 pr_err("Unable to register omap_vout device\n"); 404 return r; 405 } 406 407 return 0; 408 } 409 410 static void dispc_disable_outputs(void) 411 { 412 u32 v, irq_mask = 0; 413 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 414 int i; 415 struct omap_dss_dispc_dev_attr *da; 416 struct omap_hwmod *oh; 417 418 oh = omap_hwmod_lookup("dss_dispc"); 419 if (!oh) { 420 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 421 return; 422 } 423 424 if (!oh->dev_attr) { 425 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 426 return; 427 } 428 429 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 430 431 /* store value of LCDENABLE and DIGITENABLE bits */ 432 v = omap_hwmod_read(oh, DISPC_CONTROL); 433 lcd_en = v & LCD_EN_MASK; 434 digit_en = v & DIGIT_EN_MASK; 435 436 /* store value of LCDENABLE for LCD2 */ 437 if (da->manager_count > 2) { 438 v = omap_hwmod_read(oh, DISPC_CONTROL2); 439 lcd2_en = v & LCD_EN_MASK; 440 } 441 442 /* store value of LCDENABLE for LCD3 */ 443 if (da->manager_count > 3) { 444 v = omap_hwmod_read(oh, DISPC_CONTROL3); 445 lcd3_en = v & LCD_EN_MASK; 446 } 447 448 if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) 449 return; /* no managers currently enabled */ 450 451 /* 452 * If any manager was enabled, we need to disable it before 453 * DSS clocks are disabled or DISPC module is reset 454 */ 455 if (lcd_en) 456 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 457 458 if (digit_en) { 459 if (da->has_framedonetv_irq) { 460 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 461 } else { 462 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 463 1 << EVSYNC_ODD_IRQ_SHIFT; 464 } 465 } 466 467 if (lcd2_en) 468 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 469 if (lcd3_en) 470 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; 471 472 /* 473 * clear any previous FRAMEDONE, FRAMEDONETV, 474 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts 475 */ 476 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 477 478 /* disable LCD and TV managers */ 479 v = omap_hwmod_read(oh, DISPC_CONTROL); 480 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 481 omap_hwmod_write(v, oh, DISPC_CONTROL); 482 483 /* disable LCD2 manager */ 484 if (da->manager_count > 2) { 485 v = omap_hwmod_read(oh, DISPC_CONTROL2); 486 v &= ~LCD_EN_MASK; 487 omap_hwmod_write(v, oh, DISPC_CONTROL2); 488 } 489 490 /* disable LCD3 manager */ 491 if (da->manager_count > 3) { 492 v = omap_hwmod_read(oh, DISPC_CONTROL3); 493 v &= ~LCD_EN_MASK; 494 omap_hwmod_write(v, oh, DISPC_CONTROL3); 495 } 496 497 i = 0; 498 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 499 irq_mask) { 500 i++; 501 if (i > FRAMEDONE_IRQ_TIMEOUT) { 502 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); 503 break; 504 } 505 mdelay(1); 506 } 507 } 508 509 int omap_dss_reset(struct omap_hwmod *oh) 510 { 511 struct omap_hwmod_opt_clk *oc; 512 int c = 0; 513 int i, r; 514 515 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 516 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 517 return -EINVAL; 518 } 519 520 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 521 if (oc->_clk) 522 clk_prepare_enable(oc->_clk); 523 524 dispc_disable_outputs(); 525 526 /* clear SDI registers */ 527 if (cpu_is_omap3430()) { 528 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 529 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 530 } 531 532 /* 533 * clear DSS_CONTROL register to switch DSS clock sources to 534 * PRCM clock, if any 535 */ 536 omap_hwmod_write(0x0, oh, DSS_CONTROL); 537 538 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 539 & SYSS_RESETDONE_MASK), 540 MAX_MODULE_SOFTRESET_WAIT, c); 541 542 if (c == MAX_MODULE_SOFTRESET_WAIT) 543 pr_warning("dss_core: waiting for reset to finish failed\n"); 544 else 545 pr_debug("dss_core: softreset done\n"); 546 547 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 548 if (oc->_clk) 549 clk_disable_unprepare(oc->_clk); 550 551 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 552 553 return r; 554 } 555