1 /* 2 * arch/arm/mach-omap2/control.h 3 * 4 * OMAP2/3/4 System Control Module definitions 5 * 6 * Copyright (C) 2007-2010 Texas Instruments, Inc. 7 * Copyright (C) 2007-2008, 2010 Nokia Corporation 8 * 9 * Written by Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H 17 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H 18 19 #include <mach/io.h> 20 #include <mach/ctrl_module_core_44xx.h> 21 #include <mach/ctrl_module_wkup_44xx.h> 22 #include <mach/ctrl_module_pad_core_44xx.h> 23 #include <mach/ctrl_module_pad_wkup_44xx.h> 24 25 #ifndef __ASSEMBLY__ 26 #define OMAP242X_CTRL_REGADDR(reg) \ 27 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 28 #define OMAP243X_CTRL_REGADDR(reg) \ 29 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 30 #define OMAP343X_CTRL_REGADDR(reg) \ 31 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 32 #else 33 #define OMAP242X_CTRL_REGADDR(reg) \ 34 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 35 #define OMAP243X_CTRL_REGADDR(reg) \ 36 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 37 #define OMAP343X_CTRL_REGADDR(reg) \ 38 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 39 #endif /* __ASSEMBLY__ */ 40 41 /* 42 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 43 * OMAP24XX and OMAP34XX. 44 */ 45 46 /* Control submodule offsets */ 47 48 #define OMAP2_CONTROL_INTERFACE 0x000 49 #define OMAP2_CONTROL_PADCONFS 0x030 50 #define OMAP2_CONTROL_GENERAL 0x270 51 #define OMAP343X_CONTROL_MEM_WKUP 0x600 52 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 53 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 54 55 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 56 57 #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) 58 59 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ 60 #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) 61 #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) 62 #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) 63 #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) 64 #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) 65 #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) 66 #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) 67 #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) 68 #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) 69 #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) 70 #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) 71 #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) 72 73 /* 242x-only CONTROL_GENERAL register offsets */ 74 #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ 75 #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) 76 77 /* 243x-only CONTROL_GENERAL register offsets */ 78 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ 79 #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) 80 #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) 81 #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 82 #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 83 #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 84 #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) 85 86 /* 24xx-only CONTROL_GENERAL register offsets */ 87 #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 88 #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) 89 #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) 90 #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) 91 #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) 92 #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) 93 #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) 94 #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 95 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 96 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 97 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 98 #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 99 #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 100 #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) 101 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) 102 #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) 103 #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) 104 #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) 105 #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) 106 #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) 107 #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) 108 #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) 109 #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) 110 #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) 111 #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) 112 #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) 113 #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) 114 #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) 115 #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) 116 #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 117 #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 118 119 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) 120 121 /* 34xx-only CONTROL_GENERAL register offsets */ 122 #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 123 #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 124 #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) 125 #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) 126 #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) 127 #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) 128 #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) 129 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) 130 #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 131 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 132 #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) 133 #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) 134 #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) 135 #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) 136 #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) 137 #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) 138 #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) 139 #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) 140 #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) 141 #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) 142 #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) 143 #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) 144 #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) 145 #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) 146 #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) 147 #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) 148 #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) 149 #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) 150 #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 151 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 152 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 153 #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ 154 + ((i) >> 1) * 4 + (!((i) & 1)) * 2) 155 #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) 156 #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) 157 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) 158 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) 159 #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) 160 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) 161 #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) 162 #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) 163 #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) 164 #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) 165 #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) 166 167 /* AM35XX only CONTROL_GENERAL register offsets */ 168 #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) 169 #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) 170 #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) 171 #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) 172 #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) 173 #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) 174 #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) 175 176 /* 34xx PADCONF register offsets */ 177 #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ 178 (i)*2) 179 #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) 180 #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) 181 #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) 182 #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) 183 #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) 184 #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) 185 #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) 186 #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) 187 #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) 188 #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) 189 #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) 190 #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) 191 #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) 192 #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) 193 #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) 194 #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) 195 #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) 196 #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) 197 198 /* 34xx GENERAL_WKUP regist offsets */ 199 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ 200 0x008 + (i)) 201 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) 202 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) 203 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) 204 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 205 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 206 207 /* 36xx-only RTA - Retention till Accesss control registers and bits */ 208 #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C 209 #define OMAP36XX_RTA_DISABLE 0x0 210 211 /* 34xx D2D idle-related pins, handled by PM core */ 212 #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 213 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 214 215 /* 216 * REVISIT: This list of registers is not comprehensive - there are more 217 * that should be added. 218 */ 219 220 /* 221 * Control module register bit defines - these should eventually go into 222 * their own regbits file. Some of these will be complicated, depending 223 * on the device type (general-purpose, emulator, test, secure, bad, other) 224 * and the security mode (secure, non-secure, don't care) 225 */ 226 /* CONTROL_DEVCONF0 bits */ 227 #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ 228 #define OMAP24XX_USBSTANDBYCTRL (1 << 15) 229 #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 230 #define OMAP2_MCBSP1_FSR_MASK (1 << 4) 231 #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) 232 #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 233 234 /* CONTROL_DEVCONF1 bits */ 235 #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) 236 #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ 237 #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 238 #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 239 #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 240 241 /* CONTROL_STATUS bits */ 242 #define OMAP2_DEVICETYPE_MASK (0x7 << 8) 243 #define OMAP2_SYSBOOT_5_MASK (1 << 5) 244 #define OMAP2_SYSBOOT_4_MASK (1 << 4) 245 #define OMAP2_SYSBOOT_3_MASK (1 << 3) 246 #define OMAP2_SYSBOOT_2_MASK (1 << 2) 247 #define OMAP2_SYSBOOT_1_MASK (1 << 1) 248 #define OMAP2_SYSBOOT_0_MASK (1 << 0) 249 250 /* CONTROL_PBIAS_LITE bits */ 251 #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) 252 #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) 253 #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) 254 #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) 255 #define OMAP343X_PBIASLITEVMODE1 (1 << 8) 256 #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) 257 #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) 258 #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) 259 #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 260 #define OMAP2_PBIASLITEVMODE0 (1 << 0) 261 262 /* CONTROL_PROG_IO1 bits */ 263 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 264 265 /* CONTROL_IVA2_BOOTMOD bits */ 266 #define OMAP3_IVA2_BOOTMOD_SHIFT 0 267 #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 268 #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) 269 270 /* CONTROL_PADCONF_X bits */ 271 #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 272 #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 273 274 #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 275 #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 276 #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 277 #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ 278 OMAP343X_SCRATCHPAD + reg) 279 280 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 281 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 282 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 283 #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 284 #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 285 #define AM35XX_USBOTG_FCLK_SHIFT 8 286 #define AM35XX_CPGMAC_FCLK_SHIFT 9 287 #define AM35XX_VPFE_FCLK_SHIFT 10 288 289 /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ 290 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 291 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 292 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 293 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) 294 #define AM35XX_USBOTGSS_INT_CLR BIT(4) 295 #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) 296 #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 297 #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 298 299 /*AM35XX CONTROL_IP_SW_RESET bits*/ 300 #define AM35XX_USBOTGSS_SW_RST BIT(0) 301 #define AM35XX_CPGMACSS_SW_RST BIT(1) 302 #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 303 #define AM35XX_HECC_SW_RST BIT(3) 304 #define AM35XX_VPFE_PCLK_SW_RST BIT(4) 305 306 /* 307 * CONTROL OMAP STATUS register to identify OMAP3 features 308 */ 309 #define OMAP3_CONTROL_OMAP_STATUS 0x044c 310 311 #define OMAP3_SGX_SHIFT 13 312 #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) 313 #define FEAT_SGX_FULL 0 314 #define FEAT_SGX_HALF 1 315 #define FEAT_SGX_NONE 2 316 317 #define OMAP3_IVA_SHIFT 12 318 #define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) 319 #define FEAT_IVA 0 320 #define FEAT_IVA_NONE 1 321 322 #define OMAP3_L2CACHE_SHIFT 10 323 #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) 324 #define FEAT_L2CACHE_NONE 0 325 #define FEAT_L2CACHE_64KB 1 326 #define FEAT_L2CACHE_128KB 2 327 #define FEAT_L2CACHE_256KB 3 328 329 #define OMAP3_ISP_SHIFT 5 330 #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) 331 #define FEAT_ISP 0 332 #define FEAT_ISP_NONE 1 333 334 #define OMAP3_NEON_SHIFT 4 335 #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) 336 #define FEAT_NEON 0 337 #define FEAT_NEON_NONE 1 338 339 340 #ifndef __ASSEMBLY__ 341 #ifdef CONFIG_ARCH_OMAP2PLUS 342 extern void __iomem *omap_ctrl_base_get(void); 343 extern u8 omap_ctrl_readb(u16 offset); 344 extern u16 omap_ctrl_readw(u16 offset); 345 extern u32 omap_ctrl_readl(u16 offset); 346 extern u32 omap4_ctrl_pad_readl(u16 offset); 347 extern void omap_ctrl_writeb(u8 val, u16 offset); 348 extern void omap_ctrl_writew(u16 val, u16 offset); 349 extern void omap_ctrl_writel(u32 val, u16 offset); 350 extern void omap4_ctrl_pad_writel(u32 val, u16 offset); 351 352 extern void omap3_save_scratchpad_contents(void); 353 extern void omap3_clear_scratchpad_contents(void); 354 extern u32 *get_restore_pointer(void); 355 extern u32 *get_es3_restore_pointer(void); 356 extern u32 *get_omap3630_restore_pointer(void); 357 extern u32 omap3_arm_context[128]; 358 extern void omap3_control_save_context(void); 359 extern void omap3_control_restore_context(void); 360 extern void omap3630_ctrl_disable_rta(void); 361 #else 362 #define omap_ctrl_base_get() 0 363 #define omap_ctrl_readb(x) 0 364 #define omap_ctrl_readw(x) 0 365 #define omap_ctrl_readl(x) 0 366 #define omap4_ctrl_pad_readl(x) 0 367 #define omap_ctrl_writeb(x, y) WARN_ON(1) 368 #define omap_ctrl_writew(x, y) WARN_ON(1) 369 #define omap_ctrl_writel(x, y) WARN_ON(1) 370 #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) 371 #endif 372 #endif /* __ASSEMBLY__ */ 373 374 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ 375 376