1 /* 2 * arch/arm/mach-omap2/control.h 3 * 4 * OMAP2/3/4 System Control Module definitions 5 * 6 * Copyright (C) 2007-2010 Texas Instruments, Inc. 7 * Copyright (C) 2007-2008, 2010 Nokia Corporation 8 * 9 * Written by Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H 17 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H 18 19 #include "am33xx.h" 20 21 #ifndef __ASSEMBLY__ 22 #define OMAP242X_CTRL_REGADDR(reg) \ 23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 24 #define OMAP243X_CTRL_REGADDR(reg) \ 25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 26 #define OMAP343X_CTRL_REGADDR(reg) \ 27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 28 #define AM33XX_CTRL_REGADDR(reg) \ 29 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) 30 #else 31 #define OMAP242X_CTRL_REGADDR(reg) \ 32 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 33 #define OMAP243X_CTRL_REGADDR(reg) \ 34 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 35 #define OMAP343X_CTRL_REGADDR(reg) \ 36 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 37 #define AM33XX_CTRL_REGADDR(reg) \ 38 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) 39 #endif /* __ASSEMBLY__ */ 40 41 /* 42 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 43 * OMAP24XX and OMAP34XX. 44 */ 45 46 /* Control submodule offsets */ 47 48 #define OMAP2_CONTROL_INTERFACE 0x000 49 #define OMAP2_CONTROL_PADCONFS 0x030 50 #define OMAP2_CONTROL_GENERAL 0x270 51 #define OMAP343X_CONTROL_MEM_WKUP 0x600 52 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 53 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 54 55 /* TI81XX spefic control submodules */ 56 #define TI81XX_CONTROL_DEVCONF 0x600 57 58 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 59 60 #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) 61 62 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ 63 #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) 64 #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) 65 #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) 66 #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) 67 #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) 68 #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) 69 #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) 70 #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) 71 #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) 72 #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) 73 #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) 74 #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) 75 76 /* 242x-only CONTROL_GENERAL register offsets */ 77 #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ 78 #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) 79 80 /* 243x-only CONTROL_GENERAL register offsets */ 81 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ 82 #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) 83 #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) 84 #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 85 #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 86 #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 87 #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) 88 89 /* 24xx-only CONTROL_GENERAL register offsets */ 90 #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 91 #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) 92 #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) 93 #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) 94 #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) 95 #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) 96 #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) 97 #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 98 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 99 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 100 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 101 #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 102 #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 103 #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) 104 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) 105 #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) 106 #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) 107 #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) 108 #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) 109 #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) 110 #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) 111 #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) 112 #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) 113 #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) 114 #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) 115 #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) 116 #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) 117 #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) 118 #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) 119 #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 120 #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 121 122 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) 123 124 /* 34xx-only CONTROL_GENERAL register offsets */ 125 #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 126 #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 127 #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) 128 #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) 129 #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) 130 #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) 131 #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) 132 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) 133 #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 134 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 135 #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) 136 #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) 137 #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) 138 #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) 139 #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) 140 #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) 141 #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) 142 #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) 143 #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) 144 #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) 145 #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) 146 #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) 147 #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) 148 #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) 149 #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) 150 #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) 151 #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) 152 #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) 153 #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 154 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) 155 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) 156 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) 157 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) 158 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 159 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) 160 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 161 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) 162 #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) 163 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 164 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 165 #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ 166 + ((i) >> 1) * 4 + (!((i) & 1)) * 2) 167 #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) 168 #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) 169 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) 170 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) 171 #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) 172 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) 173 #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) 174 #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) 175 #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) 176 #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) 177 #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) 178 179 /* OMAP3630 only CONTROL_GENERAL register offsets */ 180 #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) 181 #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) 182 #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) 183 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 184 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 185 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) 186 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0) 187 188 /* OMAP44xx control efuse offsets */ 189 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C 190 #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F 191 #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 192 #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 193 #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 194 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 195 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 196 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 197 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 198 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 199 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A 200 201 /* AM35XX only CONTROL_GENERAL register offsets */ 202 #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) 203 #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) 204 #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) 205 #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) 206 #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) 207 #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) 208 #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) 209 210 /* 34xx PADCONF register offsets */ 211 #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ 212 (i)*2) 213 #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) 214 #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) 215 #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) 216 #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) 217 #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) 218 #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) 219 #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) 220 #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) 221 #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) 222 #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) 223 #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) 224 #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) 225 #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) 226 #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) 227 #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) 228 #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) 229 #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) 230 #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) 231 232 /* 34xx GENERAL_WKUP register offsets */ 233 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ 234 0x008 + (i)) 235 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) 236 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) 237 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) 238 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 239 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 240 241 /* 36xx-only RTA - Retention till Access control registers and bits */ 242 #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C 243 #define OMAP36XX_RTA_DISABLE 0x0 244 245 /* 34xx D2D idle-related pins, handled by PM core */ 246 #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 247 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 248 249 /* TI81XX CONTROL_DEVCONF register offsets */ 250 #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) 251 252 /* OMAP4 CONTROL MODULE */ 253 #define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 254 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 255 #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 256 #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 257 #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 258 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 259 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 260 261 /* OMAP4 CONTROL_DSIPHY */ 262 #define OMAP4_DSI2_LANEENABLE_SHIFT 29 263 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 264 #define OMAP4_DSI1_LANEENABLE_SHIFT 24 265 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 266 #define OMAP4_DSI1_PIPD_SHIFT 19 267 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 268 #define OMAP4_DSI2_PIPD_SHIFT 14 269 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 270 271 /* OMAP4 CONTROL_CAMERA_RX */ 272 #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 273 #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) 274 #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 275 #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) 276 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 277 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) 278 #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 279 #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) 280 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 281 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) 282 #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 283 #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) 284 285 /* OMAP54XX CONTROL STATUS register */ 286 #define OMAP5XXX_CONTROL_STATUS 0x134 287 #define OMAP5_DEVICETYPE_MASK (0x7 << 6) 288 289 /* DRA7XX CONTROL CORE BOOTSTRAP */ 290 #define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4 291 #define DRA7_SPEEDSELECT_MASK (0x3 << 8) 292 293 /* 294 * REVISIT: This list of registers is not comprehensive - there are more 295 * that should be added. 296 */ 297 298 /* 299 * Control module register bit defines - these should eventually go into 300 * their own regbits file. Some of these will be complicated, depending 301 * on the device type (general-purpose, emulator, test, secure, bad, other) 302 * and the security mode (secure, non-secure, don't care) 303 */ 304 /* CONTROL_DEVCONF0 bits */ 305 #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ 306 #define OMAP24XX_USBSTANDBYCTRL (1 << 15) 307 #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 308 #define OMAP2_MCBSP1_FSR_MASK (1 << 4) 309 #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) 310 #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 311 312 /* CONTROL_DEVCONF1 bits */ 313 #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) 314 #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ 315 #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 316 #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 317 #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 318 319 /* CONTROL_STATUS bits */ 320 #define OMAP2_DEVICETYPE_MASK (0x7 << 8) 321 #define OMAP2_SYSBOOT_5_MASK (1 << 5) 322 #define OMAP2_SYSBOOT_4_MASK (1 << 4) 323 #define OMAP2_SYSBOOT_3_MASK (1 << 3) 324 #define OMAP2_SYSBOOT_2_MASK (1 << 2) 325 #define OMAP2_SYSBOOT_1_MASK (1 << 1) 326 #define OMAP2_SYSBOOT_0_MASK (1 << 0) 327 328 /* CONTROL_PBIAS_LITE bits */ 329 #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) 330 #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) 331 #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) 332 #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) 333 #define OMAP343X_PBIASLITEVMODE1 (1 << 8) 334 #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) 335 #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) 336 #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) 337 #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 338 #define OMAP2_PBIASLITEVMODE0 (1 << 0) 339 340 /* CONTROL_PROG_IO1 bits */ 341 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 342 343 /* CONTROL_IVA2_BOOTMOD bits */ 344 #define OMAP3_IVA2_BOOTMOD_SHIFT 0 345 #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 346 #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) 347 348 /* CONTROL_PADCONF_X bits */ 349 #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 350 #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 351 352 #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 353 #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 354 #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 355 #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ 356 OMAP343X_SCRATCHPAD + reg) 357 358 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 359 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 360 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 361 #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 362 #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 363 #define AM35XX_USBOTG_FCLK_SHIFT 8 364 #define AM35XX_CPGMAC_FCLK_SHIFT 9 365 #define AM35XX_VPFE_FCLK_SHIFT 10 366 367 /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ 368 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 369 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 370 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 371 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) 372 #define AM35XX_USBOTGSS_INT_CLR BIT(4) 373 #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) 374 #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 375 #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 376 377 /* AM35XX CONTROL_IP_SW_RESET bits */ 378 #define AM35XX_USBOTGSS_SW_RST BIT(0) 379 #define AM35XX_CPGMACSS_SW_RST BIT(1) 380 #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 381 #define AM35XX_HECC_SW_RST BIT(3) 382 #define AM35XX_VPFE_PCLK_SW_RST BIT(4) 383 384 /* AM33XX CONTROL_STATUS register */ 385 #define AM33XX_CONTROL_STATUS 0x040 386 #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc 387 388 /* AM33XX CONTROL_STATUS bitfields (partial) */ 389 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 390 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 391 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) 392 393 /* AM33XX PWMSS Control register */ 394 #define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664 395 396 /* AM33XX PWMSS Control bitfields */ 397 #define AM33XX_PWMSS0_TBCLKEN_SHIFT 0 398 #define AM33XX_PWMSS1_TBCLKEN_SHIFT 1 399 #define AM33XX_PWMSS2_TBCLKEN_SHIFT 2 400 401 /* DEV Feature register to identify AM33XX features */ 402 #define AM33XX_DEV_FEATURE 0x604 403 #define AM33XX_SGX_MASK BIT(29) 404 405 /* CONTROL OMAP STATUS register to identify OMAP3 features */ 406 #define OMAP3_CONTROL_OMAP_STATUS 0x044c 407 408 #define OMAP3_SGX_SHIFT 13 409 #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) 410 #define FEAT_SGX_FULL 0 411 #define FEAT_SGX_HALF 1 412 #define FEAT_SGX_NONE 2 413 414 #define OMAP3_IVA_SHIFT 12 415 #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) 416 #define FEAT_IVA 0 417 #define FEAT_IVA_NONE 1 418 419 #define OMAP3_L2CACHE_SHIFT 10 420 #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) 421 #define FEAT_L2CACHE_NONE 0 422 #define FEAT_L2CACHE_64KB 1 423 #define FEAT_L2CACHE_128KB 2 424 #define FEAT_L2CACHE_256KB 3 425 426 #define OMAP3_ISP_SHIFT 5 427 #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) 428 #define FEAT_ISP 0 429 #define FEAT_ISP_NONE 1 430 431 #define OMAP3_NEON_SHIFT 4 432 #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) 433 #define FEAT_NEON 0 434 #define FEAT_NEON_NONE 1 435 436 437 #ifndef __ASSEMBLY__ 438 #ifdef CONFIG_ARCH_OMAP2PLUS 439 extern void __iomem *omap_ctrl_base_get(void); 440 extern u8 omap_ctrl_readb(u16 offset); 441 extern u16 omap_ctrl_readw(u16 offset); 442 extern u32 omap_ctrl_readl(u16 offset); 443 extern u32 omap4_ctrl_pad_readl(u16 offset); 444 extern void omap_ctrl_writeb(u8 val, u16 offset); 445 extern void omap_ctrl_writew(u16 val, u16 offset); 446 extern void omap_ctrl_writel(u32 val, u16 offset); 447 extern void omap4_ctrl_pad_writel(u32 val, u16 offset); 448 449 extern void omap3_save_scratchpad_contents(void); 450 extern void omap3_clear_scratchpad_contents(void); 451 extern void omap3_restore(void); 452 extern void omap3_restore_es3(void); 453 extern void omap3_restore_3630(void); 454 extern u32 omap3_arm_context[128]; 455 extern void omap3_control_save_context(void); 456 extern void omap3_control_restore_context(void); 457 extern void omap3_ctrl_write_boot_mode(u8 bootmode); 458 extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); 459 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); 460 extern void omap3630_ctrl_disable_rta(void); 461 extern int omap3_ctrl_save_padconf(void); 462 void omap3_ctrl_init(void); 463 extern void omap2_set_globals_control(void __iomem *ctrl, 464 void __iomem *ctrl_pad); 465 #else 466 #define omap_ctrl_base_get() 0 467 #define omap_ctrl_readb(x) 0 468 #define omap_ctrl_readw(x) 0 469 #define omap_ctrl_readl(x) 0 470 #define omap4_ctrl_pad_readl(x) 0 471 #define omap_ctrl_writeb(x, y) WARN_ON(1) 472 #define omap_ctrl_writew(x, y) WARN_ON(1) 473 #define omap_ctrl_writel(x, y) WARN_ON(1) 474 #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) 475 #endif 476 #endif /* __ASSEMBLY__ */ 477 478 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ 479 480