1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 18 #include <plat/common.h> 19 #include <plat/control.h> 20 #include <plat/sdrc.h> 21 #include "cm-regbits-34xx.h" 22 #include "prm-regbits-34xx.h" 23 #include "cm.h" 24 #include "prm.h" 25 #include "sdrc.h" 26 27 static void __iomem *omap2_ctrl_base; 28 29 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 30 struct omap3_scratchpad { 31 u32 boot_config_ptr; 32 u32 public_restore_ptr; 33 u32 secure_ram_restore_ptr; 34 u32 sdrc_module_semaphore; 35 u32 prcm_block_offset; 36 u32 sdrc_block_offset; 37 }; 38 39 struct omap3_scratchpad_prcm_block { 40 u32 prm_clksrc_ctrl; 41 u32 prm_clksel; 42 u32 cm_clksel_core; 43 u32 cm_clksel_wkup; 44 u32 cm_clken_pll; 45 u32 cm_autoidle_pll; 46 u32 cm_clksel1_pll; 47 u32 cm_clksel2_pll; 48 u32 cm_clksel3_pll; 49 u32 cm_clken_pll_mpu; 50 u32 cm_autoidle_pll_mpu; 51 u32 cm_clksel1_pll_mpu; 52 u32 cm_clksel2_pll_mpu; 53 u32 prcm_block_size; 54 }; 55 56 struct omap3_scratchpad_sdrc_block { 57 u16 sysconfig; 58 u16 cs_cfg; 59 u16 sharing; 60 u16 err_type; 61 u32 dll_a_ctrl; 62 u32 dll_b_ctrl; 63 u32 power; 64 u32 cs_0; 65 u32 mcfg_0; 66 u16 mr_0; 67 u16 emr_1_0; 68 u16 emr_2_0; 69 u16 emr_3_0; 70 u32 actim_ctrla_0; 71 u32 actim_ctrlb_0; 72 u32 rfr_ctrl_0; 73 u32 cs_1; 74 u32 mcfg_1; 75 u16 mr_1; 76 u16 emr_1_1; 77 u16 emr_2_1; 78 u16 emr_3_1; 79 u32 actim_ctrla_1; 80 u32 actim_ctrlb_1; 81 u32 rfr_ctrl_1; 82 u16 dcdl_1_ctrl; 83 u16 dcdl_2_ctrl; 84 u32 flags; 85 u32 block_size; 86 }; 87 88 void *omap3_secure_ram_storage; 89 90 /* 91 * This is used to store ARM registers in SDRAM before attempting 92 * an MPU OFF. The save and restore happens from the SRAM sleep code. 93 * The address is stored in scratchpad, so that it can be used 94 * during the restore path. 95 */ 96 u32 omap3_arm_context[128]; 97 98 struct omap3_control_regs { 99 u32 sysconfig; 100 u32 devconf0; 101 u32 mem_dftrw0; 102 u32 mem_dftrw1; 103 u32 msuspendmux_0; 104 u32 msuspendmux_1; 105 u32 msuspendmux_2; 106 u32 msuspendmux_3; 107 u32 msuspendmux_4; 108 u32 msuspendmux_5; 109 u32 sec_ctrl; 110 u32 devconf1; 111 u32 csirxfe; 112 u32 iva2_bootaddr; 113 u32 iva2_bootmod; 114 u32 debobs_0; 115 u32 debobs_1; 116 u32 debobs_2; 117 u32 debobs_3; 118 u32 debobs_4; 119 u32 debobs_5; 120 u32 debobs_6; 121 u32 debobs_7; 122 u32 debobs_8; 123 u32 prog_io0; 124 u32 prog_io1; 125 u32 dss_dpll_spreading; 126 u32 core_dpll_spreading; 127 u32 per_dpll_spreading; 128 u32 usbhost_dpll_spreading; 129 u32 pbias_lite; 130 u32 temp_sensor; 131 u32 sramldo4; 132 u32 sramldo5; 133 u32 csi; 134 }; 135 136 static struct omap3_control_regs control_context; 137 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 138 139 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 140 141 void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 142 { 143 /* Static mapping, never released */ 144 if (omap2_globals->ctrl) { 145 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); 146 WARN_ON(!omap2_ctrl_base); 147 } 148 } 149 150 void __iomem *omap_ctrl_base_get(void) 151 { 152 return omap2_ctrl_base; 153 } 154 155 u8 omap_ctrl_readb(u16 offset) 156 { 157 return __raw_readb(OMAP_CTRL_REGADDR(offset)); 158 } 159 160 u16 omap_ctrl_readw(u16 offset) 161 { 162 return __raw_readw(OMAP_CTRL_REGADDR(offset)); 163 } 164 165 u32 omap_ctrl_readl(u16 offset) 166 { 167 return __raw_readl(OMAP_CTRL_REGADDR(offset)); 168 } 169 170 void omap_ctrl_writeb(u8 val, u16 offset) 171 { 172 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 173 } 174 175 void omap_ctrl_writew(u16 val, u16 offset) 176 { 177 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 178 } 179 180 void omap_ctrl_writel(u32 val, u16 offset) 181 { 182 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 183 } 184 185 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 186 /* 187 * Clears the scratchpad contents in case of cold boot- 188 * called during bootup 189 */ 190 void omap3_clear_scratchpad_contents(void) 191 { 192 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 193 u32 *v_addr; 194 u32 offset = 0; 195 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 196 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 197 OMAP3430_GLOBAL_COLD_RST_MASK) { 198 for ( ; offset <= max_offset; offset += 0x4) 199 __raw_writel(0x0, (v_addr + offset)); 200 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 201 OMAP3430_GR_MOD, 202 OMAP3_PRM_RSTST_OFFSET); 203 } 204 } 205 206 /* Populate the scratchpad structure with restore structure */ 207 void omap3_save_scratchpad_contents(void) 208 { 209 void * __iomem scratchpad_address; 210 u32 arm_context_addr; 211 struct omap3_scratchpad scratchpad_contents; 212 struct omap3_scratchpad_prcm_block prcm_block_contents; 213 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 214 215 /* Populate the Scratchpad contents */ 216 scratchpad_contents.boot_config_ptr = 0x0; 217 if (omap_rev() != OMAP3430_REV_ES3_0 && 218 omap_rev() != OMAP3430_REV_ES3_1) 219 scratchpad_contents.public_restore_ptr = 220 virt_to_phys(get_restore_pointer()); 221 else 222 scratchpad_contents.public_restore_ptr = 223 virt_to_phys(get_es3_restore_pointer()); 224 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 225 scratchpad_contents.secure_ram_restore_ptr = 0x0; 226 else 227 scratchpad_contents.secure_ram_restore_ptr = 228 (u32) __pa(omap3_secure_ram_storage); 229 scratchpad_contents.sdrc_module_semaphore = 0x0; 230 scratchpad_contents.prcm_block_offset = 0x2C; 231 scratchpad_contents.sdrc_block_offset = 0x64; 232 233 /* Populate the PRCM block contents */ 234 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, 235 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 236 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, 237 OMAP3_PRM_CLKSEL_OFFSET); 238 prcm_block_contents.cm_clksel_core = 239 cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 240 prcm_block_contents.cm_clksel_wkup = 241 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 242 prcm_block_contents.cm_clken_pll = 243 cm_read_mod_reg(PLL_MOD, CM_CLKEN); 244 prcm_block_contents.cm_autoidle_pll = 245 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); 246 prcm_block_contents.cm_clksel1_pll = 247 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); 248 prcm_block_contents.cm_clksel2_pll = 249 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); 250 prcm_block_contents.cm_clksel3_pll = 251 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); 252 prcm_block_contents.cm_clken_pll_mpu = 253 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); 254 prcm_block_contents.cm_autoidle_pll_mpu = 255 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); 256 prcm_block_contents.cm_clksel1_pll_mpu = 257 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); 258 prcm_block_contents.cm_clksel2_pll_mpu = 259 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); 260 prcm_block_contents.prcm_block_size = 0x0; 261 262 /* Populate the SDRC block contents */ 263 sdrc_block_contents.sysconfig = 264 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 265 sdrc_block_contents.cs_cfg = 266 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 267 sdrc_block_contents.sharing = 268 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 269 sdrc_block_contents.err_type = 270 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 271 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 272 sdrc_block_contents.dll_b_ctrl = 0x0; 273 /* 274 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 275 * be programed to issue automatic self refresh on timeout 276 * of AUTO_CNT = 1 prior to any transition to OFF mode. 277 */ 278 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 279 && (omap_rev() >= OMAP3430_REV_ES3_0)) 280 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 281 ~(SDRC_POWER_AUTOCOUNT_MASK| 282 SDRC_POWER_CLKCTRL_MASK)) | 283 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 284 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 285 else 286 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 287 288 sdrc_block_contents.cs_0 = 0x0; 289 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 290 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 291 sdrc_block_contents.emr_1_0 = 0x0; 292 sdrc_block_contents.emr_2_0 = 0x0; 293 sdrc_block_contents.emr_3_0 = 0x0; 294 sdrc_block_contents.actim_ctrla_0 = 295 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 296 sdrc_block_contents.actim_ctrlb_0 = 297 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 298 sdrc_block_contents.rfr_ctrl_0 = 299 sdrc_read_reg(SDRC_RFR_CTRL_0); 300 sdrc_block_contents.cs_1 = 0x0; 301 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 302 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 303 sdrc_block_contents.emr_1_1 = 0x0; 304 sdrc_block_contents.emr_2_1 = 0x0; 305 sdrc_block_contents.emr_3_1 = 0x0; 306 sdrc_block_contents.actim_ctrla_1 = 307 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 308 sdrc_block_contents.actim_ctrlb_1 = 309 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 310 sdrc_block_contents.rfr_ctrl_1 = 311 sdrc_read_reg(SDRC_RFR_CTRL_1); 312 sdrc_block_contents.dcdl_1_ctrl = 0x0; 313 sdrc_block_contents.dcdl_2_ctrl = 0x0; 314 sdrc_block_contents.flags = 0x0; 315 sdrc_block_contents.block_size = 0x0; 316 317 arm_context_addr = virt_to_phys(omap3_arm_context); 318 319 /* Copy all the contents to the scratchpad location */ 320 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 321 memcpy_toio(scratchpad_address, &scratchpad_contents, 322 sizeof(scratchpad_contents)); 323 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 324 memcpy_toio(scratchpad_address + 325 scratchpad_contents.prcm_block_offset, 326 &prcm_block_contents, sizeof(prcm_block_contents)); 327 memcpy_toio(scratchpad_address + 328 scratchpad_contents.sdrc_block_offset, 329 &sdrc_block_contents, sizeof(sdrc_block_contents)); 330 /* 331 * Copies the address of the location in SDRAM where ARM 332 * registers get saved during a MPU OFF transition. 333 */ 334 memcpy_toio(scratchpad_address + 335 scratchpad_contents.sdrc_block_offset + 336 sizeof(sdrc_block_contents), &arm_context_addr, 4); 337 } 338 339 void omap3_control_save_context(void) 340 { 341 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 342 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 343 control_context.mem_dftrw0 = 344 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 345 control_context.mem_dftrw1 = 346 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 347 control_context.msuspendmux_0 = 348 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 349 control_context.msuspendmux_1 = 350 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 351 control_context.msuspendmux_2 = 352 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 353 control_context.msuspendmux_3 = 354 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 355 control_context.msuspendmux_4 = 356 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 357 control_context.msuspendmux_5 = 358 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 359 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 360 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 361 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 362 control_context.iva2_bootaddr = 363 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 364 control_context.iva2_bootmod = 365 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 366 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 367 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 368 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 369 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 370 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 371 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 372 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 373 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 374 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 375 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 376 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 377 control_context.dss_dpll_spreading = 378 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 379 control_context.core_dpll_spreading = 380 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 381 control_context.per_dpll_spreading = 382 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 383 control_context.usbhost_dpll_spreading = 384 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 385 control_context.pbias_lite = 386 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 387 control_context.temp_sensor = 388 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 389 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 390 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 391 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 392 return; 393 } 394 395 void omap3_control_restore_context(void) 396 { 397 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 398 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 399 omap_ctrl_writel(control_context.mem_dftrw0, 400 OMAP343X_CONTROL_MEM_DFTRW0); 401 omap_ctrl_writel(control_context.mem_dftrw1, 402 OMAP343X_CONTROL_MEM_DFTRW1); 403 omap_ctrl_writel(control_context.msuspendmux_0, 404 OMAP2_CONTROL_MSUSPENDMUX_0); 405 omap_ctrl_writel(control_context.msuspendmux_1, 406 OMAP2_CONTROL_MSUSPENDMUX_1); 407 omap_ctrl_writel(control_context.msuspendmux_2, 408 OMAP2_CONTROL_MSUSPENDMUX_2); 409 omap_ctrl_writel(control_context.msuspendmux_3, 410 OMAP2_CONTROL_MSUSPENDMUX_3); 411 omap_ctrl_writel(control_context.msuspendmux_4, 412 OMAP2_CONTROL_MSUSPENDMUX_4); 413 omap_ctrl_writel(control_context.msuspendmux_5, 414 OMAP2_CONTROL_MSUSPENDMUX_5); 415 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 416 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 417 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 418 omap_ctrl_writel(control_context.iva2_bootaddr, 419 OMAP343X_CONTROL_IVA2_BOOTADDR); 420 omap_ctrl_writel(control_context.iva2_bootmod, 421 OMAP343X_CONTROL_IVA2_BOOTMOD); 422 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 423 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 424 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 425 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 426 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 427 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 428 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 429 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 430 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 431 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 432 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 433 omap_ctrl_writel(control_context.dss_dpll_spreading, 434 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 435 omap_ctrl_writel(control_context.core_dpll_spreading, 436 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 437 omap_ctrl_writel(control_context.per_dpll_spreading, 438 OMAP343X_CONTROL_PER_DPLL_SPREADING); 439 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 440 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 441 omap_ctrl_writel(control_context.pbias_lite, 442 OMAP343X_CONTROL_PBIAS_LITE); 443 omap_ctrl_writel(control_context.temp_sensor, 444 OMAP343X_CONTROL_TEMP_SENSOR); 445 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 446 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 447 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 448 return; 449 } 450 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 451