1 /* 2 * OMAP4 CM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 13 * or CM2 hardware modules. For example, the EMU_CM CM instance is in 14 * the PRM hardware module. What a mess... 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/io.h> 22 23 #include <plat/common.h> 24 25 #include "cm.h" 26 #include "cm1_44xx.h" 27 #include "cm2_44xx.h" 28 #include "cm44xx.h" 29 #include "cminst44xx.h" 30 #include "cm-regbits-34xx.h" 31 #include "cm-regbits-44xx.h" 32 #include "prcm44xx.h" 33 #include "prm44xx.h" 34 #include "prcm_mpu44xx.h" 35 36 /* 37 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 38 * 39 * 0x0 func: Module is fully functional, including OCP 40 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 41 * abortion 42 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 43 * using separate functional clock 44 * 0x3 disabled: Module is disabled and cannot be accessed 45 * 46 */ 47 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 48 #define CLKCTRL_IDLEST_INTRANSITION 0x1 49 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 50 #define CLKCTRL_IDLEST_DISABLED 0x3 51 52 static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { 53 [OMAP4430_INVALID_PRCM_PARTITION] = 0, 54 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, 55 [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, 56 [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, 57 [OMAP4430_SCRM_PARTITION] = 0, 58 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, 59 }; 60 61 /* Private functions */ 62 63 /** 64 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 65 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 66 * @inst: CM instance register offset (*_INST macro) 67 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 68 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 69 * 70 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 71 * bit 0. 72 */ 73 static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 74 { 75 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 76 v &= OMAP4430_IDLEST_MASK; 77 v >>= OMAP4430_IDLEST_SHIFT; 78 return v; 79 } 80 81 /** 82 * _is_module_ready - can module registers be accessed without causing an abort? 83 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 84 * @inst: CM instance register offset (*_INST macro) 85 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 86 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 87 * 88 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 89 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 90 */ 91 static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 92 { 93 u32 v; 94 95 v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs); 96 97 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 98 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 99 } 100 101 /* Public functions */ 102 103 /* Read a register in a CM instance */ 104 u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) 105 { 106 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 107 part == OMAP4430_INVALID_PRCM_PARTITION || 108 !_cm_bases[part]); 109 return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); 110 } 111 112 /* Write into a register in a CM instance */ 113 void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) 114 { 115 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 116 part == OMAP4430_INVALID_PRCM_PARTITION || 117 !_cm_bases[part]); 118 __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); 119 } 120 121 /* Read-modify-write a register in CM1. Caller must lock */ 122 u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, 123 s16 idx) 124 { 125 u32 v; 126 127 v = omap4_cminst_read_inst_reg(part, inst, idx); 128 v &= ~mask; 129 v |= bits; 130 omap4_cminst_write_inst_reg(v, part, inst, idx); 131 132 return v; 133 } 134 135 u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) 136 { 137 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 138 } 139 140 u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) 141 { 142 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 143 } 144 145 u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 146 { 147 u32 v; 148 149 v = omap4_cminst_read_inst_reg(part, inst, idx); 150 v &= mask; 151 v >>= __ffs(mask); 152 153 return v; 154 } 155 156 /* 157 * 158 */ 159 160 /** 161 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 162 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 163 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 164 * @inst: CM instance register offset (*_INST macro) 165 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 166 * 167 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 168 * will handle the shift itself. 169 */ 170 static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) 171 { 172 u32 v; 173 174 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 175 v &= ~OMAP4430_CLKTRCTRL_MASK; 176 v |= c << OMAP4430_CLKTRCTRL_SHIFT; 177 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 178 } 179 180 /** 181 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 182 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 183 * @inst: CM instance register offset (*_INST macro) 184 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 185 * 186 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 187 * is in hardware-supervised idle mode, or 0 otherwise. 188 */ 189 bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) 190 { 191 u32 v; 192 193 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 194 v &= OMAP4430_CLKTRCTRL_MASK; 195 v >>= OMAP4430_CLKTRCTRL_SHIFT; 196 197 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 198 } 199 200 /** 201 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 202 * @part: PRCM partition ID that the clockdomain registers exist in 203 * @inst: CM instance register offset (*_INST macro) 204 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 205 * 206 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 207 * hardware-supervised idle mode. No return value. 208 */ 209 void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) 210 { 211 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 212 } 213 214 /** 215 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 216 * @part: PRCM partition ID that the clockdomain registers exist in 217 * @inst: CM instance register offset (*_INST macro) 218 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 219 * 220 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 221 * software-supervised idle mode, i.e., controlled manually by the 222 * Linux OMAP clockdomain code. No return value. 223 */ 224 void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) 225 { 226 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 227 } 228 229 /** 230 * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle 231 * @part: PRCM partition ID that the clockdomain registers exist in 232 * @inst: CM instance register offset (*_INST macro) 233 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 234 * 235 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle 236 * No return value. 237 */ 238 void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs) 239 { 240 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 241 } 242 243 /** 244 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 245 * @part: PRCM partition ID that the clockdomain registers exist in 246 * @inst: CM instance register offset (*_INST macro) 247 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 248 * 249 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 250 * waking it up. No return value. 251 */ 252 void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) 253 { 254 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 255 } 256 257 /* 258 * 259 */ 260 261 /** 262 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 263 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 264 * @inst: CM instance register offset (*_INST macro) 265 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 266 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 267 * 268 * Wait for the module IDLEST to be functional. If the idle state is in any 269 * the non functional state (trans, idle or disabled), module and thus the 270 * sysconfig cannot be accessed and will probably lead to an "imprecise 271 * external abort" 272 */ 273 int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, 274 u16 clkctrl_offs) 275 { 276 int i = 0; 277 278 if (!clkctrl_offs) 279 return 0; 280 281 omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs), 282 MAX_MODULE_READY_TIME, i); 283 284 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 285 } 286 287 /** 288 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 289 * state 290 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 291 * @inst: CM instance register offset (*_INST macro) 292 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 293 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 294 * 295 * Wait for the module IDLEST to be disabled. Some PRCM transition, 296 * like reset assertion or parent clock de-activation must wait the 297 * module to be fully disabled. 298 */ 299 int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 300 { 301 int i = 0; 302 303 if (!clkctrl_offs) 304 return 0; 305 306 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == 307 CLKCTRL_IDLEST_DISABLED), 308 MAX_MODULE_READY_TIME, i); 309 310 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 311 } 312 313 /** 314 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 315 * @mode: Module mode (SW or HW) 316 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 317 * @inst: CM instance register offset (*_INST macro) 318 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 319 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 320 * 321 * No return value. 322 */ 323 void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 324 u16 clkctrl_offs) 325 { 326 u32 v; 327 328 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 329 v &= ~OMAP4430_MODULEMODE_MASK; 330 v |= mode << OMAP4430_MODULEMODE_SHIFT; 331 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 332 } 333 334 /** 335 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 336 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 337 * @inst: CM instance register offset (*_INST macro) 338 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 339 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 340 * 341 * No return value. 342 */ 343 void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 344 u16 clkctrl_offs) 345 { 346 u32 v; 347 348 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 349 v &= ~OMAP4430_MODULEMODE_MASK; 350 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 351 } 352