1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ff4ae5d9SPaul Walmsley /* 3ff4ae5d9SPaul Walmsley * OMAP2xxx Clock Management (CM) register definitions 4ff4ae5d9SPaul Walmsley * 5ff4ae5d9SPaul Walmsley * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. 6ff4ae5d9SPaul Walmsley * Copyright (C) 2007-2010 Nokia Corporation 7ff4ae5d9SPaul Walmsley * Paul Walmsley 8ff4ae5d9SPaul Walmsley * 9ff4ae5d9SPaul Walmsley * The CM hardware modules on the OMAP2/3 are quite similar to each 10ff4ae5d9SPaul Walmsley * other. The CM modules/instances on OMAP4 are quite different, so 11ff4ae5d9SPaul Walmsley * they are handled in a separate file. 12ff4ae5d9SPaul Walmsley */ 13ff4ae5d9SPaul Walmsley #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H 14ff4ae5d9SPaul Walmsley #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H 15ff4ae5d9SPaul Walmsley 16ff4ae5d9SPaul Walmsley #include "prcm-common.h" 17ff4ae5d9SPaul Walmsley #include "cm2xxx_3xxx.h" 18ff4ae5d9SPaul Walmsley 19ff4ae5d9SPaul Walmsley #define OMAP2420_CM_REGADDR(module, reg) \ 20ff4ae5d9SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 21ff4ae5d9SPaul Walmsley #define OMAP2430_CM_REGADDR(module, reg) \ 22ff4ae5d9SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 23ff4ae5d9SPaul Walmsley 24ff4ae5d9SPaul Walmsley /* 25ff4ae5d9SPaul Walmsley * Module specific CM register offsets from CM_BASE + domain offset 26ff4ae5d9SPaul Walmsley * Use cm_{read,write}_mod_reg() with these registers. 27ff4ae5d9SPaul Walmsley * These register offsets generally appear in more than one PRCM submodule. 28ff4ae5d9SPaul Walmsley */ 29ff4ae5d9SPaul Walmsley 30ff4ae5d9SPaul Walmsley /* OMAP2-specific register offsets */ 31ff4ae5d9SPaul Walmsley 32ff4ae5d9SPaul Walmsley #define OMAP24XX_CM_FCLKEN2 0x0004 33ff4ae5d9SPaul Walmsley #define OMAP24XX_CM_ICLKEN4 0x001c 34ff4ae5d9SPaul Walmsley #define OMAP24XX_CM_AUTOIDLE4 0x003c 35ff4ae5d9SPaul Walmsley #define OMAP24XX_CM_IDLEST4 0x002c 36ff4ae5d9SPaul Walmsley 37ff4ae5d9SPaul Walmsley /* CM_IDLEST bit field values to indicate deasserted IdleReq */ 38ff4ae5d9SPaul Walmsley 39ff4ae5d9SPaul Walmsley #define OMAP24XX_CM_IDLEST_VAL 0 40ff4ae5d9SPaul Walmsley 41ff4ae5d9SPaul Walmsley 42ff4ae5d9SPaul Walmsley /* Clock management domain register get/set */ 43ff4ae5d9SPaul Walmsley 44ff4ae5d9SPaul Walmsley #ifndef __ASSEMBLER__ 45ff4ae5d9SPaul Walmsley 46ff4ae5d9SPaul Walmsley extern void omap2xxx_cm_set_dpll_disable_autoidle(void); 47ff4ae5d9SPaul Walmsley extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); 48ff4ae5d9SPaul Walmsley 49cd6e9db2STero Kristo extern int omap2xxx_cm_fclks_active(void); 50cd6e9db2STero Kristo extern int omap2xxx_cm_mpu_retention_allowed(void); 51cd6e9db2STero Kristo extern u32 omap2xxx_cm_get_core_clk_src(void); 52cd6e9db2STero Kristo extern u32 omap2xxx_cm_get_core_pll_config(void); 53cd6e9db2STero Kristo extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, 54cd6e9db2STero Kristo u32 mdm); 55c4ceedcbSPaul Walmsley 56425dc8b2STero Kristo int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data); 57ff4ae5d9SPaul Walmsley 58ff4ae5d9SPaul Walmsley #endif 59ff4ae5d9SPaul Walmsley 60ff4ae5d9SPaul Walmsley #endif 61