1 /* 2 * linux/arch/arm/mach-omap2/clock.h 3 * 4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 5 * Copyright (C) 2004-2011 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H 18 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 22 #include <linux/clkdev.h> 23 #include <linux/clk-provider.h> 24 #include <linux/clk/ti.h> 25 26 struct omap_clk { 27 u16 cpu; 28 struct clk_lookup lk; 29 }; 30 31 #define CLK(dev, con, ck) \ 32 { \ 33 .lk = { \ 34 .dev_id = dev, \ 35 .con_id = con, \ 36 .clk = ck, \ 37 }, \ 38 } 39 40 struct clockdomain; 41 42 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ 43 static struct clk_core _name##_core = { \ 44 .name = #_name, \ 45 .hw = &_name##_hw.hw, \ 46 .parent_names = _parent_array_name, \ 47 .num_parents = ARRAY_SIZE(_parent_array_name), \ 48 .ops = &_clkops_name, \ 49 }; \ 50 static struct clk _name = { \ 51 .core = &_name##_core, \ 52 }; 53 54 #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ 55 _clkops_name, _flags) \ 56 static struct clk_core _name##_core = { \ 57 .name = #_name, \ 58 .hw = &_name##_hw.hw, \ 59 .parent_names = _parent_array_name, \ 60 .num_parents = ARRAY_SIZE(_parent_array_name), \ 61 .ops = &_clkops_name, \ 62 .flags = _flags, \ 63 }; \ 64 static struct clk _name = { \ 65 .core = &_name##_core, \ 66 }; 67 68 #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ 69 static struct clk_hw_omap _name##_hw = { \ 70 .hw = { \ 71 .clk = &_name, \ 72 }, \ 73 .clkdm_name = _clkdm_name, \ 74 }; 75 76 #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ 77 _clksel_reg, _clksel_mask, \ 78 _parent_names, _ops) \ 79 static struct clk _name; \ 80 static struct clk_hw_omap _name##_hw = { \ 81 .hw = { \ 82 .clk = &_name, \ 83 }, \ 84 .clksel = _clksel, \ 85 .clksel_reg = _clksel_reg, \ 86 .clksel_mask = _clksel_mask, \ 87 .clkdm_name = _clkdm_name, \ 88 }; \ 89 DEFINE_STRUCT_CLK(_name, _parent_names, _ops); 90 91 #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ 92 _clksel_reg, _clksel_mask, \ 93 _enable_reg, _enable_bit, \ 94 _hwops, _parent_names, _ops) \ 95 static struct clk _name; \ 96 static struct clk_hw_omap _name##_hw = { \ 97 .hw = { \ 98 .clk = &_name, \ 99 }, \ 100 .ops = _hwops, \ 101 .enable_reg = _enable_reg, \ 102 .enable_bit = _enable_bit, \ 103 .clksel = _clksel, \ 104 .clksel_reg = _clksel_reg, \ 105 .clksel_mask = _clksel_mask, \ 106 .clkdm_name = _clkdm_name, \ 107 }; \ 108 DEFINE_STRUCT_CLK(_name, _parent_names, _ops); 109 110 /* struct clksel_rate.flags possibilities */ 111 #define RATE_IN_242X (1 << 0) 112 #define RATE_IN_243X (1 << 1) 113 #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ 114 #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ 115 #define RATE_IN_36XX (1 << 4) 116 #define RATE_IN_4430 (1 << 5) 117 #define RATE_IN_TI816X (1 << 6) 118 #define RATE_IN_4460 (1 << 7) 119 #define RATE_IN_AM33XX (1 << 8) 120 #define RATE_IN_TI814X (1 << 9) 121 122 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 123 #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 124 #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 125 #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) 126 127 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 128 #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 129 130 131 /** 132 * struct clksel_rate - register bitfield values corresponding to clk divisors 133 * @val: register bitfield value (shifted to bit 0) 134 * @div: clock divisor corresponding to @val 135 * @flags: (see "struct clksel_rate.flags possibilities" above) 136 * 137 * @val should match the value of a read from struct clk.clksel_reg 138 * AND'ed with struct clk.clksel_mask, shifted right to bit 0. 139 * 140 * @div is the divisor that should be applied to the parent clock's rate 141 * to produce the current clock's rate. 142 */ 143 struct clksel_rate { 144 u32 val; 145 u8 div; 146 u16 flags; 147 }; 148 149 /** 150 * struct clksel - available parent clocks, and a pointer to their divisors 151 * @parent: struct clk * to a possible parent clock 152 * @rates: available divisors for this parent clock 153 * 154 * A struct clksel is always associated with one or more struct clks 155 * and one or more struct clksel_rates. 156 */ 157 struct clksel { 158 struct clk *parent; 159 const struct clksel_rate *rates; 160 }; 161 162 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 163 #define CORE_CLK_SRC_32K 0x0 164 #define CORE_CLK_SRC_DPLL 0x1 165 #define CORE_CLK_SRC_DPLL_X2 0x2 166 167 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ 168 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 169 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 170 #define OMAP2XXX_EN_DPLL_LOCKED 0x3 171 172 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 173 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 174 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 175 #define OMAP3XXX_EN_DPLL_LOCKED 0x7 176 177 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 178 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 179 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 180 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 181 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 182 183 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); 184 void omap3_dpll_allow_idle(struct clk_hw_omap *clk); 185 void omap3_dpll_deny_idle(struct clk_hw_omap *clk); 186 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); 187 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); 188 189 void __init omap2_clk_disable_clkdm_control(void); 190 191 /* clkt_clksel.c public functions */ 192 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, 193 unsigned long target_rate, 194 u32 *new_div); 195 u8 omap2_clksel_find_parent_index(struct clk_hw *hw); 196 unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); 197 long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, 198 unsigned long *parent_rate); 199 int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, 200 unsigned long parent_rate); 201 int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); 202 203 /* clkt_iclk.c public functions */ 204 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 205 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 206 207 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); 208 209 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 210 void __iomem **other_reg, 211 u8 *other_bit); 212 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 213 void __iomem **idlest_reg, 214 u8 *idlest_bit, u8 *idlest_val); 215 int omap2_clk_enable_autoidle_all(void); 216 int omap2_clk_allow_idle(struct clk *clk); 217 int omap2_clk_deny_idle(struct clk *clk); 218 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 219 void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 220 const char *core_ck_name, 221 const char *mpu_ck_name); 222 223 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg); 224 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); 225 226 extern u16 cpu_mask; 227 228 /* 229 * Clock features setup. Used instead of CPU type checks. 230 */ 231 struct ti_clk_features { 232 u32 flags; 233 long fint_min; 234 long fint_max; 235 long fint_band1_max; 236 long fint_band2_min; 237 u8 dpll_bypass_vals; 238 u8 cm_idlest_val; 239 }; 240 241 #define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) 242 #define TI_CLK_DPLL4_DENY_REPROGRAM (1 << 1) 243 244 extern struct ti_clk_features ti_clk_features; 245 246 extern const struct clkops clkops_omap2_dflt_wait; 247 extern const struct clkops clkops_omap2_dflt; 248 249 extern struct clk_functions omap2_clk_functions; 250 251 extern const struct clksel_rate gpt_32k_rates[]; 252 extern const struct clksel_rate gpt_sys_rates[]; 253 extern const struct clksel_rate gfx_l3_rates[]; 254 extern const struct clksel_rate dsp_ick_rates[]; 255 256 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 257 extern const struct clk_hw_omap_ops clkhwops_wait; 258 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; 259 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 260 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; 261 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 262 extern const struct clk_hw_omap_ops clkhwops_apll54; 263 extern const struct clk_hw_omap_ops clkhwops_apll96; 264 265 /* clksel_rate blocks shared between OMAP44xx and AM33xx */ 266 extern const struct clksel_rate div_1_0_rates[]; 267 extern const struct clksel_rate div3_1to4_rates[]; 268 extern const struct clksel_rate div_1_1_rates[]; 269 extern const struct clksel_rate div_1_2_rates[]; 270 extern const struct clksel_rate div_1_3_rates[]; 271 extern const struct clksel_rate div_1_4_rates[]; 272 extern const struct clksel_rate div31_1to31_rates[]; 273 274 extern void __iomem *clk_memmaps[]; 275 276 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 277 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 278 279 void __init ti_clk_init_features(void); 280 #endif 281