1 /* 2 * linux/arch/arm/mach-omap2/clock.h 3 * 4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 5 * Copyright (C) 2004-2011 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H 18 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 22 #include <linux/clkdev.h> 23 #include <linux/clk-provider.h> 24 25 struct omap_clk { 26 u16 cpu; 27 struct clk_lookup lk; 28 }; 29 30 #define CLK(dev, con, ck, cp) \ 31 { \ 32 .cpu = cp, \ 33 .lk = { \ 34 .dev_id = dev, \ 35 .con_id = con, \ 36 .clk = ck, \ 37 }, \ 38 } 39 40 /* Platform flags for the clkdev-OMAP integration code */ 41 #define CK_242X (1 << 0) 42 #define CK_243X (1 << 1) /* 243x, 253x */ 43 #define CK_3430ES1 (1 << 2) /* 34xxES1 only */ 44 #define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */ 45 #define CK_AM35XX (1 << 4) /* Sitara AM35xx */ 46 #define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */ 47 #define CK_443X (1 << 6) 48 #define CK_TI816X (1 << 7) 49 #define CK_446X (1 << 8) 50 #define CK_AM33XX (1 << 9) /* AM33xx specific clocks */ 51 52 53 #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 54 #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) 55 56 struct clockdomain; 57 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 58 59 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ 60 static struct clk _name = { \ 61 .name = #_name, \ 62 .hw = &_name##_hw.hw, \ 63 .parent_names = _parent_array_name, \ 64 .num_parents = ARRAY_SIZE(_parent_array_name), \ 65 .ops = &_clkops_name, \ 66 }; 67 68 #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ 69 static struct clk_hw_omap _name##_hw = { \ 70 .hw = { \ 71 .clk = &_name, \ 72 }, \ 73 .clkdm_name = _clkdm_name, \ 74 }; 75 76 #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ 77 _clksel_reg, _clksel_mask, \ 78 _parent_names, _ops) \ 79 static struct clk _name; \ 80 static struct clk_hw_omap _name##_hw = { \ 81 .hw = { \ 82 .clk = &_name, \ 83 }, \ 84 .clksel = _clksel, \ 85 .clksel_reg = _clksel_reg, \ 86 .clksel_mask = _clksel_mask, \ 87 .clkdm_name = _clkdm_name, \ 88 }; \ 89 DEFINE_STRUCT_CLK(_name, _parent_names, _ops); 90 91 #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ 92 _clksel_reg, _clksel_mask, \ 93 _enable_reg, _enable_bit, \ 94 _hwops, _parent_names, _ops) \ 95 static struct clk _name; \ 96 static struct clk_hw_omap _name##_hw = { \ 97 .hw = { \ 98 .clk = &_name, \ 99 }, \ 100 .ops = _hwops, \ 101 .enable_reg = _enable_reg, \ 102 .enable_bit = _enable_bit, \ 103 .clksel = _clksel, \ 104 .clksel_reg = _clksel_reg, \ 105 .clksel_mask = _clksel_mask, \ 106 .clkdm_name = _clkdm_name, \ 107 }; \ 108 DEFINE_STRUCT_CLK(_name, _parent_names, _ops); 109 110 #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ 111 _parent_ptr, _flags, \ 112 _clksel_reg, _clksel_mask) \ 113 static const struct clksel _name##_div[] = { \ 114 { \ 115 .parent = _parent_ptr, \ 116 .rates = div31_1to31_rates \ 117 }, \ 118 { .parent = NULL }, \ 119 }; \ 120 static struct clk _name; \ 121 static const char *_name##_parent_names[] = { \ 122 _parent_name, \ 123 }; \ 124 static struct clk_hw_omap _name##_hw = { \ 125 .hw = { \ 126 .clk = &_name, \ 127 }, \ 128 .clksel = _name##_div, \ 129 .clksel_reg = _clksel_reg, \ 130 .clksel_mask = _clksel_mask, \ 131 .ops = &clkhwops_omap4_dpllmx, \ 132 }; \ 133 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); 134 135 /* struct clksel_rate.flags possibilities */ 136 #define RATE_IN_242X (1 << 0) 137 #define RATE_IN_243X (1 << 1) 138 #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ 139 #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ 140 #define RATE_IN_36XX (1 << 4) 141 #define RATE_IN_4430 (1 << 5) 142 #define RATE_IN_TI816X (1 << 6) 143 #define RATE_IN_4460 (1 << 7) 144 #define RATE_IN_AM33XX (1 << 8) 145 #define RATE_IN_TI814X (1 << 9) 146 147 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 148 #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 149 #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 150 #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) 151 152 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 153 #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 154 155 156 /** 157 * struct clksel_rate - register bitfield values corresponding to clk divisors 158 * @val: register bitfield value (shifted to bit 0) 159 * @div: clock divisor corresponding to @val 160 * @flags: (see "struct clksel_rate.flags possibilities" above) 161 * 162 * @val should match the value of a read from struct clk.clksel_reg 163 * AND'ed with struct clk.clksel_mask, shifted right to bit 0. 164 * 165 * @div is the divisor that should be applied to the parent clock's rate 166 * to produce the current clock's rate. 167 */ 168 struct clksel_rate { 169 u32 val; 170 u8 div; 171 u16 flags; 172 }; 173 174 /** 175 * struct clksel - available parent clocks, and a pointer to their divisors 176 * @parent: struct clk * to a possible parent clock 177 * @rates: available divisors for this parent clock 178 * 179 * A struct clksel is always associated with one or more struct clks 180 * and one or more struct clksel_rates. 181 */ 182 struct clksel { 183 struct clk *parent; 184 const struct clksel_rate *rates; 185 }; 186 187 /** 188 * struct dpll_data - DPLL registers and integration data 189 * @mult_div1_reg: register containing the DPLL M and N bitfields 190 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg 191 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg 192 * @clk_bypass: struct clk pointer to the clock's bypass clock input 193 * @clk_ref: struct clk pointer to the clock's reference clock input 194 * @control_reg: register containing the DPLL mode bitfield 195 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 196 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 197 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 198 * @last_rounded_m4xen: cache of the last M4X result of 199 * omap4_dpll_regm4xen_round_rate() 200 * @last_rounded_lpmode: cache of the last lpmode result of 201 * omap4_dpll_lpmode_recalc() 202 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 203 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() 204 * @min_divider: minimum valid non-bypass divider value (actual) 205 * @max_divider: maximum valid non-bypass divider value (actual) 206 * @modes: possible values of @enable_mask 207 * @autoidle_reg: register containing the DPLL autoidle mode bitfield 208 * @idlest_reg: register containing the DPLL idle status bitfield 209 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg 210 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg 211 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg 212 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg 213 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg 214 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg 215 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs 216 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs 217 * @flags: DPLL type/features (see below) 218 * 219 * Possible values for @flags: 220 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) 221 * 222 * @freqsel_mask is only used on the OMAP34xx family and AM35xx. 223 * 224 * XXX Some DPLLs have multiple bypass inputs, so it's not technically 225 * correct to only have one @clk_bypass pointer. 226 * 227 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, 228 * @last_rounded_n) should be separated from the runtime-fixed fields 229 * and placed into a different structure, so that the runtime-fixed data 230 * can be placed into read-only space. 231 */ 232 struct dpll_data { 233 void __iomem *mult_div1_reg; 234 u32 mult_mask; 235 u32 div1_mask; 236 struct clk *clk_bypass; 237 struct clk *clk_ref; 238 void __iomem *control_reg; 239 u32 enable_mask; 240 unsigned long last_rounded_rate; 241 u16 last_rounded_m; 242 u8 last_rounded_m4xen; 243 u8 last_rounded_lpmode; 244 u16 max_multiplier; 245 u8 last_rounded_n; 246 u8 min_divider; 247 u16 max_divider; 248 u8 modes; 249 void __iomem *autoidle_reg; 250 void __iomem *idlest_reg; 251 u32 autoidle_mask; 252 u32 freqsel_mask; 253 u32 idlest_mask; 254 u32 dco_mask; 255 u32 sddiv_mask; 256 u32 lpmode_mask; 257 u32 m4xen_mask; 258 u8 auto_recal_bit; 259 u8 recal_en_bit; 260 u8 recal_st_bit; 261 u8 flags; 262 }; 263 264 /* 265 * struct clk.flags possibilities 266 * 267 * XXX document the rest of the clock flags here 268 * 269 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL 270 * bits share the same register. This flag allows the 271 * omap4_dpllmx*() code to determine which GATE_CTRL bit field 272 * should be used. This is a temporary solution - a better approach 273 * would be to associate clock type-specific data with the clock, 274 * similar to the struct dpll_data approach. 275 */ 276 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ 277 #define CLOCK_IDLE_CONTROL (1 << 1) 278 #define CLOCK_NO_IDLE_PARENT (1 << 2) 279 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ 280 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 281 #define CLOCK_CLKOUTX2 (1 << 5) 282 283 /** 284 * struct clk_hw_omap - OMAP struct clk 285 * @node: list_head connecting this clock into the full clock list 286 * @enable_reg: register to write to enable the clock (see @enable_bit) 287 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) 288 * @flags: see "struct clk.flags possibilities" above 289 * @clksel_reg: for clksel clks, register va containing src/divisor select 290 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector 291 * @clksel: for clksel clks, pointer to struct clksel for this clock 292 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock 293 * @clkdm_name: clockdomain name that this clock is contained in 294 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime 295 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) 296 * @src_offset: bitshift for source selection bitfield (OMAP1 only) 297 * 298 * XXX @rate_offset, @src_offset should probably be removed and OMAP1 299 * clock code converted to use clksel. 300 * 301 */ 302 303 struct clk_hw_omap_ops; 304 305 struct clk_hw_omap { 306 struct clk_hw hw; 307 struct list_head node; 308 unsigned long fixed_rate; 309 u8 fixed_div; 310 void __iomem *enable_reg; 311 u8 enable_bit; 312 u8 flags; 313 void __iomem *clksel_reg; 314 u32 clksel_mask; 315 const struct clksel *clksel; 316 struct dpll_data *dpll_data; 317 const char *clkdm_name; 318 struct clockdomain *clkdm; 319 const struct clk_hw_omap_ops *ops; 320 }; 321 322 struct clk_hw_omap_ops { 323 void (*find_idlest)(struct clk_hw_omap *oclk, 324 void __iomem **idlest_reg, 325 u8 *idlest_bit, u8 *idlest_val); 326 void (*find_companion)(struct clk_hw_omap *oclk, 327 void __iomem **other_reg, 328 u8 *other_bit); 329 void (*allow_idle)(struct clk_hw_omap *oclk); 330 void (*deny_idle)(struct clk_hw_omap *oclk); 331 }; 332 333 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 334 unsigned long parent_rate); 335 336 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 337 #define CORE_CLK_SRC_32K 0x0 338 #define CORE_CLK_SRC_DPLL 0x1 339 #define CORE_CLK_SRC_DPLL_X2 0x2 340 341 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ 342 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 343 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 344 #define OMAP2XXX_EN_DPLL_LOCKED 0x3 345 346 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 347 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 348 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 349 #define OMAP3XXX_EN_DPLL_LOCKED 0x7 350 351 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 352 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 353 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 354 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 355 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 356 357 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 358 #define DPLL_LOW_POWER_STOP 0x1 359 #define DPLL_LOW_POWER_BYPASS 0x5 360 #define DPLL_LOCKED 0x7 361 362 /* DPLL Type and DCO Selection Flags */ 363 #define DPLL_J_TYPE 0x1 364 365 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 366 unsigned long *parent_rate); 367 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 368 int omap3_noncore_dpll_enable(struct clk_hw *hw); 369 void omap3_noncore_dpll_disable(struct clk_hw *hw); 370 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 371 unsigned long parent_rate); 372 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); 373 void omap3_dpll_allow_idle(struct clk_hw_omap *clk); 374 void omap3_dpll_deny_idle(struct clk_hw_omap *clk); 375 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 376 unsigned long parent_rate); 377 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); 378 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); 379 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); 380 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 381 unsigned long parent_rate); 382 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 383 unsigned long target_rate, 384 unsigned long *parent_rate); 385 386 void omap2_init_clk_clkdm(struct clk_hw *clk); 387 void __init omap2_clk_disable_clkdm_control(void); 388 389 /* clkt_clksel.c public functions */ 390 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, 391 unsigned long target_rate, 392 u32 *new_div); 393 u8 omap2_clksel_find_parent_index(struct clk_hw *hw); 394 unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); 395 long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, 396 unsigned long *parent_rate); 397 int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, 398 unsigned long parent_rate); 399 int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); 400 401 /* clkt_iclk.c public functions */ 402 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 403 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 404 405 u8 omap2_init_dpll_parent(struct clk_hw *hw); 406 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); 407 408 int omap2_dflt_clk_enable(struct clk_hw *hw); 409 void omap2_dflt_clk_disable(struct clk_hw *hw); 410 int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 411 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 412 void __iomem **other_reg, 413 u8 *other_bit); 414 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 415 void __iomem **idlest_reg, 416 u8 *idlest_bit, u8 *idlest_val); 417 void omap2_init_clk_hw_omap_clocks(struct clk *clk); 418 int omap2_clk_enable_autoidle_all(void); 419 int omap2_clk_disable_autoidle_all(void); 420 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 421 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 422 void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 423 const char *core_ck_name, 424 const char *mpu_ck_name); 425 426 extern u16 cpu_mask; 427 428 extern const struct clkops clkops_omap2_dflt_wait; 429 extern const struct clkops clkops_dummy; 430 extern const struct clkops clkops_omap2_dflt; 431 432 extern struct clk_functions omap2_clk_functions; 433 434 extern const struct clksel_rate gpt_32k_rates[]; 435 extern const struct clksel_rate gpt_sys_rates[]; 436 extern const struct clksel_rate gfx_l3_rates[]; 437 extern const struct clksel_rate dsp_ick_rates[]; 438 extern struct clk dummy_ck; 439 440 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 441 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 442 extern const struct clk_hw_omap_ops clkhwops_wait; 443 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 444 extern const struct clk_hw_omap_ops clkhwops_iclk; 445 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; 446 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 447 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 448 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 449 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 450 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; 451 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 452 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 453 extern const struct clk_hw_omap_ops clkhwops_apll54; 454 extern const struct clk_hw_omap_ops clkhwops_apll96; 455 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; 456 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 457 458 /* clksel_rate blocks shared between OMAP44xx and AM33xx */ 459 extern const struct clksel_rate div_1_0_rates[]; 460 extern const struct clksel_rate div3_1to4_rates[]; 461 extern const struct clksel_rate div_1_1_rates[]; 462 extern const struct clksel_rate div_1_2_rates[]; 463 extern const struct clksel_rate div_1_3_rates[]; 464 extern const struct clksel_rate div_1_4_rates[]; 465 extern const struct clksel_rate div31_1to31_rates[]; 466 467 extern int am33xx_clk_init(void); 468 469 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 470 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 471 472 #endif 473