1 /* 2 * DPLL + CORE_CLK composite clock functions 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, 12 * Gordon McNutt and RidgeRun, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * XXX The DPLL and CORE clocks should be split into two separate clock 19 * types. 20 */ 21 #undef DEBUG 22 23 #include <linux/kernel.h> 24 #include <linux/errno.h> 25 #include <linux/clk.h> 26 #include <linux/io.h> 27 28 #include "clock.h" 29 #include "clock2xxx.h" 30 #include "opp2xxx.h" 31 #include "cm2xxx.h" 32 #include "cm-regbits-24xx.h" 33 #include "sdrc.h" 34 #include "sram.h" 35 36 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ 37 38 /* 39 * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx 40 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set 41 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). 42 */ 43 static struct clk_hw_omap *dpll_core_ck; 44 45 /** 46 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 47 * 48 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate 49 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz 50 * (the latter is unusual). This currently should be called with 51 * struct clk *dpll_ck, which is a composite clock of dpll_ck and 52 * core_ck. 53 */ 54 unsigned long omap2xxx_clk_get_core_rate(void) 55 { 56 long long core_clk; 57 u32 v; 58 59 WARN_ON(!dpll_core_ck); 60 61 core_clk = omap2_get_dpll_rate(dpll_core_ck); 62 63 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 64 v &= OMAP24XX_CORE_CLK_SRC_MASK; 65 66 if (v == CORE_CLK_SRC_32K) 67 core_clk = 32768; 68 else 69 core_clk *= v; 70 71 return core_clk; 72 } 73 74 /* 75 * Uses the current prcm set to tell if a rate is valid. 76 * You can go slower, but not faster within a given rate set. 77 */ 78 static long omap2_dpllcore_round_rate(unsigned long target_rate) 79 { 80 u32 high, low, core_clk_src; 81 82 core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 83 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; 84 85 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ 86 high = curr_prcm_set->dpll_speed * 2; 87 low = curr_prcm_set->dpll_speed; 88 } else { /* DPLL clockout x 2 */ 89 high = curr_prcm_set->dpll_speed; 90 low = curr_prcm_set->dpll_speed / 2; 91 } 92 93 #ifdef DOWN_VARIABLE_DPLL 94 if (target_rate > high) 95 return high; 96 else 97 return target_rate; 98 #else 99 if (target_rate > low) 100 return high; 101 else 102 return low; 103 #endif 104 105 } 106 107 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, 108 unsigned long parent_rate) 109 { 110 return omap2xxx_clk_get_core_rate(); 111 } 112 113 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, 114 unsigned long parent_rate) 115 { 116 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 117 u32 cur_rate, low, mult, div, valid_rate, done_rate; 118 u32 bypass = 0; 119 struct prcm_config tmpset; 120 const struct dpll_data *dd; 121 122 cur_rate = omap2xxx_clk_get_core_rate(); 123 mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 124 mult &= OMAP24XX_CORE_CLK_SRC_MASK; 125 126 if ((rate == (cur_rate / 2)) && (mult == 2)) { 127 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); 128 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 129 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 130 } else if (rate != cur_rate) { 131 valid_rate = omap2_dpllcore_round_rate(rate); 132 if (valid_rate != rate) 133 return -EINVAL; 134 135 if (mult == 1) 136 low = curr_prcm_set->dpll_speed; 137 else 138 low = curr_prcm_set->dpll_speed / 2; 139 140 dd = clk->dpll_data; 141 if (!dd) 142 return -EINVAL; 143 144 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); 145 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 146 dd->div1_mask); 147 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 148 tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 149 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; 150 if (rate > low) { 151 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; 152 mult = ((rate / 2) / 1000000); 153 done_rate = CORE_CLK_SRC_DPLL_X2; 154 } else { 155 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; 156 mult = (rate / 1000000); 157 done_rate = CORE_CLK_SRC_DPLL; 158 } 159 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); 160 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); 161 162 /* Worst case */ 163 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; 164 165 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ 166 bypass = 1; 167 168 /* For omap2xxx_sdrc_init_params() */ 169 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 170 171 /* Force dll lock mode */ 172 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, 173 bypass); 174 175 /* Errata: ret dll entry state */ 176 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); 177 omap2xxx_sdrc_reprogram(done_rate, 0); 178 } 179 180 return 0; 181 } 182 183 /** 184 * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck 185 * @clk: struct clk *dpll_ck 186 * 187 * Store a local copy of @clk in dpll_core_ck so other code can query 188 * the core rate without having to clk_get(), which can sleep. Must 189 * only be called once. No return value. XXX If the clock 190 * registration process is ever changed such that dpll_ck is no longer 191 * statically defined, this code may need to change to increment some 192 * kind of use count on dpll_ck. 193 */ 194 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) 195 { 196 WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); 197 dpll_core_ck = to_clk_hw_omap(hw); 198 } 199