1 /* 2 * linux/arch/arm/mach-omap1/time.c 3 * 4 * OMAP Timers 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Partial timer rewrite and additional dynamic tick timer support by 8 * Tony Lindgen <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 10 * 11 * MPU timer code based on the older MPU timer code for OMAP 12 * Copyright (C) 2000 RidgeRun, Inc. 13 * Author: Greg Lonnon <glonnon@ridgerun.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * You should have received a copy of the GNU General Public License along 32 * with this program; if not, write to the Free Software Foundation, Inc., 33 * 675 Mass Ave, Cambridge, MA 02139, USA. 34 */ 35 36 #include <linux/config.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/sched.h> 42 #include <linux/spinlock.h> 43 44 #include <asm/system.h> 45 #include <asm/hardware.h> 46 #include <asm/io.h> 47 #include <asm/leds.h> 48 #include <asm/irq.h> 49 #include <asm/mach/irq.h> 50 #include <asm/mach/time.h> 51 52 struct sys_timer omap_timer; 53 54 /* 55 * --------------------------------------------------------------------------- 56 * MPU timer 57 * --------------------------------------------------------------------------- 58 */ 59 #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE 60 #define OMAP_MPU_TIMER_OFFSET 0x100 61 62 /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c, 63 * converted to use kHz by Kevin Hilman */ 64 /* convert from cycles(64bits) => nanoseconds (64bits) 65 * basic equation: 66 * ns = cycles / (freq / ns_per_sec) 67 * ns = cycles * (ns_per_sec / freq) 68 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 69 * ns = cycles * (10^6 / cpu_khz) 70 * 71 * Then we use scaling math (suggested by george at mvista.com) to get: 72 * ns = cycles * (10^6 * SC / cpu_khz / SC 73 * ns = cycles * cyc2ns_scale / SC 74 * 75 * And since SC is a constant power of two, we can convert the div 76 * into a shift. 77 * -johnstul at us.ibm.com "math is hard, lets go shopping!" 78 */ 79 static unsigned long cyc2ns_scale; 80 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ 81 82 static inline void set_cyc2ns_scale(unsigned long cpu_khz) 83 { 84 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz; 85 } 86 87 static inline unsigned long long cycles_2_ns(unsigned long long cyc) 88 { 89 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; 90 } 91 92 /* 93 * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs 94 * will break. On P2, the timer count rate is 6.5 MHz after programming PTV 95 * with 0. This divides the 13MHz input by 2, and is undocumented. 96 */ 97 #ifdef CONFIG_MACH_OMAP_PERSEUS2 98 /* REVISIT: This ifdef construct should be replaced by a query to clock 99 * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz. 100 */ 101 #define MPU_TICKS_PER_SEC (13000000 / 2) 102 #else 103 #define MPU_TICKS_PER_SEC (12000000 / 2) 104 #endif 105 106 #define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1) 107 108 typedef struct { 109 u32 cntl; /* CNTL_TIMER, R/W */ 110 u32 load_tim; /* LOAD_TIM, W */ 111 u32 read_tim; /* READ_TIM, R */ 112 } omap_mpu_timer_regs_t; 113 114 #define omap_mpu_timer_base(n) \ 115 ((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ 116 (n)*OMAP_MPU_TIMER_OFFSET)) 117 118 static inline unsigned long omap_mpu_timer_read(int nr) 119 { 120 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 121 return timer->read_tim; 122 } 123 124 static inline void omap_mpu_timer_start(int nr, unsigned long load_val) 125 { 126 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 127 128 timer->cntl = MPU_TIMER_CLOCK_ENABLE; 129 udelay(1); 130 timer->load_tim = load_val; 131 udelay(1); 132 timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST); 133 } 134 135 unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks) 136 { 137 unsigned long long nsec; 138 139 nsec = cycles_2_ns((unsigned long long)nr_ticks); 140 return (unsigned long)nsec / 1000; 141 } 142 143 /* 144 * Last processed system timer interrupt 145 */ 146 static unsigned long omap_mpu_timer_last = 0; 147 148 /* 149 * Returns elapsed usecs since last system timer interrupt 150 */ 151 static unsigned long omap_mpu_timer_gettimeoffset(void) 152 { 153 unsigned long now = 0 - omap_mpu_timer_read(0); 154 unsigned long elapsed = now - omap_mpu_timer_last; 155 156 return omap_mpu_timer_ticks_to_usecs(elapsed); 157 } 158 159 /* 160 * Elapsed time between interrupts is calculated using timer0. 161 * Latency during the interrupt is calculated using timer1. 162 * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz). 163 */ 164 static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id, 165 struct pt_regs *regs) 166 { 167 unsigned long now, latency; 168 169 write_seqlock(&xtime_lock); 170 now = 0 - omap_mpu_timer_read(0); 171 latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1); 172 omap_mpu_timer_last = now - latency; 173 timer_tick(regs); 174 write_sequnlock(&xtime_lock); 175 176 return IRQ_HANDLED; 177 } 178 179 static struct irqaction omap_mpu_timer_irq = { 180 .name = "mpu timer", 181 .flags = SA_INTERRUPT | SA_TIMER, 182 .handler = omap_mpu_timer_interrupt, 183 }; 184 185 static unsigned long omap_mpu_timer1_overflows; 186 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id, 187 struct pt_regs *regs) 188 { 189 omap_mpu_timer1_overflows++; 190 return IRQ_HANDLED; 191 } 192 193 static struct irqaction omap_mpu_timer1_irq = { 194 .name = "mpu timer1 overflow", 195 .flags = SA_INTERRUPT, 196 .handler = omap_mpu_timer1_interrupt, 197 }; 198 199 static __init void omap_init_mpu_timer(void) 200 { 201 set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000); 202 omap_timer.offset = omap_mpu_timer_gettimeoffset; 203 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); 204 setup_irq(INT_TIMER2, &omap_mpu_timer_irq); 205 omap_mpu_timer_start(0, 0xffffffff); 206 omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD); 207 } 208 209 /* 210 * Scheduler clock - returns current time in nanosec units. 211 */ 212 unsigned long long sched_clock(void) 213 { 214 unsigned long ticks = 0 - omap_mpu_timer_read(0); 215 unsigned long long ticks64; 216 217 ticks64 = omap_mpu_timer1_overflows; 218 ticks64 <<= 32; 219 ticks64 |= ticks; 220 221 return cycles_2_ns(ticks64); 222 } 223 224 /* 225 * --------------------------------------------------------------------------- 226 * Timer initialization 227 * --------------------------------------------------------------------------- 228 */ 229 static void __init omap_timer_init(void) 230 { 231 omap_init_mpu_timer(); 232 } 233 234 struct sys_timer omap_timer = { 235 .init = omap_timer_init, 236 .offset = NULL, /* Initialized later */ 237 }; 238