1 /* 2 * linux/arch/arm/mach-omap1/serial.c 3 * 4 * OMAP1 serial support. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/delay.h> 16 #include <linux/serial.h> 17 #include <linux/tty.h> 18 #include <linux/serial_8250.h> 19 #include <linux/serial_reg.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 23 #include <asm/mach-types.h> 24 25 #include <mach/board.h> 26 #include <mach/mux.h> 27 #include <mach/gpio.h> 28 #include <mach/fpga.h> 29 30 static struct clk * uart1_ck; 31 static struct clk * uart2_ck; 32 static struct clk * uart3_ck; 33 34 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up, 35 int offset) 36 { 37 offset <<= up->regshift; 38 return (unsigned int)__raw_readb(up->membase + offset); 39 } 40 41 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset, 42 int value) 43 { 44 offset <<= p->regshift; 45 __raw_writeb(value, p->membase + offset); 46 } 47 48 /* 49 * Internal UARTs need to be initialized for the 8250 autoconfig to work 50 * properly. Note that the TX watermark initialization may not be needed 51 * once the 8250.c watermark handling code is merged. 52 */ 53 static void __init omap_serial_reset(struct plat_serial8250_port *p) 54 { 55 omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */ 56 omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ 57 omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */ 58 59 if (!cpu_is_omap15xx()) { 60 omap_serial_outp(p, UART_OMAP_SYSC, 0x01); 61 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01)); 62 } 63 } 64 65 static struct plat_serial8250_port serial_platform_data[] = { 66 { 67 .membase = IO_ADDRESS(OMAP_UART1_BASE), 68 .mapbase = OMAP_UART1_BASE, 69 .irq = INT_UART1, 70 .flags = UPF_BOOT_AUTOCONF, 71 .iotype = UPIO_MEM, 72 .regshift = 2, 73 .uartclk = OMAP16XX_BASE_BAUD * 16, 74 }, 75 { 76 .membase = IO_ADDRESS(OMAP_UART2_BASE), 77 .mapbase = OMAP_UART2_BASE, 78 .irq = INT_UART2, 79 .flags = UPF_BOOT_AUTOCONF, 80 .iotype = UPIO_MEM, 81 .regshift = 2, 82 .uartclk = OMAP16XX_BASE_BAUD * 16, 83 }, 84 { 85 .membase = IO_ADDRESS(OMAP_UART3_BASE), 86 .mapbase = OMAP_UART3_BASE, 87 .irq = INT_UART3, 88 .flags = UPF_BOOT_AUTOCONF, 89 .iotype = UPIO_MEM, 90 .regshift = 2, 91 .uartclk = OMAP16XX_BASE_BAUD * 16, 92 }, 93 { }, 94 }; 95 96 static struct platform_device serial_device = { 97 .name = "serial8250", 98 .id = PLAT8250_DEV_PLATFORM, 99 .dev = { 100 .platform_data = serial_platform_data, 101 }, 102 }; 103 104 /* 105 * Note that on Innovator-1510 UART2 pins conflict with USB2. 106 * By default UART2 does not work on Innovator-1510 if you have 107 * USB OHCI enabled. To use UART2, you must disable USB2 first. 108 */ 109 void __init omap_serial_init(void) 110 { 111 int i; 112 const struct omap_uart_config *info; 113 114 if (cpu_is_omap730()) { 115 serial_platform_data[0].regshift = 0; 116 serial_platform_data[1].regshift = 0; 117 serial_platform_data[0].irq = INT_730_UART_MODEM_1; 118 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; 119 } 120 121 if (cpu_is_omap850()) { 122 serial_platform_data[0].regshift = 0; 123 serial_platform_data[1].regshift = 0; 124 serial_platform_data[0].irq = INT_850_UART_MODEM_1; 125 serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; 126 } 127 128 if (cpu_is_omap15xx()) { 129 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; 130 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; 131 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; 132 } 133 134 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); 135 if (info == NULL) 136 return; 137 138 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { 139 unsigned char reg; 140 141 if (!((1 << i) & info->enabled_uarts)) { 142 serial_platform_data[i].membase = NULL; 143 serial_platform_data[i].mapbase = 0; 144 continue; 145 } 146 147 switch (i) { 148 case 0: 149 uart1_ck = clk_get(NULL, "uart1_ck"); 150 if (IS_ERR(uart1_ck)) 151 printk("Could not get uart1_ck\n"); 152 else { 153 clk_enable(uart1_ck); 154 if (cpu_is_omap15xx()) 155 clk_set_rate(uart1_ck, 12000000); 156 } 157 if (cpu_is_omap15xx()) { 158 omap_cfg_reg(UART1_TX); 159 omap_cfg_reg(UART1_RTS); 160 if (machine_is_omap_innovator()) { 161 reg = fpga_read(OMAP1510_FPGA_POWER); 162 reg |= OMAP1510_FPGA_PCR_COM1_EN; 163 fpga_write(reg, OMAP1510_FPGA_POWER); 164 udelay(10); 165 } 166 } 167 break; 168 case 1: 169 uart2_ck = clk_get(NULL, "uart2_ck"); 170 if (IS_ERR(uart2_ck)) 171 printk("Could not get uart2_ck\n"); 172 else { 173 clk_enable(uart2_ck); 174 if (cpu_is_omap15xx()) 175 clk_set_rate(uart2_ck, 12000000); 176 else 177 clk_set_rate(uart2_ck, 48000000); 178 } 179 if (cpu_is_omap15xx()) { 180 omap_cfg_reg(UART2_TX); 181 omap_cfg_reg(UART2_RTS); 182 if (machine_is_omap_innovator()) { 183 reg = fpga_read(OMAP1510_FPGA_POWER); 184 reg |= OMAP1510_FPGA_PCR_COM2_EN; 185 fpga_write(reg, OMAP1510_FPGA_POWER); 186 udelay(10); 187 } 188 } 189 break; 190 case 2: 191 uart3_ck = clk_get(NULL, "uart3_ck"); 192 if (IS_ERR(uart3_ck)) 193 printk("Could not get uart3_ck\n"); 194 else { 195 clk_enable(uart3_ck); 196 if (cpu_is_omap15xx()) 197 clk_set_rate(uart3_ck, 12000000); 198 } 199 if (cpu_is_omap15xx()) { 200 omap_cfg_reg(UART3_TX); 201 omap_cfg_reg(UART3_RX); 202 } 203 break; 204 } 205 omap_serial_reset(&serial_platform_data[i]); 206 } 207 } 208 209 #ifdef CONFIG_OMAP_SERIAL_WAKE 210 211 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id) 212 { 213 /* Need to do something with serial port right after wake-up? */ 214 return IRQ_HANDLED; 215 } 216 217 /* 218 * Reroutes serial RX lines to GPIO lines for the duration of 219 * sleep to allow waking up the device from serial port even 220 * in deep sleep. 221 */ 222 void omap_serial_wake_trigger(int enable) 223 { 224 if (!cpu_is_omap16xx()) 225 return; 226 227 if (uart1_ck != NULL) { 228 if (enable) 229 omap_cfg_reg(V14_16XX_GPIO37); 230 else 231 omap_cfg_reg(V14_16XX_UART1_RX); 232 } 233 if (uart2_ck != NULL) { 234 if (enable) 235 omap_cfg_reg(R9_16XX_GPIO18); 236 else 237 omap_cfg_reg(R9_16XX_UART2_RX); 238 } 239 if (uart3_ck != NULL) { 240 if (enable) 241 omap_cfg_reg(L14_16XX_GPIO49); 242 else 243 omap_cfg_reg(L14_16XX_UART3_RX); 244 } 245 } 246 247 static void __init omap_serial_set_port_wakeup(int gpio_nr) 248 { 249 int ret; 250 251 ret = gpio_request(gpio_nr, "UART wake"); 252 if (ret < 0) { 253 printk(KERN_ERR "Could not request UART wake GPIO: %i\n", 254 gpio_nr); 255 return; 256 } 257 gpio_direction_input(gpio_nr); 258 ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt, 259 IRQF_TRIGGER_RISING, "serial wakeup", NULL); 260 if (ret) { 261 gpio_free(gpio_nr); 262 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n", 263 gpio_nr); 264 return; 265 } 266 enable_irq_wake(gpio_to_irq(gpio_nr)); 267 } 268 269 static int __init omap_serial_wakeup_init(void) 270 { 271 if (!cpu_is_omap16xx()) 272 return 0; 273 274 if (uart1_ck != NULL) 275 omap_serial_set_port_wakeup(37); 276 if (uart2_ck != NULL) 277 omap_serial_set_port_wakeup(18); 278 if (uart3_ck != NULL) 279 omap_serial_set_port_wakeup(49); 280 281 return 0; 282 } 283 late_initcall(omap_serial_wakeup_init); 284 285 #endif /* CONFIG_OMAP_SERIAL_WAKE */ 286 287 static int __init omap_init(void) 288 { 289 return platform_device_register(&serial_device); 290 } 291 arch_initcall(omap_init); 292