1 //kernel/linux-omap-fsample/arch/arm/mach-omap1/pm.c#3 - integrate change 4545 (text) 2 /* 3 * linux/arch/arm/mach-omap1/pm.c 4 * 5 * OMAP Power Management Routines 6 * 7 * Original code for the SA11x0: 8 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 9 * 10 * Modified for the PXA250 by Nicolas Pitre: 11 * Copyright (c) 2002 Monta Vista Software, Inc. 12 * 13 * Modified for the OMAP1510 by David Singleton: 14 * Copyright (c) 2002 Monta Vista Software, Inc. 15 * 16 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com> 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 39 #include <linux/pm.h> 40 #include <linux/sched.h> 41 #include <linux/proc_fs.h> 42 #include <linux/pm.h> 43 #include <linux/interrupt.h> 44 #include <linux/sysfs.h> 45 #include <linux/module.h> 46 47 #include <asm/io.h> 48 #include <asm/irq.h> 49 #include <asm/atomic.h> 50 #include <asm/mach/time.h> 51 #include <asm/mach/irq.h> 52 #include <asm/mach-types.h> 53 54 #include <asm/arch/cpu.h> 55 #include <asm/arch/irqs.h> 56 #include <asm/arch/clock.h> 57 #include <asm/arch/sram.h> 58 #include <asm/arch/tc.h> 59 #include <asm/arch/pm.h> 60 #include <asm/arch/mux.h> 61 #include <asm/arch/tps65010.h> 62 #include <asm/arch/dma.h> 63 #include <asm/arch/dsp_common.h> 64 #include <asm/arch/dmtimer.h> 65 66 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 67 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; 68 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; 69 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; 70 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 71 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 72 73 static unsigned short enable_dyn_sleep = 1; 74 75 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf) 76 { 77 return sprintf(buf, "%hu\n", enable_dyn_sleep); 78 } 79 80 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys, 81 const char * buf, 82 size_t n) 83 { 84 unsigned short value; 85 if (sscanf(buf, "%hu", &value) != 1 || 86 (value != 0 && value != 1)) { 87 printk(KERN_ERR "idle_sleep_store: Invalid value\n"); 88 return -EINVAL; 89 } 90 enable_dyn_sleep = value; 91 return n; 92 } 93 94 static struct subsys_attribute sleep_while_idle_attr = { 95 .attr = { 96 .name = __stringify(sleep_while_idle), 97 .mode = 0644, 98 }, 99 .show = omap_pm_sleep_while_idle_show, 100 .store = omap_pm_sleep_while_idle_store, 101 }; 102 103 extern struct subsystem power_subsys; 104 static void (*omap_sram_idle)(void) = NULL; 105 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 106 107 /* 108 * Let's power down on idle, but only if we are really 109 * idle, because once we start down the path of 110 * going idle we continue to do idle even if we get 111 * a clock tick interrupt . . 112 */ 113 void omap_pm_idle(void) 114 { 115 extern __u32 arm_idlect1_mask; 116 __u32 use_idlect1 = arm_idlect1_mask; 117 #ifndef CONFIG_OMAP_MPU_TIMER 118 int do_sleep; 119 #endif 120 121 local_irq_disable(); 122 local_fiq_disable(); 123 if (need_resched()) { 124 local_fiq_enable(); 125 local_irq_enable(); 126 return; 127 } 128 129 /* 130 * Since an interrupt may set up a timer, we don't want to 131 * reprogram the hardware timer with interrupts enabled. 132 * Re-enable interrupts only after returning from idle. 133 */ 134 timer_dyn_reprogram(); 135 136 #ifdef CONFIG_OMAP_MPU_TIMER 137 #warning Enable 32kHz OS timer in order to allow sleep states in idle 138 use_idlect1 = use_idlect1 & ~(1 << 9); 139 #else 140 141 do_sleep = 0; 142 while (enable_dyn_sleep) { 143 144 #ifdef CONFIG_CBUS_TAHVO_USB 145 extern int vbus_active; 146 /* Clock requirements? */ 147 if (vbus_active) 148 break; 149 #endif 150 do_sleep = 1; 151 break; 152 } 153 154 #ifdef CONFIG_OMAP_DM_TIMER 155 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); 156 #endif 157 158 if (omap_dma_running()) { 159 use_idlect1 &= ~(1 << 6); 160 if (omap_lcd_dma_ext_running()) 161 use_idlect1 &= ~(1 << 12); 162 } 163 164 /* We should be able to remove the do_sleep variable and multiple 165 * tests above as soon as drivers, timer and DMA code have been fixed. 166 * Even the sleep block count should become obsolete. */ 167 if ((use_idlect1 != ~0) || !do_sleep) { 168 169 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); 170 if (cpu_is_omap15xx()) 171 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; 172 else 173 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; 174 omap_writel(use_idlect1, ARM_IDLECT1); 175 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); 176 omap_writel(saved_idlect1, ARM_IDLECT1); 177 178 local_fiq_enable(); 179 local_irq_enable(); 180 return; 181 } 182 omap_sram_suspend(omap_readl(ARM_IDLECT1), 183 omap_readl(ARM_IDLECT2)); 184 #endif 185 186 local_fiq_enable(); 187 local_irq_enable(); 188 } 189 190 /* 191 * Configuration of the wakeup event is board specific. For the 192 * moment we put it into this helper function. Later it may move 193 * to board specific files. 194 */ 195 static void omap_pm_wakeup_setup(void) 196 { 197 u32 level1_wake = 0; 198 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); 199 200 /* 201 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, 202 * and the L2 wakeup interrupts: keypad and UART2. Note that the 203 * drivers must still separately call omap_set_gpio_wakeup() to 204 * wake up to a GPIO interrupt. 205 */ 206 if (cpu_is_omap730()) 207 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) | 208 OMAP_IRQ_BIT(INT_730_IH2_IRQ); 209 else if (cpu_is_omap15xx()) 210 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 211 OMAP_IRQ_BIT(INT_1510_IH2_IRQ); 212 else if (cpu_is_omap16xx()) 213 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 214 OMAP_IRQ_BIT(INT_1610_IH2_IRQ); 215 216 omap_writel(~level1_wake, OMAP_IH1_MIR); 217 218 if (cpu_is_omap730()) { 219 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 220 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | 221 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), 222 OMAP_IH2_1_MIR); 223 } else if (cpu_is_omap15xx()) { 224 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 225 omap_writel(~level2_wake, OMAP_IH2_MIR); 226 } else if (cpu_is_omap16xx()) { 227 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 228 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 229 230 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ 231 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), 232 OMAP_IH2_1_MIR); 233 omap_writel(~0x0, OMAP_IH2_2_MIR); 234 omap_writel(~0x0, OMAP_IH2_3_MIR); 235 } 236 237 /* New IRQ agreement, recalculate in cascade order */ 238 omap_writel(1, OMAP_IH2_CONTROL); 239 omap_writel(1, OMAP_IH1_CONTROL); 240 } 241 242 #define EN_DSPCK 13 /* ARM_CKCTL */ 243 #define EN_APICK 6 /* ARM_IDLECT2 */ 244 #define DSP_EN 1 /* ARM_RSTCT1 */ 245 246 void omap_pm_suspend(void) 247 { 248 unsigned long arg0 = 0, arg1 = 0; 249 250 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev); 251 252 omap_serial_wake_trigger(1); 253 254 if (machine_is_omap_osk()) { 255 /* Stop LED1 (D9) blink */ 256 tps65010_set_led(LED1, OFF); 257 } 258 259 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); 260 261 /* 262 * Step 1: turn off interrupts (FIXME: NOTE: already disabled) 263 */ 264 265 local_irq_disable(); 266 local_fiq_disable(); 267 268 /* 269 * Step 2: save registers 270 * 271 * The omap is a strange/beautiful device. The caches, memory 272 * and register state are preserved across power saves. 273 * We have to save and restore very little register state to 274 * idle the omap. 275 * 276 * Save interrupt, MPUI, ARM and UPLD control registers. 277 */ 278 279 if (cpu_is_omap730()) { 280 MPUI730_SAVE(OMAP_IH1_MIR); 281 MPUI730_SAVE(OMAP_IH2_0_MIR); 282 MPUI730_SAVE(OMAP_IH2_1_MIR); 283 MPUI730_SAVE(MPUI_CTRL); 284 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 285 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 286 MPUI730_SAVE(EMIFS_CONFIG); 287 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 288 289 } else if (cpu_is_omap15xx()) { 290 MPUI1510_SAVE(OMAP_IH1_MIR); 291 MPUI1510_SAVE(OMAP_IH2_MIR); 292 MPUI1510_SAVE(MPUI_CTRL); 293 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 294 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 295 MPUI1510_SAVE(EMIFS_CONFIG); 296 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 297 } else if (cpu_is_omap16xx()) { 298 MPUI1610_SAVE(OMAP_IH1_MIR); 299 MPUI1610_SAVE(OMAP_IH2_0_MIR); 300 MPUI1610_SAVE(OMAP_IH2_1_MIR); 301 MPUI1610_SAVE(OMAP_IH2_2_MIR); 302 MPUI1610_SAVE(OMAP_IH2_3_MIR); 303 MPUI1610_SAVE(MPUI_CTRL); 304 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 305 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 306 MPUI1610_SAVE(EMIFS_CONFIG); 307 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 308 } 309 310 ARM_SAVE(ARM_CKCTL); 311 ARM_SAVE(ARM_IDLECT1); 312 ARM_SAVE(ARM_IDLECT2); 313 if (!(cpu_is_omap15xx())) 314 ARM_SAVE(ARM_IDLECT3); 315 ARM_SAVE(ARM_EWUPCT); 316 ARM_SAVE(ARM_RSTCT1); 317 ARM_SAVE(ARM_RSTCT2); 318 ARM_SAVE(ARM_SYSST); 319 ULPD_SAVE(ULPD_CLOCK_CTRL); 320 ULPD_SAVE(ULPD_STATUS_REQ); 321 322 /* (Step 3 removed - we now allow deep sleep by default) */ 323 324 /* 325 * Step 4: OMAP DSP Shutdown 326 */ 327 328 /* stop DSP */ 329 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); 330 331 /* shut down dsp_ck */ 332 if (!cpu_is_omap730()) 333 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 334 335 /* temporarily enabling api_ck to access DSP registers */ 336 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 337 338 /* save DSP registers */ 339 DSP_SAVE(DSP_IDLECT2); 340 341 /* Stop all DSP domain clocks */ 342 __raw_writew(0, DSP_IDLECT2); 343 344 /* 345 * Step 5: Wakeup Event Setup 346 */ 347 348 omap_pm_wakeup_setup(); 349 350 /* 351 * Step 6: ARM and Traffic controller shutdown 352 */ 353 354 /* disable ARM watchdog */ 355 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); 356 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); 357 358 /* 359 * Step 6b: ARM and Traffic controller shutdown 360 * 361 * Step 6 continues here. Prepare jump to power management 362 * assembly code in internal SRAM. 363 * 364 * Since the omap_cpu_suspend routine has been copied to 365 * SRAM, we'll do an indirect procedure call to it and pass the 366 * contents of arm_idlect1 and arm_idlect2 so it can restore 367 * them when it wakes up and it will return. 368 */ 369 370 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; 371 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; 372 373 /* 374 * Step 6c: ARM and Traffic controller shutdown 375 * 376 * Jump to assembly code. The processor will stay there 377 * until wake up. 378 */ 379 omap_sram_suspend(arg0, arg1); 380 381 /* 382 * If we are here, processor is woken up! 383 */ 384 385 /* 386 * Restore DSP clocks 387 */ 388 389 /* again temporarily enabling api_ck to access DSP registers */ 390 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 391 392 /* Restore DSP domain clocks */ 393 DSP_RESTORE(DSP_IDLECT2); 394 395 /* 396 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did 397 */ 398 399 if (!(cpu_is_omap15xx())) 400 ARM_RESTORE(ARM_IDLECT3); 401 ARM_RESTORE(ARM_CKCTL); 402 ARM_RESTORE(ARM_EWUPCT); 403 ARM_RESTORE(ARM_RSTCT1); 404 ARM_RESTORE(ARM_RSTCT2); 405 ARM_RESTORE(ARM_SYSST); 406 ULPD_RESTORE(ULPD_CLOCK_CTRL); 407 ULPD_RESTORE(ULPD_STATUS_REQ); 408 409 if (cpu_is_omap730()) { 410 MPUI730_RESTORE(EMIFS_CONFIG); 411 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG); 412 MPUI730_RESTORE(OMAP_IH1_MIR); 413 MPUI730_RESTORE(OMAP_IH2_0_MIR); 414 MPUI730_RESTORE(OMAP_IH2_1_MIR); 415 } else if (cpu_is_omap15xx()) { 416 MPUI1510_RESTORE(MPUI_CTRL); 417 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); 418 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); 419 MPUI1510_RESTORE(EMIFS_CONFIG); 420 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); 421 MPUI1510_RESTORE(OMAP_IH1_MIR); 422 MPUI1510_RESTORE(OMAP_IH2_MIR); 423 } else if (cpu_is_omap16xx()) { 424 MPUI1610_RESTORE(MPUI_CTRL); 425 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); 426 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); 427 MPUI1610_RESTORE(EMIFS_CONFIG); 428 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); 429 430 MPUI1610_RESTORE(OMAP_IH1_MIR); 431 MPUI1610_RESTORE(OMAP_IH2_0_MIR); 432 MPUI1610_RESTORE(OMAP_IH2_1_MIR); 433 MPUI1610_RESTORE(OMAP_IH2_2_MIR); 434 MPUI1610_RESTORE(OMAP_IH2_3_MIR); 435 } 436 437 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); 438 439 /* 440 * Reenable interrupts 441 */ 442 443 local_irq_enable(); 444 local_fiq_enable(); 445 446 omap_serial_wake_trigger(0); 447 448 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev); 449 450 if (machine_is_omap_osk()) { 451 /* Let LED1 (D9) blink again */ 452 tps65010_set_led(LED1, BLINK); 453 } 454 } 455 456 #if defined(DEBUG) && defined(CONFIG_PROC_FS) 457 static int g_read_completed; 458 459 /* 460 * Read system PM registers for debugging 461 */ 462 static int omap_pm_read_proc( 463 char *page_buffer, 464 char **my_first_byte, 465 off_t virtual_start, 466 int length, 467 int *eof, 468 void *data) 469 { 470 int my_buffer_offset = 0; 471 char * const my_base = page_buffer; 472 473 ARM_SAVE(ARM_CKCTL); 474 ARM_SAVE(ARM_IDLECT1); 475 ARM_SAVE(ARM_IDLECT2); 476 if (!(cpu_is_omap15xx())) 477 ARM_SAVE(ARM_IDLECT3); 478 ARM_SAVE(ARM_EWUPCT); 479 ARM_SAVE(ARM_RSTCT1); 480 ARM_SAVE(ARM_RSTCT2); 481 ARM_SAVE(ARM_SYSST); 482 483 ULPD_SAVE(ULPD_IT_STATUS); 484 ULPD_SAVE(ULPD_CLOCK_CTRL); 485 ULPD_SAVE(ULPD_SOFT_REQ); 486 ULPD_SAVE(ULPD_STATUS_REQ); 487 ULPD_SAVE(ULPD_DPLL_CTRL); 488 ULPD_SAVE(ULPD_POWER_CTRL); 489 490 if (cpu_is_omap730()) { 491 MPUI730_SAVE(MPUI_CTRL); 492 MPUI730_SAVE(MPUI_DSP_STATUS); 493 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 494 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 495 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 496 MPUI730_SAVE(EMIFS_CONFIG); 497 } else if (cpu_is_omap15xx()) { 498 MPUI1510_SAVE(MPUI_CTRL); 499 MPUI1510_SAVE(MPUI_DSP_STATUS); 500 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 501 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 502 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 503 MPUI1510_SAVE(EMIFS_CONFIG); 504 } else if (cpu_is_omap16xx()) { 505 MPUI1610_SAVE(MPUI_CTRL); 506 MPUI1610_SAVE(MPUI_DSP_STATUS); 507 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 508 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 509 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 510 MPUI1610_SAVE(EMIFS_CONFIG); 511 } 512 513 if (virtual_start == 0) { 514 g_read_completed = 0; 515 516 my_buffer_offset += sprintf(my_base + my_buffer_offset, 517 "ARM_CKCTL_REG: 0x%-8x \n" 518 "ARM_IDLECT1_REG: 0x%-8x \n" 519 "ARM_IDLECT2_REG: 0x%-8x \n" 520 "ARM_IDLECT3_REG: 0x%-8x \n" 521 "ARM_EWUPCT_REG: 0x%-8x \n" 522 "ARM_RSTCT1_REG: 0x%-8x \n" 523 "ARM_RSTCT2_REG: 0x%-8x \n" 524 "ARM_SYSST_REG: 0x%-8x \n" 525 "ULPD_IT_STATUS_REG: 0x%-4x \n" 526 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n" 527 "ULPD_SOFT_REQ_REG: 0x%-4x \n" 528 "ULPD_DPLL_CTRL_REG: 0x%-4x \n" 529 "ULPD_STATUS_REQ_REG: 0x%-4x \n" 530 "ULPD_POWER_CTRL_REG: 0x%-4x \n", 531 ARM_SHOW(ARM_CKCTL), 532 ARM_SHOW(ARM_IDLECT1), 533 ARM_SHOW(ARM_IDLECT2), 534 ARM_SHOW(ARM_IDLECT3), 535 ARM_SHOW(ARM_EWUPCT), 536 ARM_SHOW(ARM_RSTCT1), 537 ARM_SHOW(ARM_RSTCT2), 538 ARM_SHOW(ARM_SYSST), 539 ULPD_SHOW(ULPD_IT_STATUS), 540 ULPD_SHOW(ULPD_CLOCK_CTRL), 541 ULPD_SHOW(ULPD_SOFT_REQ), 542 ULPD_SHOW(ULPD_DPLL_CTRL), 543 ULPD_SHOW(ULPD_STATUS_REQ), 544 ULPD_SHOW(ULPD_POWER_CTRL)); 545 546 if (cpu_is_omap730()) { 547 my_buffer_offset += sprintf(my_base + my_buffer_offset, 548 "MPUI730_CTRL_REG 0x%-8x \n" 549 "MPUI730_DSP_STATUS_REG: 0x%-8x \n" 550 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 551 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n" 552 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n" 553 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n", 554 MPUI730_SHOW(MPUI_CTRL), 555 MPUI730_SHOW(MPUI_DSP_STATUS), 556 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG), 557 MPUI730_SHOW(MPUI_DSP_API_CONFIG), 558 MPUI730_SHOW(EMIFF_SDRAM_CONFIG), 559 MPUI730_SHOW(EMIFS_CONFIG)); 560 } else if (cpu_is_omap15xx()) { 561 my_buffer_offset += sprintf(my_base + my_buffer_offset, 562 "MPUI1510_CTRL_REG 0x%-8x \n" 563 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" 564 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 565 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" 566 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" 567 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n", 568 MPUI1510_SHOW(MPUI_CTRL), 569 MPUI1510_SHOW(MPUI_DSP_STATUS), 570 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), 571 MPUI1510_SHOW(MPUI_DSP_API_CONFIG), 572 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), 573 MPUI1510_SHOW(EMIFS_CONFIG)); 574 } else if (cpu_is_omap16xx()) { 575 my_buffer_offset += sprintf(my_base + my_buffer_offset, 576 "MPUI1610_CTRL_REG 0x%-8x \n" 577 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n" 578 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 579 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" 580 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" 581 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n", 582 MPUI1610_SHOW(MPUI_CTRL), 583 MPUI1610_SHOW(MPUI_DSP_STATUS), 584 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), 585 MPUI1610_SHOW(MPUI_DSP_API_CONFIG), 586 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), 587 MPUI1610_SHOW(EMIFS_CONFIG)); 588 } 589 590 g_read_completed++; 591 } else if (g_read_completed >= 1) { 592 *eof = 1; 593 return 0; 594 } 595 g_read_completed++; 596 597 *my_first_byte = page_buffer; 598 return my_buffer_offset; 599 } 600 601 static void omap_pm_init_proc(void) 602 { 603 struct proc_dir_entry *entry; 604 605 entry = create_proc_read_entry("driver/omap_pm", 606 S_IWUSR | S_IRUGO, NULL, 607 omap_pm_read_proc, NULL); 608 } 609 610 #endif /* DEBUG && CONFIG_PROC_FS */ 611 612 static void (*saved_idle)(void) = NULL; 613 614 /* 615 * omap_pm_prepare - Do preliminary suspend work. 616 * @state: suspend state we're entering. 617 * 618 */ 619 static int omap_pm_prepare(suspend_state_t state) 620 { 621 int error = 0; 622 623 /* We cannot sleep in idle until we have resumed */ 624 saved_idle = pm_idle; 625 pm_idle = NULL; 626 627 switch (state) 628 { 629 case PM_SUSPEND_STANDBY: 630 case PM_SUSPEND_MEM: 631 break; 632 633 case PM_SUSPEND_DISK: 634 return -ENOTSUPP; 635 636 default: 637 return -EINVAL; 638 } 639 640 return error; 641 } 642 643 644 /* 645 * omap_pm_enter - Actually enter a sleep state. 646 * @state: State we're entering. 647 * 648 */ 649 650 static int omap_pm_enter(suspend_state_t state) 651 { 652 switch (state) 653 { 654 case PM_SUSPEND_STANDBY: 655 case PM_SUSPEND_MEM: 656 omap_pm_suspend(); 657 break; 658 659 case PM_SUSPEND_DISK: 660 return -ENOTSUPP; 661 662 default: 663 return -EINVAL; 664 } 665 666 return 0; 667 } 668 669 670 /** 671 * omap_pm_finish - Finish up suspend sequence. 672 * @state: State we're coming out of. 673 * 674 * This is called after we wake back up (or if entering the sleep state 675 * failed). 676 */ 677 678 static int omap_pm_finish(suspend_state_t state) 679 { 680 pm_idle = saved_idle; 681 return 0; 682 } 683 684 685 static irqreturn_t omap_wakeup_interrupt(int irq, void * dev, 686 struct pt_regs * regs) 687 { 688 return IRQ_HANDLED; 689 } 690 691 static struct irqaction omap_wakeup_irq = { 692 .name = "peripheral wakeup", 693 .flags = IRQF_DISABLED, 694 .handler = omap_wakeup_interrupt 695 }; 696 697 698 699 static struct pm_ops omap_pm_ops ={ 700 .pm_disk_mode = 0, 701 .prepare = omap_pm_prepare, 702 .enter = omap_pm_enter, 703 .finish = omap_pm_finish, 704 }; 705 706 static int __init omap_pm_init(void) 707 { 708 printk("Power Management for TI OMAP.\n"); 709 710 /* 711 * We copy the assembler sleep/wakeup routines to SRAM. 712 * These routines need to be in SRAM as that's the only 713 * memory the MPU can see when it wakes up. 714 */ 715 if (cpu_is_omap730()) { 716 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend, 717 omap730_idle_loop_suspend_sz); 718 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, 719 omap730_cpu_suspend_sz); 720 } else if (cpu_is_omap15xx()) { 721 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend, 722 omap1510_idle_loop_suspend_sz); 723 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 724 omap1510_cpu_suspend_sz); 725 } else if (cpu_is_omap16xx()) { 726 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend, 727 omap1610_idle_loop_suspend_sz); 728 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, 729 omap1610_cpu_suspend_sz); 730 } 731 732 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) { 733 printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); 734 return -ENODEV; 735 } 736 737 pm_idle = omap_pm_idle; 738 739 if (cpu_is_omap730()) 740 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); 741 else if (cpu_is_omap16xx()) 742 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); 743 744 /* Program new power ramp-up time 745 * (0 for most boards since we don't lower voltage when in deep sleep) 746 */ 747 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); 748 749 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ 750 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); 751 752 /* Configure IDLECT3 */ 753 if (cpu_is_omap730()) 754 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3); 755 else if (cpu_is_omap16xx()) 756 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); 757 758 pm_set_ops(&omap_pm_ops); 759 760 #if defined(DEBUG) && defined(CONFIG_PROC_FS) 761 omap_pm_init_proc(); 762 #endif 763 764 subsys_create_file(&power_subsys, &sleep_while_idle_attr); 765 766 if (cpu_is_omap16xx()) { 767 /* configure LOW_PWR pin */ 768 omap_cfg_reg(T20_1610_LOW_PWR); 769 } 770 771 return 0; 772 } 773 __initcall(omap_pm_init); 774