1 /* 2 * linux/arch/arm/mach-omap1/irq.c 3 * 4 * Interrupt handler for all OMAP boards 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * Major cleanups by Juha Yrj�l� <juha.yrjola@nokia.com> 9 * 10 * Completely re-written to support various OMAP chips with bank specific 11 * interrupt handlers. 12 * 13 * Some snippets of the code taken from the older OMAP interrupt handler 14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 39 #include <linux/config.h> 40 #include <linux/init.h> 41 #include <linux/module.h> 42 #include <linux/sched.h> 43 #include <linux/interrupt.h> 44 #include <linux/ptrace.h> 45 46 #include <asm/hardware.h> 47 #include <asm/irq.h> 48 #include <asm/mach/irq.h> 49 #include <asm/arch/gpio.h> 50 #include <asm/arch/cpu.h> 51 52 #include <asm/io.h> 53 54 #define IRQ_BANK(irq) ((irq) >> 5) 55 #define IRQ_BIT(irq) ((irq) & 0x1f) 56 57 struct omap_irq_bank { 58 unsigned long base_reg; 59 unsigned long trigger_map; 60 unsigned long wake_enable; 61 }; 62 63 static unsigned int irq_bank_count = 0; 64 static struct omap_irq_bank *irq_banks; 65 66 static inline unsigned int irq_bank_readl(int bank, int offset) 67 { 68 return omap_readl(irq_banks[bank].base_reg + offset); 69 } 70 71 static inline void irq_bank_writel(unsigned long value, int bank, int offset) 72 { 73 omap_writel(value, irq_banks[bank].base_reg + offset); 74 } 75 76 static void omap_ack_irq(unsigned int irq) 77 { 78 if (irq > 31) 79 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); 80 81 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); 82 } 83 84 static void omap_mask_irq(unsigned int irq) 85 { 86 int bank = IRQ_BANK(irq); 87 u32 l; 88 89 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 90 l |= 1 << IRQ_BIT(irq); 91 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 92 } 93 94 static void omap_unmask_irq(unsigned int irq) 95 { 96 int bank = IRQ_BANK(irq); 97 u32 l; 98 99 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 100 l &= ~(1 << IRQ_BIT(irq)); 101 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 102 } 103 104 static void omap_mask_ack_irq(unsigned int irq) 105 { 106 omap_mask_irq(irq); 107 omap_ack_irq(irq); 108 } 109 110 static int omap_wake_irq(unsigned int irq, unsigned int enable) 111 { 112 int bank = IRQ_BANK(irq); 113 114 if (enable) 115 irq_banks[bank].wake_enable |= IRQ_BIT(irq); 116 else 117 irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); 118 119 return 0; 120 } 121 122 123 /* 124 * Allows tuning the IRQ type and priority 125 * 126 * NOTE: There is currently no OMAP fiq handler for Linux. Read the 127 * mailing list threads on FIQ handlers if you are planning to 128 * add a FIQ handler for OMAP. 129 */ 130 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 131 { 132 signed int bank; 133 unsigned long val, offset; 134 135 bank = IRQ_BANK(irq); 136 /* FIQ is only available on bank 0 interrupts */ 137 fiq = bank ? 0 : (fiq & 0x1); 138 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); 139 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; 140 irq_bank_writel(val, bank, offset); 141 } 142 143 #ifdef CONFIG_ARCH_OMAP730 144 static struct omap_irq_bank omap730_irq_banks[] = { 145 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, 146 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, 147 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, 148 }; 149 #endif 150 151 #ifdef CONFIG_ARCH_OMAP15XX 152 static struct omap_irq_bank omap1510_irq_banks[] = { 153 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 154 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 155 }; 156 static struct omap_irq_bank omap310_irq_banks[] = { 157 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, 158 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, 159 }; 160 #endif 161 162 #if defined(CONFIG_ARCH_OMAP16XX) 163 164 static struct omap_irq_bank omap1610_irq_banks[] = { 165 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 166 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 167 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 168 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 169 }; 170 #endif 171 172 static struct irqchip omap_irq_chip = { 173 .ack = omap_mask_ack_irq, 174 .mask = omap_mask_irq, 175 .unmask = omap_unmask_irq, 176 .set_wake = omap_wake_irq, 177 }; 178 179 void __init omap_init_irq(void) 180 { 181 int i, j; 182 183 #ifdef CONFIG_ARCH_OMAP730 184 if (cpu_is_omap730()) { 185 irq_banks = omap730_irq_banks; 186 irq_bank_count = ARRAY_SIZE(omap730_irq_banks); 187 } 188 #endif 189 #ifdef CONFIG_ARCH_OMAP15XX 190 if (cpu_is_omap1510()) { 191 irq_banks = omap1510_irq_banks; 192 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 193 } 194 if (cpu_is_omap310()) { 195 irq_banks = omap310_irq_banks; 196 irq_bank_count = ARRAY_SIZE(omap310_irq_banks); 197 } 198 #endif 199 #if defined(CONFIG_ARCH_OMAP16XX) 200 if (cpu_is_omap16xx()) { 201 irq_banks = omap1610_irq_banks; 202 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); 203 } 204 #endif 205 printk("Total of %i interrupts in %i interrupt banks\n", 206 irq_bank_count * 32, irq_bank_count); 207 208 /* Mask and clear all interrupts */ 209 for (i = 0; i < irq_bank_count; i++) { 210 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); 211 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); 212 } 213 214 /* Clear any pending interrupts */ 215 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); 216 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); 217 218 /* Enable interrupts in global mask */ 219 if (cpu_is_omap730()) { 220 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); 221 } 222 223 /* Install the interrupt handlers for each bank */ 224 for (i = 0; i < irq_bank_count; i++) { 225 for (j = i * 32; j < (i + 1) * 32; j++) { 226 int irq_trigger; 227 228 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 229 omap_irq_set_cfg(j, 0, 0, irq_trigger); 230 231 set_irq_chip(j, &omap_irq_chip); 232 set_irq_handler(j, do_level_IRQ); 233 set_irq_flags(j, IRQF_VALID); 234 } 235 } 236 237 /* Unmask level 2 handler */ 238 239 if (cpu_is_omap730()) 240 omap_unmask_irq(INT_730_IH2_IRQ); 241 else if (cpu_is_omap1510()) 242 omap_unmask_irq(INT_1510_IH2_IRQ); 243 else if (cpu_is_omap16xx()) 244 omap_unmask_irq(INT_1610_IH2_IRQ); 245 } 246