1 /* 2 * linux/arch/arm/mach-omap/irq.c 3 * 4 * Interrupt handler for all OMAP boards 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * Major cleanups by Juha Yrj�l� <juha.yrjola@nokia.com> 9 * 10 * Completely re-written to support various OMAP chips with bank specific 11 * interrupt handlers. 12 * 13 * Some snippets of the code taken from the older OMAP interrupt handler 14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38 39 #include <linux/config.h> 40 #include <linux/init.h> 41 #include <linux/module.h> 42 #include <linux/sched.h> 43 #include <linux/interrupt.h> 44 #include <linux/ptrace.h> 45 46 #include <asm/hardware.h> 47 #include <asm/irq.h> 48 #include <asm/mach/irq.h> 49 #include <asm/arch/gpio.h> 50 51 #include <asm/io.h> 52 53 #define IRQ_BANK(irq) ((irq) >> 5) 54 #define IRQ_BIT(irq) ((irq) & 0x1f) 55 56 struct omap_irq_bank { 57 unsigned long base_reg; 58 unsigned long trigger_map; 59 unsigned long wake_enable; 60 }; 61 62 static unsigned int irq_bank_count = 0; 63 static struct omap_irq_bank *irq_banks; 64 65 static inline unsigned int irq_bank_readl(int bank, int offset) 66 { 67 return omap_readl(irq_banks[bank].base_reg + offset); 68 } 69 70 static inline void irq_bank_writel(unsigned long value, int bank, int offset) 71 { 72 omap_writel(value, irq_banks[bank].base_reg + offset); 73 } 74 75 static void omap_ack_irq(unsigned int irq) 76 { 77 if (irq > 31) 78 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); 79 80 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); 81 } 82 83 static void omap_mask_irq(unsigned int irq) 84 { 85 int bank = IRQ_BANK(irq); 86 u32 l; 87 88 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 89 l |= 1 << IRQ_BIT(irq); 90 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 91 } 92 93 static void omap_unmask_irq(unsigned int irq) 94 { 95 int bank = IRQ_BANK(irq); 96 u32 l; 97 98 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 99 l &= ~(1 << IRQ_BIT(irq)); 100 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 101 } 102 103 static void omap_mask_ack_irq(unsigned int irq) 104 { 105 omap_mask_irq(irq); 106 omap_ack_irq(irq); 107 } 108 109 static int omap_wake_irq(unsigned int irq, unsigned int enable) 110 { 111 int bank = IRQ_BANK(irq); 112 113 if (enable) 114 irq_banks[bank].wake_enable |= IRQ_BIT(irq); 115 else 116 irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); 117 118 return 0; 119 } 120 121 122 /* 123 * Allows tuning the IRQ type and priority 124 * 125 * NOTE: There is currently no OMAP fiq handler for Linux. Read the 126 * mailing list threads on FIQ handlers if you are planning to 127 * add a FIQ handler for OMAP. 128 */ 129 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 130 { 131 signed int bank; 132 unsigned long val, offset; 133 134 bank = IRQ_BANK(irq); 135 /* FIQ is only available on bank 0 interrupts */ 136 fiq = bank ? 0 : (fiq & 0x1); 137 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); 138 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; 139 irq_bank_writel(val, bank, offset); 140 } 141 142 #ifdef CONFIG_ARCH_OMAP730 143 static struct omap_irq_bank omap730_irq_banks[] = { 144 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, 145 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, 146 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, 147 }; 148 #endif 149 150 #ifdef CONFIG_ARCH_OMAP1510 151 static struct omap_irq_bank omap1510_irq_banks[] = { 152 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 153 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 154 }; 155 #endif 156 157 #if defined(CONFIG_ARCH_OMAP16XX) 158 159 static struct omap_irq_bank omap1610_irq_banks[] = { 160 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 161 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 162 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 163 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 164 }; 165 #endif 166 167 static struct irqchip omap_irq_chip = { 168 .ack = omap_mask_ack_irq, 169 .mask = omap_mask_irq, 170 .unmask = omap_unmask_irq, 171 .wake = omap_wake_irq, 172 }; 173 174 void __init omap_init_irq(void) 175 { 176 int i, j; 177 178 #ifdef CONFIG_ARCH_OMAP730 179 if (cpu_is_omap730()) { 180 irq_banks = omap730_irq_banks; 181 irq_bank_count = ARRAY_SIZE(omap730_irq_banks); 182 } 183 #endif 184 #ifdef CONFIG_ARCH_OMAP1510 185 if (cpu_is_omap1510()) { 186 irq_banks = omap1510_irq_banks; 187 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 188 } 189 #endif 190 #if defined(CONFIG_ARCH_OMAP16XX) 191 if (cpu_is_omap16xx()) { 192 irq_banks = omap1610_irq_banks; 193 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); 194 } 195 #endif 196 printk("Total of %i interrupts in %i interrupt banks\n", 197 irq_bank_count * 32, irq_bank_count); 198 199 /* Mask and clear all interrupts */ 200 for (i = 0; i < irq_bank_count; i++) { 201 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); 202 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); 203 } 204 205 /* Clear any pending interrupts */ 206 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); 207 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); 208 209 /* Enable interrupts in global mask */ 210 if (cpu_is_omap730()) { 211 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); 212 } 213 214 /* Install the interrupt handlers for each bank */ 215 for (i = 0; i < irq_bank_count; i++) { 216 for (j = i * 32; j < (i + 1) * 32; j++) { 217 int irq_trigger; 218 219 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 220 omap_irq_set_cfg(j, 0, 0, irq_trigger); 221 222 set_irq_chip(j, &omap_irq_chip); 223 set_irq_handler(j, do_level_IRQ); 224 set_irq_flags(j, IRQF_VALID); 225 } 226 } 227 228 /* Unmask level 2 handler */ 229 if (cpu_is_omap730()) { 230 omap_unmask_irq(INT_730_IH2_IRQ); 231 } else { 232 omap_unmask_irq(INT_IH2_IRQ); 233 } 234 } 235