152650505SPaul Walmsley /* 252650505SPaul Walmsley * linux/arch/arm/mach-omap1/clock_data.c 352650505SPaul Walmsley * 451c19541SPaul Walmsley * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation 552650505SPaul Walmsley * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 652650505SPaul Walmsley * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 752650505SPaul Walmsley * 852650505SPaul Walmsley * This program is free software; you can redistribute it and/or modify 952650505SPaul Walmsley * it under the terms of the GNU General Public License version 2 as 1052650505SPaul Walmsley * published by the Free Software Foundation. 11fb2fc920SPaul Walmsley * 12fb2fc920SPaul Walmsley * To do: 13fb2fc920SPaul Walmsley * - Clocks that are only available on some chips should be marked with the 14fb2fc920SPaul Walmsley * chips that they are present on. 1552650505SPaul Walmsley */ 1652650505SPaul Walmsley 1752650505SPaul Walmsley #include <linux/kernel.h> 182c799cefSTony Lindgren #include <linux/io.h> 1952650505SPaul Walmsley #include <linux/clk.h> 206560ee07SJanusz Krzysztofik #include <linux/cpufreq.h> 216560ee07SJanusz Krzysztofik #include <linux/delay.h> 2252650505SPaul Walmsley 2352650505SPaul Walmsley #include <asm/mach-types.h> /* for machine_is_* */ 2452650505SPaul Walmsley 2552650505SPaul Walmsley #include <plat/clock.h> 2652650505SPaul Walmsley #include <plat/cpu.h> 2752650505SPaul Walmsley #include <plat/clkdev_omap.h> 2852650505SPaul Walmsley 292c799cefSTony Lindgren #include <mach/hardware.h> 30b924b204STony Lindgren #include <mach/usb.h> /* for OTG_BASE */ 312c799cefSTony Lindgren 32*622297fdSTony Lindgren #include "../plat-omap/sram.h" 33*622297fdSTony Lindgren 342e3ee9f4STony Lindgren #include "iomap.h" 3552650505SPaul Walmsley #include "clock.h" 3652650505SPaul Walmsley 37fb2fc920SPaul Walmsley /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ 38fb2fc920SPaul Walmsley #define IDL_CLKOUT_ARM_SHIFT 12 39fb2fc920SPaul Walmsley #define IDLTIM_ARM_SHIFT 9 40fb2fc920SPaul Walmsley #define IDLAPI_ARM_SHIFT 8 41fb2fc920SPaul Walmsley #define IDLIF_ARM_SHIFT 6 42fb2fc920SPaul Walmsley #define IDLLB_ARM_SHIFT 4 /* undocumented? */ 43fb2fc920SPaul Walmsley #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ 44fb2fc920SPaul Walmsley #define IDLPER_ARM_SHIFT 2 45fb2fc920SPaul Walmsley #define IDLXORP_ARM_SHIFT 1 46fb2fc920SPaul Walmsley #define IDLWDT_ARM_SHIFT 0 47fb2fc920SPaul Walmsley 48fb2fc920SPaul Walmsley /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ 49fb2fc920SPaul Walmsley #define CONF_MOD_UART3_CLK_MODE_R 31 50fb2fc920SPaul Walmsley #define CONF_MOD_UART2_CLK_MODE_R 30 51fb2fc920SPaul Walmsley #define CONF_MOD_UART1_CLK_MODE_R 29 52fb2fc920SPaul Walmsley #define CONF_MOD_MMC_SD_CLK_REQ_R 23 53fb2fc920SPaul Walmsley #define CONF_MOD_MCBSP3_AUXON 20 54fb2fc920SPaul Walmsley 55fb2fc920SPaul Walmsley /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ 56fb2fc920SPaul Walmsley #define CONF_MOD_SOSSI_CLK_EN_R 16 57fb2fc920SPaul Walmsley 58fb2fc920SPaul Walmsley /* Some OTG_SYSCON_2-specific bit fields */ 59fb2fc920SPaul Walmsley #define OTG_SYSCON_2_UHOST_EN_SHIFT 8 60fb2fc920SPaul Walmsley 61fb2fc920SPaul Walmsley /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ 62fb2fc920SPaul Walmsley #define SOFT_MMC2_DPLL_REQ_SHIFT 13 63fb2fc920SPaul Walmsley #define SOFT_MMC_DPLL_REQ_SHIFT 12 64fb2fc920SPaul Walmsley #define SOFT_UART3_DPLL_REQ_SHIFT 11 65fb2fc920SPaul Walmsley #define SOFT_UART2_DPLL_REQ_SHIFT 10 66fb2fc920SPaul Walmsley #define SOFT_UART1_DPLL_REQ_SHIFT 9 67fb2fc920SPaul Walmsley #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 68fb2fc920SPaul Walmsley #define SOFT_CAM_DPLL_REQ_SHIFT 7 69fb2fc920SPaul Walmsley #define SOFT_COM_MCKO_REQ_SHIFT 6 70fb2fc920SPaul Walmsley #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ 71fb2fc920SPaul Walmsley #define USB_REQ_EN_SHIFT 4 72fb2fc920SPaul Walmsley #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ 73fb2fc920SPaul Walmsley #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ 74fb2fc920SPaul Walmsley #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ 75fb2fc920SPaul Walmsley #define SOFT_DPLL_REQ_SHIFT 0 76fb2fc920SPaul Walmsley 77fb2fc920SPaul Walmsley /* 7852650505SPaul Walmsley * Omap1 clocks 79fb2fc920SPaul Walmsley */ 8052650505SPaul Walmsley 8152650505SPaul Walmsley static struct clk ck_ref = { 8252650505SPaul Walmsley .name = "ck_ref", 8352650505SPaul Walmsley .ops = &clkops_null, 8452650505SPaul Walmsley .rate = 12000000, 8552650505SPaul Walmsley }; 8652650505SPaul Walmsley 8752650505SPaul Walmsley static struct clk ck_dpll1 = { 8852650505SPaul Walmsley .name = "ck_dpll1", 8952650505SPaul Walmsley .ops = &clkops_null, 9052650505SPaul Walmsley .parent = &ck_ref, 9152650505SPaul Walmsley }; 9252650505SPaul Walmsley 9352650505SPaul Walmsley /* 9452650505SPaul Walmsley * FIXME: This clock seems to be necessary but no-one has asked for its 9552650505SPaul Walmsley * activation. [ FIX: SoSSI, SSR ] 9652650505SPaul Walmsley */ 9752650505SPaul Walmsley static struct arm_idlect1_clk ck_dpll1out = { 9852650505SPaul Walmsley .clk = { 9952650505SPaul Walmsley .name = "ck_dpll1out", 10052650505SPaul Walmsley .ops = &clkops_generic, 10152650505SPaul Walmsley .parent = &ck_dpll1, 10252650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | 10352650505SPaul Walmsley ENABLE_ON_INIT, 10452650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 10552650505SPaul Walmsley .enable_bit = EN_CKOUT_ARM, 10652650505SPaul Walmsley .recalc = &followparent_recalc, 10752650505SPaul Walmsley }, 108fb2fc920SPaul Walmsley .idlect_shift = IDL_CLKOUT_ARM_SHIFT, 10952650505SPaul Walmsley }; 11052650505SPaul Walmsley 11152650505SPaul Walmsley static struct clk sossi_ck = { 11252650505SPaul Walmsley .name = "ck_sossi", 11352650505SPaul Walmsley .ops = &clkops_generic, 11452650505SPaul Walmsley .parent = &ck_dpll1out.clk, 11552650505SPaul Walmsley .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, 11652650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), 117fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, 11852650505SPaul Walmsley .recalc = &omap1_sossi_recalc, 11952650505SPaul Walmsley .set_rate = &omap1_set_sossi_rate, 12052650505SPaul Walmsley }; 12152650505SPaul Walmsley 12252650505SPaul Walmsley static struct clk arm_ck = { 12352650505SPaul Walmsley .name = "arm_ck", 12452650505SPaul Walmsley .ops = &clkops_null, 12552650505SPaul Walmsley .parent = &ck_dpll1, 12652650505SPaul Walmsley .rate_offset = CKCTL_ARMDIV_OFFSET, 12752650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 12852650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 12952650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 13052650505SPaul Walmsley }; 13152650505SPaul Walmsley 13252650505SPaul Walmsley static struct arm_idlect1_clk armper_ck = { 13352650505SPaul Walmsley .clk = { 13452650505SPaul Walmsley .name = "armper_ck", 13552650505SPaul Walmsley .ops = &clkops_generic, 13652650505SPaul Walmsley .parent = &ck_dpll1, 13752650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 13852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 13952650505SPaul Walmsley .enable_bit = EN_PERCK, 14052650505SPaul Walmsley .rate_offset = CKCTL_PERDIV_OFFSET, 14152650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 14252650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 14352650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 14452650505SPaul Walmsley }, 145fb2fc920SPaul Walmsley .idlect_shift = IDLPER_ARM_SHIFT, 14652650505SPaul Walmsley }; 14752650505SPaul Walmsley 14852650505SPaul Walmsley /* 14952650505SPaul Walmsley * FIXME: This clock seems to be necessary but no-one has asked for its 15052650505SPaul Walmsley * activation. [ GPIO code for 1510 ] 15152650505SPaul Walmsley */ 15252650505SPaul Walmsley static struct clk arm_gpio_ck = { 15377640aabSVaradarajan, Charulatha .name = "ick", 15452650505SPaul Walmsley .ops = &clkops_generic, 15552650505SPaul Walmsley .parent = &ck_dpll1, 15652650505SPaul Walmsley .flags = ENABLE_ON_INIT, 15752650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 15852650505SPaul Walmsley .enable_bit = EN_GPIOCK, 15952650505SPaul Walmsley .recalc = &followparent_recalc, 16052650505SPaul Walmsley }; 16152650505SPaul Walmsley 16252650505SPaul Walmsley static struct arm_idlect1_clk armxor_ck = { 16352650505SPaul Walmsley .clk = { 16452650505SPaul Walmsley .name = "armxor_ck", 16552650505SPaul Walmsley .ops = &clkops_generic, 16652650505SPaul Walmsley .parent = &ck_ref, 16752650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 16852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 16952650505SPaul Walmsley .enable_bit = EN_XORPCK, 17052650505SPaul Walmsley .recalc = &followparent_recalc, 17152650505SPaul Walmsley }, 172fb2fc920SPaul Walmsley .idlect_shift = IDLXORP_ARM_SHIFT, 17352650505SPaul Walmsley }; 17452650505SPaul Walmsley 17552650505SPaul Walmsley static struct arm_idlect1_clk armtim_ck = { 17652650505SPaul Walmsley .clk = { 17752650505SPaul Walmsley .name = "armtim_ck", 17852650505SPaul Walmsley .ops = &clkops_generic, 17952650505SPaul Walmsley .parent = &ck_ref, 18052650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 18152650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 18252650505SPaul Walmsley .enable_bit = EN_TIMCK, 18352650505SPaul Walmsley .recalc = &followparent_recalc, 18452650505SPaul Walmsley }, 185fb2fc920SPaul Walmsley .idlect_shift = IDLTIM_ARM_SHIFT, 18652650505SPaul Walmsley }; 18752650505SPaul Walmsley 18852650505SPaul Walmsley static struct arm_idlect1_clk armwdt_ck = { 18952650505SPaul Walmsley .clk = { 19052650505SPaul Walmsley .name = "armwdt_ck", 19152650505SPaul Walmsley .ops = &clkops_generic, 19252650505SPaul Walmsley .parent = &ck_ref, 19352650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 19452650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 19552650505SPaul Walmsley .enable_bit = EN_WDTCK, 1960dfc242fSPaul Walmsley .fixed_div = 14, 1970dfc242fSPaul Walmsley .recalc = &omap_fixed_divisor_recalc, 19852650505SPaul Walmsley }, 199fb2fc920SPaul Walmsley .idlect_shift = IDLWDT_ARM_SHIFT, 20052650505SPaul Walmsley }; 20152650505SPaul Walmsley 20252650505SPaul Walmsley static struct clk arminth_ck16xx = { 20352650505SPaul Walmsley .name = "arminth_ck", 20452650505SPaul Walmsley .ops = &clkops_null, 20552650505SPaul Walmsley .parent = &arm_ck, 20652650505SPaul Walmsley .recalc = &followparent_recalc, 20752650505SPaul Walmsley /* Note: On 16xx the frequency can be divided by 2 by programming 20852650505SPaul Walmsley * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 20952650505SPaul Walmsley * 21052650505SPaul Walmsley * 1510 version is in TC clocks. 21152650505SPaul Walmsley */ 21252650505SPaul Walmsley }; 21352650505SPaul Walmsley 21452650505SPaul Walmsley static struct clk dsp_ck = { 21552650505SPaul Walmsley .name = "dsp_ck", 21652650505SPaul Walmsley .ops = &clkops_generic, 21752650505SPaul Walmsley .parent = &ck_dpll1, 21852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), 21952650505SPaul Walmsley .enable_bit = EN_DSPCK, 22052650505SPaul Walmsley .rate_offset = CKCTL_DSPDIV_OFFSET, 22152650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 22252650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 22352650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 22452650505SPaul Walmsley }; 22552650505SPaul Walmsley 22652650505SPaul Walmsley static struct clk dspmmu_ck = { 22752650505SPaul Walmsley .name = "dspmmu_ck", 22852650505SPaul Walmsley .ops = &clkops_null, 22952650505SPaul Walmsley .parent = &ck_dpll1, 23052650505SPaul Walmsley .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 23152650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 23252650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 23352650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 23452650505SPaul Walmsley }; 23552650505SPaul Walmsley 23652650505SPaul Walmsley static struct clk dspper_ck = { 23752650505SPaul Walmsley .name = "dspper_ck", 23852650505SPaul Walmsley .ops = &clkops_dspck, 23952650505SPaul Walmsley .parent = &ck_dpll1, 24052650505SPaul Walmsley .enable_reg = DSP_IDLECT2, 24152650505SPaul Walmsley .enable_bit = EN_PERCK, 24252650505SPaul Walmsley .rate_offset = CKCTL_PERDIV_OFFSET, 24352650505SPaul Walmsley .recalc = &omap1_ckctl_recalc_dsp_domain, 24452650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 24552650505SPaul Walmsley .set_rate = &omap1_clk_set_rate_dsp_domain, 24652650505SPaul Walmsley }; 24752650505SPaul Walmsley 24852650505SPaul Walmsley static struct clk dspxor_ck = { 24952650505SPaul Walmsley .name = "dspxor_ck", 25052650505SPaul Walmsley .ops = &clkops_dspck, 25152650505SPaul Walmsley .parent = &ck_ref, 25252650505SPaul Walmsley .enable_reg = DSP_IDLECT2, 25352650505SPaul Walmsley .enable_bit = EN_XORPCK, 25452650505SPaul Walmsley .recalc = &followparent_recalc, 25552650505SPaul Walmsley }; 25652650505SPaul Walmsley 25752650505SPaul Walmsley static struct clk dsptim_ck = { 25852650505SPaul Walmsley .name = "dsptim_ck", 25952650505SPaul Walmsley .ops = &clkops_dspck, 26052650505SPaul Walmsley .parent = &ck_ref, 26152650505SPaul Walmsley .enable_reg = DSP_IDLECT2, 26252650505SPaul Walmsley .enable_bit = EN_DSPTIMCK, 26352650505SPaul Walmsley .recalc = &followparent_recalc, 26452650505SPaul Walmsley }; 26552650505SPaul Walmsley 26652650505SPaul Walmsley static struct arm_idlect1_clk tc_ck = { 26752650505SPaul Walmsley .clk = { 26852650505SPaul Walmsley .name = "tc_ck", 26952650505SPaul Walmsley .ops = &clkops_null, 27052650505SPaul Walmsley .parent = &ck_dpll1, 27152650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 27252650505SPaul Walmsley .rate_offset = CKCTL_TCDIV_OFFSET, 27352650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 27452650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 27552650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 27652650505SPaul Walmsley }, 277fb2fc920SPaul Walmsley .idlect_shift = IDLIF_ARM_SHIFT, 27852650505SPaul Walmsley }; 27952650505SPaul Walmsley 28052650505SPaul Walmsley static struct clk arminth_ck1510 = { 28152650505SPaul Walmsley .name = "arminth_ck", 28252650505SPaul Walmsley .ops = &clkops_null, 28352650505SPaul Walmsley .parent = &tc_ck.clk, 28452650505SPaul Walmsley .recalc = &followparent_recalc, 28552650505SPaul Walmsley /* Note: On 1510 the frequency follows TC_CK 28652650505SPaul Walmsley * 28752650505SPaul Walmsley * 16xx version is in MPU clocks. 28852650505SPaul Walmsley */ 28952650505SPaul Walmsley }; 29052650505SPaul Walmsley 29152650505SPaul Walmsley static struct clk tipb_ck = { 29252650505SPaul Walmsley /* No-idle controlled by "tc_ck" */ 29352650505SPaul Walmsley .name = "tipb_ck", 29452650505SPaul Walmsley .ops = &clkops_null, 29552650505SPaul Walmsley .parent = &tc_ck.clk, 29652650505SPaul Walmsley .recalc = &followparent_recalc, 29752650505SPaul Walmsley }; 29852650505SPaul Walmsley 29952650505SPaul Walmsley static struct clk l3_ocpi_ck = { 30052650505SPaul Walmsley /* No-idle controlled by "tc_ck" */ 30152650505SPaul Walmsley .name = "l3_ocpi_ck", 30252650505SPaul Walmsley .ops = &clkops_generic, 30352650505SPaul Walmsley .parent = &tc_ck.clk, 30452650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), 30552650505SPaul Walmsley .enable_bit = EN_OCPI_CK, 30652650505SPaul Walmsley .recalc = &followparent_recalc, 30752650505SPaul Walmsley }; 30852650505SPaul Walmsley 30952650505SPaul Walmsley static struct clk tc1_ck = { 31052650505SPaul Walmsley .name = "tc1_ck", 31152650505SPaul Walmsley .ops = &clkops_generic, 31252650505SPaul Walmsley .parent = &tc_ck.clk, 31352650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), 31452650505SPaul Walmsley .enable_bit = EN_TC1_CK, 31552650505SPaul Walmsley .recalc = &followparent_recalc, 31652650505SPaul Walmsley }; 31752650505SPaul Walmsley 31852650505SPaul Walmsley /* 31952650505SPaul Walmsley * FIXME: This clock seems to be necessary but no-one has asked for its 32052650505SPaul Walmsley * activation. [ pm.c (SRAM), CCP, Camera ] 32152650505SPaul Walmsley */ 32252650505SPaul Walmsley static struct clk tc2_ck = { 32352650505SPaul Walmsley .name = "tc2_ck", 32452650505SPaul Walmsley .ops = &clkops_generic, 32552650505SPaul Walmsley .parent = &tc_ck.clk, 32652650505SPaul Walmsley .flags = ENABLE_ON_INIT, 32752650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), 32852650505SPaul Walmsley .enable_bit = EN_TC2_CK, 32952650505SPaul Walmsley .recalc = &followparent_recalc, 33052650505SPaul Walmsley }; 33152650505SPaul Walmsley 33252650505SPaul Walmsley static struct clk dma_ck = { 33352650505SPaul Walmsley /* No-idle controlled by "tc_ck" */ 33452650505SPaul Walmsley .name = "dma_ck", 33552650505SPaul Walmsley .ops = &clkops_null, 33652650505SPaul Walmsley .parent = &tc_ck.clk, 33752650505SPaul Walmsley .recalc = &followparent_recalc, 33852650505SPaul Walmsley }; 33952650505SPaul Walmsley 34052650505SPaul Walmsley static struct clk dma_lcdfree_ck = { 34152650505SPaul Walmsley .name = "dma_lcdfree_ck", 34252650505SPaul Walmsley .ops = &clkops_null, 34352650505SPaul Walmsley .parent = &tc_ck.clk, 34452650505SPaul Walmsley .recalc = &followparent_recalc, 34552650505SPaul Walmsley }; 34652650505SPaul Walmsley 34752650505SPaul Walmsley static struct arm_idlect1_clk api_ck = { 34852650505SPaul Walmsley .clk = { 34952650505SPaul Walmsley .name = "api_ck", 35052650505SPaul Walmsley .ops = &clkops_generic, 35152650505SPaul Walmsley .parent = &tc_ck.clk, 35252650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 35352650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 35452650505SPaul Walmsley .enable_bit = EN_APICK, 35552650505SPaul Walmsley .recalc = &followparent_recalc, 35652650505SPaul Walmsley }, 357fb2fc920SPaul Walmsley .idlect_shift = IDLAPI_ARM_SHIFT, 35852650505SPaul Walmsley }; 35952650505SPaul Walmsley 36052650505SPaul Walmsley static struct arm_idlect1_clk lb_ck = { 36152650505SPaul Walmsley .clk = { 36252650505SPaul Walmsley .name = "lb_ck", 36352650505SPaul Walmsley .ops = &clkops_generic, 36452650505SPaul Walmsley .parent = &tc_ck.clk, 36552650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 36652650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 36752650505SPaul Walmsley .enable_bit = EN_LBCK, 36852650505SPaul Walmsley .recalc = &followparent_recalc, 36952650505SPaul Walmsley }, 370fb2fc920SPaul Walmsley .idlect_shift = IDLLB_ARM_SHIFT, 37152650505SPaul Walmsley }; 37252650505SPaul Walmsley 37352650505SPaul Walmsley static struct clk rhea1_ck = { 37452650505SPaul Walmsley .name = "rhea1_ck", 37552650505SPaul Walmsley .ops = &clkops_null, 37652650505SPaul Walmsley .parent = &tc_ck.clk, 37752650505SPaul Walmsley .recalc = &followparent_recalc, 37852650505SPaul Walmsley }; 37952650505SPaul Walmsley 38052650505SPaul Walmsley static struct clk rhea2_ck = { 38152650505SPaul Walmsley .name = "rhea2_ck", 38252650505SPaul Walmsley .ops = &clkops_null, 38352650505SPaul Walmsley .parent = &tc_ck.clk, 38452650505SPaul Walmsley .recalc = &followparent_recalc, 38552650505SPaul Walmsley }; 38652650505SPaul Walmsley 38752650505SPaul Walmsley static struct clk lcd_ck_16xx = { 38852650505SPaul Walmsley .name = "lcd_ck", 38952650505SPaul Walmsley .ops = &clkops_generic, 39052650505SPaul Walmsley .parent = &ck_dpll1, 39152650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 39252650505SPaul Walmsley .enable_bit = EN_LCDCK, 39352650505SPaul Walmsley .rate_offset = CKCTL_LCDDIV_OFFSET, 39452650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 39552650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 39652650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 39752650505SPaul Walmsley }; 39852650505SPaul Walmsley 39952650505SPaul Walmsley static struct arm_idlect1_clk lcd_ck_1510 = { 40052650505SPaul Walmsley .clk = { 40152650505SPaul Walmsley .name = "lcd_ck", 40252650505SPaul Walmsley .ops = &clkops_generic, 40352650505SPaul Walmsley .parent = &ck_dpll1, 40452650505SPaul Walmsley .flags = CLOCK_IDLE_CONTROL, 40552650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), 40652650505SPaul Walmsley .enable_bit = EN_LCDCK, 40752650505SPaul Walmsley .rate_offset = CKCTL_LCDDIV_OFFSET, 40852650505SPaul Walmsley .recalc = &omap1_ckctl_recalc, 40952650505SPaul Walmsley .round_rate = omap1_clk_round_rate_ckctl_arm, 41052650505SPaul Walmsley .set_rate = omap1_clk_set_rate_ckctl_arm, 41152650505SPaul Walmsley }, 412fb2fc920SPaul Walmsley .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, 41352650505SPaul Walmsley }; 41452650505SPaul Walmsley 415fb2fc920SPaul Walmsley /* 416fb2fc920SPaul Walmsley * XXX The enable_bit here is misused - it simply switches between 12MHz 417fb2fc920SPaul Walmsley * and 48MHz. Reimplement with clksel. 418fb2fc920SPaul Walmsley * 419fb2fc920SPaul Walmsley * XXX does this need SYSC register handling? 420fb2fc920SPaul Walmsley */ 42152650505SPaul Walmsley static struct clk uart1_1510 = { 42252650505SPaul Walmsley .name = "uart1_ck", 42352650505SPaul Walmsley .ops = &clkops_null, 42452650505SPaul Walmsley /* Direct from ULPD, no real parent */ 42552650505SPaul Walmsley .parent = &armper_ck.clk, 42652650505SPaul Walmsley .rate = 12000000, 42752650505SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 42852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 429fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_UART1_CLK_MODE_R, 43052650505SPaul Walmsley .set_rate = &omap1_set_uart_rate, 43152650505SPaul Walmsley .recalc = &omap1_uart_recalc, 43252650505SPaul Walmsley }; 43352650505SPaul Walmsley 434fb2fc920SPaul Walmsley /* 435fb2fc920SPaul Walmsley * XXX The enable_bit here is misused - it simply switches between 12MHz 436fb2fc920SPaul Walmsley * and 48MHz. Reimplement with clksel. 437fb2fc920SPaul Walmsley * 438fb2fc920SPaul Walmsley * XXX SYSC register handling does not belong in the clock framework 439fb2fc920SPaul Walmsley */ 44052650505SPaul Walmsley static struct uart_clk uart1_16xx = { 44152650505SPaul Walmsley .clk = { 44252650505SPaul Walmsley .name = "uart1_ck", 443fb2fc920SPaul Walmsley .ops = &clkops_uart_16xx, 44452650505SPaul Walmsley /* Direct from ULPD, no real parent */ 44552650505SPaul Walmsley .parent = &armper_ck.clk, 44652650505SPaul Walmsley .rate = 48000000, 44751c19541SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 44852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 449fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_UART1_CLK_MODE_R, 45052650505SPaul Walmsley }, 45152650505SPaul Walmsley .sysc_addr = 0xfffb0054, 45252650505SPaul Walmsley }; 45352650505SPaul Walmsley 454fb2fc920SPaul Walmsley /* 455fb2fc920SPaul Walmsley * XXX The enable_bit here is misused - it simply switches between 12MHz 456fb2fc920SPaul Walmsley * and 48MHz. Reimplement with clksel. 457fb2fc920SPaul Walmsley * 458fb2fc920SPaul Walmsley * XXX does this need SYSC register handling? 459fb2fc920SPaul Walmsley */ 46052650505SPaul Walmsley static struct clk uart2_ck = { 46152650505SPaul Walmsley .name = "uart2_ck", 46252650505SPaul Walmsley .ops = &clkops_null, 46352650505SPaul Walmsley /* Direct from ULPD, no real parent */ 46452650505SPaul Walmsley .parent = &armper_ck.clk, 46552650505SPaul Walmsley .rate = 12000000, 46652650505SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 46752650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 468fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_UART2_CLK_MODE_R, 46952650505SPaul Walmsley .set_rate = &omap1_set_uart_rate, 47052650505SPaul Walmsley .recalc = &omap1_uart_recalc, 47152650505SPaul Walmsley }; 47252650505SPaul Walmsley 473fb2fc920SPaul Walmsley /* 474fb2fc920SPaul Walmsley * XXX The enable_bit here is misused - it simply switches between 12MHz 475fb2fc920SPaul Walmsley * and 48MHz. Reimplement with clksel. 476fb2fc920SPaul Walmsley * 477fb2fc920SPaul Walmsley * XXX does this need SYSC register handling? 478fb2fc920SPaul Walmsley */ 47952650505SPaul Walmsley static struct clk uart3_1510 = { 48052650505SPaul Walmsley .name = "uart3_ck", 48152650505SPaul Walmsley .ops = &clkops_null, 48252650505SPaul Walmsley /* Direct from ULPD, no real parent */ 48352650505SPaul Walmsley .parent = &armper_ck.clk, 48452650505SPaul Walmsley .rate = 12000000, 48552650505SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 48652650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 487fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_UART3_CLK_MODE_R, 48852650505SPaul Walmsley .set_rate = &omap1_set_uart_rate, 48952650505SPaul Walmsley .recalc = &omap1_uart_recalc, 49052650505SPaul Walmsley }; 49152650505SPaul Walmsley 492fb2fc920SPaul Walmsley /* 493fb2fc920SPaul Walmsley * XXX The enable_bit here is misused - it simply switches between 12MHz 494fb2fc920SPaul Walmsley * and 48MHz. Reimplement with clksel. 495fb2fc920SPaul Walmsley * 496fb2fc920SPaul Walmsley * XXX SYSC register handling does not belong in the clock framework 497fb2fc920SPaul Walmsley */ 49852650505SPaul Walmsley static struct uart_clk uart3_16xx = { 49952650505SPaul Walmsley .clk = { 50052650505SPaul Walmsley .name = "uart3_ck", 501fb2fc920SPaul Walmsley .ops = &clkops_uart_16xx, 50252650505SPaul Walmsley /* Direct from ULPD, no real parent */ 50352650505SPaul Walmsley .parent = &armper_ck.clk, 50452650505SPaul Walmsley .rate = 48000000, 50551c19541SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 50652650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 507fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_UART3_CLK_MODE_R, 50852650505SPaul Walmsley }, 50952650505SPaul Walmsley .sysc_addr = 0xfffb9854, 51052650505SPaul Walmsley }; 51152650505SPaul Walmsley 51252650505SPaul Walmsley static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 51352650505SPaul Walmsley .name = "usb_clko", 51452650505SPaul Walmsley .ops = &clkops_generic, 51552650505SPaul Walmsley /* Direct from ULPD, no parent */ 51652650505SPaul Walmsley .rate = 6000000, 51751c19541SPaul Walmsley .flags = ENABLE_REG_32BIT, 51852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), 51952650505SPaul Walmsley .enable_bit = USB_MCLK_EN_BIT, 52052650505SPaul Walmsley }; 52152650505SPaul Walmsley 52252650505SPaul Walmsley static struct clk usb_hhc_ck1510 = { 52352650505SPaul Walmsley .name = "usb_hhc_ck", 52452650505SPaul Walmsley .ops = &clkops_generic, 52552650505SPaul Walmsley /* Direct from ULPD, no parent */ 52652650505SPaul Walmsley .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 52751c19541SPaul Walmsley .flags = ENABLE_REG_32BIT, 52852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 52952650505SPaul Walmsley .enable_bit = USB_HOST_HHC_UHOST_EN, 53052650505SPaul Walmsley }; 53152650505SPaul Walmsley 53252650505SPaul Walmsley static struct clk usb_hhc_ck16xx = { 53352650505SPaul Walmsley .name = "usb_hhc_ck", 53452650505SPaul Walmsley .ops = &clkops_generic, 53552650505SPaul Walmsley /* Direct from ULPD, no parent */ 53652650505SPaul Walmsley .rate = 48000000, 53752650505SPaul Walmsley /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 53851c19541SPaul Walmsley .flags = ENABLE_REG_32BIT, 53952650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ 540fb2fc920SPaul Walmsley .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT 54152650505SPaul Walmsley }; 54252650505SPaul Walmsley 54352650505SPaul Walmsley static struct clk usb_dc_ck = { 54452650505SPaul Walmsley .name = "usb_dc_ck", 54552650505SPaul Walmsley .ops = &clkops_generic, 54652650505SPaul Walmsley /* Direct from ULPD, no parent */ 54752650505SPaul Walmsley .rate = 48000000, 54852650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 549fb2fc920SPaul Walmsley .enable_bit = USB_REQ_EN_SHIFT, 55052650505SPaul Walmsley }; 55152650505SPaul Walmsley 55252650505SPaul Walmsley static struct clk usb_dc_ck7xx = { 55352650505SPaul Walmsley .name = "usb_dc_ck", 55452650505SPaul Walmsley .ops = &clkops_generic, 55552650505SPaul Walmsley /* Direct from ULPD, no parent */ 55652650505SPaul Walmsley .rate = 48000000, 55752650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 558fb2fc920SPaul Walmsley .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, 55952650505SPaul Walmsley }; 56052650505SPaul Walmsley 5618b8fbd39SCory Maccarrone static struct clk uart1_7xx = { 5628b8fbd39SCory Maccarrone .name = "uart1_ck", 5638b8fbd39SCory Maccarrone .ops = &clkops_generic, 5648b8fbd39SCory Maccarrone /* Direct from ULPD, no parent */ 5658b8fbd39SCory Maccarrone .rate = 12000000, 5668b8fbd39SCory Maccarrone .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 5678b8fbd39SCory Maccarrone .enable_bit = 9, 5688b8fbd39SCory Maccarrone }; 5698b8fbd39SCory Maccarrone 5708b8fbd39SCory Maccarrone static struct clk uart2_7xx = { 5718b8fbd39SCory Maccarrone .name = "uart2_ck", 5728b8fbd39SCory Maccarrone .ops = &clkops_generic, 5738b8fbd39SCory Maccarrone /* Direct from ULPD, no parent */ 5748b8fbd39SCory Maccarrone .rate = 12000000, 5758b8fbd39SCory Maccarrone .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 5768b8fbd39SCory Maccarrone .enable_bit = 11, 5778b8fbd39SCory Maccarrone }; 5788b8fbd39SCory Maccarrone 57952650505SPaul Walmsley static struct clk mclk_1510 = { 58052650505SPaul Walmsley .name = "mclk", 58152650505SPaul Walmsley .ops = &clkops_generic, 58252650505SPaul Walmsley /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 58352650505SPaul Walmsley .rate = 12000000, 58452650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 585fb2fc920SPaul Walmsley .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, 58652650505SPaul Walmsley }; 58752650505SPaul Walmsley 58852650505SPaul Walmsley static struct clk mclk_16xx = { 58952650505SPaul Walmsley .name = "mclk", 59052650505SPaul Walmsley .ops = &clkops_generic, 59152650505SPaul Walmsley /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 59252650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), 59352650505SPaul Walmsley .enable_bit = COM_ULPD_PLL_CLK_REQ, 59452650505SPaul Walmsley .set_rate = &omap1_set_ext_clk_rate, 59552650505SPaul Walmsley .round_rate = &omap1_round_ext_clk_rate, 59652650505SPaul Walmsley .init = &omap1_init_ext_clk, 59752650505SPaul Walmsley }; 59852650505SPaul Walmsley 59952650505SPaul Walmsley static struct clk bclk_1510 = { 60052650505SPaul Walmsley .name = "bclk", 60152650505SPaul Walmsley .ops = &clkops_generic, 60252650505SPaul Walmsley /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 60352650505SPaul Walmsley .rate = 12000000, 60452650505SPaul Walmsley }; 60552650505SPaul Walmsley 60652650505SPaul Walmsley static struct clk bclk_16xx = { 60752650505SPaul Walmsley .name = "bclk", 60852650505SPaul Walmsley .ops = &clkops_generic, 60952650505SPaul Walmsley /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 61052650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), 61152650505SPaul Walmsley .enable_bit = SWD_ULPD_PLL_CLK_REQ, 61252650505SPaul Walmsley .set_rate = &omap1_set_ext_clk_rate, 61352650505SPaul Walmsley .round_rate = &omap1_round_ext_clk_rate, 61452650505SPaul Walmsley .init = &omap1_init_ext_clk, 61552650505SPaul Walmsley }; 61652650505SPaul Walmsley 61752650505SPaul Walmsley static struct clk mmc1_ck = { 618b92c170dSPaul Walmsley .name = "mmc1_ck", 61952650505SPaul Walmsley .ops = &clkops_generic, 62052650505SPaul Walmsley /* Functional clock is direct from ULPD, interface clock is ARMPER */ 62152650505SPaul Walmsley .parent = &armper_ck.clk, 62252650505SPaul Walmsley .rate = 48000000, 62351c19541SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 62452650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 625fb2fc920SPaul Walmsley .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, 62652650505SPaul Walmsley }; 62752650505SPaul Walmsley 628fb2fc920SPaul Walmsley /* 629fb2fc920SPaul Walmsley * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as 630fb2fc920SPaul Walmsley * CONF_MOD_MCBSP3_AUXON ?? 631fb2fc920SPaul Walmsley */ 63252650505SPaul Walmsley static struct clk mmc2_ck = { 633b92c170dSPaul Walmsley .name = "mmc2_ck", 63452650505SPaul Walmsley .ops = &clkops_generic, 63552650505SPaul Walmsley /* Functional clock is direct from ULPD, interface clock is ARMPER */ 63652650505SPaul Walmsley .parent = &armper_ck.clk, 63752650505SPaul Walmsley .rate = 48000000, 63851c19541SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 63952650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 64052650505SPaul Walmsley .enable_bit = 20, 64152650505SPaul Walmsley }; 64252650505SPaul Walmsley 64352650505SPaul Walmsley static struct clk mmc3_ck = { 644b92c170dSPaul Walmsley .name = "mmc3_ck", 64552650505SPaul Walmsley .ops = &clkops_generic, 64652650505SPaul Walmsley /* Functional clock is direct from ULPD, interface clock is ARMPER */ 64752650505SPaul Walmsley .parent = &armper_ck.clk, 64852650505SPaul Walmsley .rate = 48000000, 64951c19541SPaul Walmsley .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 65052650505SPaul Walmsley .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 651fb2fc920SPaul Walmsley .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, 65252650505SPaul Walmsley }; 65352650505SPaul Walmsley 65452650505SPaul Walmsley static struct clk virtual_ck_mpu = { 65552650505SPaul Walmsley .name = "mpu", 65652650505SPaul Walmsley .ops = &clkops_null, 65752650505SPaul Walmsley .parent = &arm_ck, /* Is smarter alias for */ 65852650505SPaul Walmsley .recalc = &followparent_recalc, 65952650505SPaul Walmsley .set_rate = &omap1_select_table_rate, 66052650505SPaul Walmsley .round_rate = &omap1_round_to_table_rate, 66152650505SPaul Walmsley }; 66252650505SPaul Walmsley 66352650505SPaul Walmsley /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK 66452650505SPaul Walmsley remains active during MPU idle whenever this is enabled */ 66552650505SPaul Walmsley static struct clk i2c_fck = { 66652650505SPaul Walmsley .name = "i2c_fck", 66752650505SPaul Walmsley .ops = &clkops_null, 66852650505SPaul Walmsley .flags = CLOCK_NO_IDLE_PARENT, 66952650505SPaul Walmsley .parent = &armxor_ck.clk, 67052650505SPaul Walmsley .recalc = &followparent_recalc, 67152650505SPaul Walmsley }; 67252650505SPaul Walmsley 67352650505SPaul Walmsley static struct clk i2c_ick = { 67452650505SPaul Walmsley .name = "i2c_ick", 67552650505SPaul Walmsley .ops = &clkops_null, 67652650505SPaul Walmsley .flags = CLOCK_NO_IDLE_PARENT, 67752650505SPaul Walmsley .parent = &armper_ck.clk, 67852650505SPaul Walmsley .recalc = &followparent_recalc, 67952650505SPaul Walmsley }; 68052650505SPaul Walmsley 68152650505SPaul Walmsley /* 68252650505SPaul Walmsley * clkdev integration 68352650505SPaul Walmsley */ 68452650505SPaul Walmsley 68552650505SPaul Walmsley static struct omap_clk omap_clks[] = { 68652650505SPaul Walmsley /* non-ULPD clocks */ 68752650505SPaul Walmsley CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), 688e8ae6b6eSCory Maccarrone CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), 68952650505SPaul Walmsley /* CK_GEN1 clocks */ 69052650505SPaul Walmsley CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), 69152650505SPaul Walmsley CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), 69252650505SPaul Walmsley CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), 69352650505SPaul Walmsley CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 69477640aabSVaradarajan, Charulatha CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), 69552650505SPaul Walmsley CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 69652650505SPaul Walmsley CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), 69752650505SPaul Walmsley CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), 69852650505SPaul Walmsley CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), 69952650505SPaul Walmsley CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), 70052650505SPaul Walmsley CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), 70152650505SPaul Walmsley CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), 70252650505SPaul Walmsley /* CK_GEN2 clocks */ 70352650505SPaul Walmsley CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), 70452650505SPaul Walmsley CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), 70552650505SPaul Walmsley CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), 70652650505SPaul Walmsley CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 70752650505SPaul Walmsley CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), 70852650505SPaul Walmsley /* CK_GEN3 clocks */ 70952650505SPaul Walmsley CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 71052650505SPaul Walmsley CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), 71152650505SPaul Walmsley CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), 71252650505SPaul Walmsley CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), 71352650505SPaul Walmsley CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), 71452650505SPaul Walmsley CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), 71552650505SPaul Walmsley CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), 716e8ae6b6eSCory Maccarrone CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 71752650505SPaul Walmsley CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), 71852650505SPaul Walmsley CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), 71952650505SPaul Walmsley CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), 72052650505SPaul Walmsley CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), 72152650505SPaul Walmsley CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), 72252650505SPaul Walmsley /* ULPD clocks */ 72352650505SPaul Walmsley CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), 72452650505SPaul Walmsley CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), 7258b8fbd39SCory Maccarrone CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), 72652650505SPaul Walmsley CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), 7278b8fbd39SCory Maccarrone CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), 72852650505SPaul Walmsley CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), 72952650505SPaul Walmsley CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), 73052650505SPaul Walmsley CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), 73152650505SPaul Walmsley CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), 73252650505SPaul Walmsley CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), 73352650505SPaul Walmsley CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), 73452650505SPaul Walmsley CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), 73552650505SPaul Walmsley CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), 73652650505SPaul Walmsley CLK(NULL, "mclk", &mclk_16xx, CK_16XX), 73752650505SPaul Walmsley CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), 73852650505SPaul Walmsley CLK(NULL, "bclk", &bclk_16xx, CK_16XX), 73952650505SPaul Walmsley CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), 74052650505SPaul Walmsley CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), 74152650505SPaul Walmsley CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 74252650505SPaul Walmsley CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), 74352650505SPaul Walmsley CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), 74452650505SPaul Walmsley /* Virtual clocks */ 74552650505SPaul Walmsley CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), 746f7bb0d9aSBenoit Cousson CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), 747f7bb0d9aSBenoit Cousson CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), 748f7bb0d9aSBenoit Cousson CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), 749c5c4dce4SCory Maccarrone CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), 750c5c4dce4SCory Maccarrone CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), 751c5c4dce4SCory Maccarrone CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), 752c5c4dce4SCory Maccarrone CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), 75352650505SPaul Walmsley CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), 75452650505SPaul Walmsley CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), 75552650505SPaul Walmsley CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), 75652650505SPaul Walmsley CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), 75752650505SPaul Walmsley CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), 75852650505SPaul Walmsley CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), 75952650505SPaul Walmsley CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), 76052650505SPaul Walmsley CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 76152650505SPaul Walmsley CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 76252650505SPaul Walmsley CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 76352650505SPaul Walmsley }; 76452650505SPaul Walmsley 76552650505SPaul Walmsley /* 76652650505SPaul Walmsley * init 76752650505SPaul Walmsley */ 76852650505SPaul Walmsley 7699b11769fSCory Maccarrone static struct clk_functions omap1_clk_functions = { 77052650505SPaul Walmsley .clk_enable = omap1_clk_enable, 77152650505SPaul Walmsley .clk_disable = omap1_clk_disable, 77252650505SPaul Walmsley .clk_round_rate = omap1_clk_round_rate, 77352650505SPaul Walmsley .clk_set_rate = omap1_clk_set_rate, 77452650505SPaul Walmsley .clk_disable_unused = omap1_clk_disable_unused, 77552650505SPaul Walmsley }; 77652650505SPaul Walmsley 777e9b7086bSTony Lindgren static void __init omap1_show_rates(void) 778e9b7086bSTony Lindgren { 7797852ec05SPaul Walmsley pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 780e9b7086bSTony Lindgren ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, 781e9b7086bSTony Lindgren ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 782e9b7086bSTony Lindgren arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 783e9b7086bSTony Lindgren } 784e9b7086bSTony Lindgren 78524ce2705SJanusz Krzysztofik u32 cpu_mask; 78624ce2705SJanusz Krzysztofik 78752650505SPaul Walmsley int __init omap1_clk_init(void) 78852650505SPaul Walmsley { 78952650505SPaul Walmsley struct omap_clk *c; 79052650505SPaul Walmsley int crystal_type = 0; /* Default 12 MHz */ 79124ce2705SJanusz Krzysztofik u32 reg; 79252650505SPaul Walmsley 79352650505SPaul Walmsley #ifdef CONFIG_DEBUG_LL 79452650505SPaul Walmsley /* 79552650505SPaul Walmsley * Resets some clocks that may be left on from bootloader, 79652650505SPaul Walmsley * but leaves serial clocks on. 79752650505SPaul Walmsley */ 79852650505SPaul Walmsley omap_writel(0x3 << 29, MOD_CONF_CTRL_0); 79952650505SPaul Walmsley #endif 80052650505SPaul Walmsley 80152650505SPaul Walmsley /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 80252650505SPaul Walmsley reg = omap_readw(SOFT_REQ_REG) & (1 << 4); 80352650505SPaul Walmsley omap_writew(reg, SOFT_REQ_REG); 80452650505SPaul Walmsley if (!cpu_is_omap15xx()) 80552650505SPaul Walmsley omap_writew(0, SOFT_REQ_REG2); 80652650505SPaul Walmsley 80752650505SPaul Walmsley clk_init(&omap1_clk_functions); 80852650505SPaul Walmsley 80952650505SPaul Walmsley /* By default all idlect1 clocks are allowed to idle */ 81052650505SPaul Walmsley arm_idlect1_mask = ~0; 81152650505SPaul Walmsley 81252650505SPaul Walmsley for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 81352650505SPaul Walmsley clk_preinit(c->lk.clk); 81452650505SPaul Walmsley 81552650505SPaul Walmsley cpu_mask = 0; 81624ce2705SJanusz Krzysztofik if (cpu_is_omap1710()) 81724ce2705SJanusz Krzysztofik cpu_mask |= CK_1710; 81852650505SPaul Walmsley if (cpu_is_omap16xx()) 81952650505SPaul Walmsley cpu_mask |= CK_16XX; 82052650505SPaul Walmsley if (cpu_is_omap1510()) 82152650505SPaul Walmsley cpu_mask |= CK_1510; 82252650505SPaul Walmsley if (cpu_is_omap7xx()) 82352650505SPaul Walmsley cpu_mask |= CK_7XX; 82452650505SPaul Walmsley if (cpu_is_omap310()) 82552650505SPaul Walmsley cpu_mask |= CK_310; 82652650505SPaul Walmsley 82752650505SPaul Walmsley for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 82852650505SPaul Walmsley if (c->cpu & cpu_mask) { 82952650505SPaul Walmsley clkdev_add(&c->lk); 83052650505SPaul Walmsley clk_register(c->lk.clk); 83152650505SPaul Walmsley } 83252650505SPaul Walmsley 83352650505SPaul Walmsley /* Pointers to these clocks are needed by code in clock.c */ 83452650505SPaul Walmsley api_ck_p = clk_get(NULL, "api_ck"); 83552650505SPaul Walmsley ck_dpll1_p = clk_get(NULL, "ck_dpll1"); 83652650505SPaul Walmsley ck_ref_p = clk_get(NULL, "ck_ref"); 83752650505SPaul Walmsley 83865ae65c9SJanusz Krzysztofik if (cpu_is_omap7xx()) 83952650505SPaul Walmsley ck_ref.rate = 13000000; 84065ae65c9SJanusz Krzysztofik if (cpu_is_omap16xx() && crystal_type == 2) 84152650505SPaul Walmsley ck_ref.rate = 19200000; 84252650505SPaul Walmsley 8437852ec05SPaul Walmsley pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", 8447852ec05SPaul Walmsley omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), 84552650505SPaul Walmsley omap_readw(ARM_CKCTL)); 84652650505SPaul Walmsley 84752650505SPaul Walmsley /* We want to be in syncronous scalable mode */ 84852650505SPaul Walmsley omap_writew(0x1000, ARM_SYSST); 84952650505SPaul Walmsley 850e9b7086bSTony Lindgren 851e9b7086bSTony Lindgren /* 852e9b7086bSTony Lindgren * Initially use the values set by bootloader. Determine PLL rate and 853e9b7086bSTony Lindgren * recalculate dependent clocks as if kernel had changed PLL or 854e9b7086bSTony Lindgren * divisors. See also omap1_clk_late_init() that can reprogram dpll1 855e9b7086bSTony Lindgren * after the SRAM is initialized. 85652650505SPaul Walmsley */ 85752650505SPaul Walmsley { 85852650505SPaul Walmsley unsigned pll_ctl_val = omap_readw(DPLL_CTL); 85952650505SPaul Walmsley 86052650505SPaul Walmsley ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ 86152650505SPaul Walmsley if (pll_ctl_val & 0x10) { 86252650505SPaul Walmsley /* PLL enabled, apply multiplier and divisor */ 86352650505SPaul Walmsley if (pll_ctl_val & 0xf80) 86452650505SPaul Walmsley ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; 86552650505SPaul Walmsley ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; 86652650505SPaul Walmsley } else { 86752650505SPaul Walmsley /* PLL disabled, apply bypass divisor */ 86852650505SPaul Walmsley switch (pll_ctl_val & 0xc) { 86952650505SPaul Walmsley case 0: 87052650505SPaul Walmsley break; 87152650505SPaul Walmsley case 0x4: 87252650505SPaul Walmsley ck_dpll1.rate /= 2; 87352650505SPaul Walmsley break; 87452650505SPaul Walmsley default: 87552650505SPaul Walmsley ck_dpll1.rate /= 4; 87652650505SPaul Walmsley break; 87752650505SPaul Walmsley } 87852650505SPaul Walmsley } 87952650505SPaul Walmsley } 88052650505SPaul Walmsley propagate_rate(&ck_dpll1); 88152650505SPaul Walmsley /* Cache rates for clocks connected to ck_ref (not dpll1) */ 88252650505SPaul Walmsley propagate_rate(&ck_ref); 883e9b7086bSTony Lindgren omap1_show_rates(); 88465ae65c9SJanusz Krzysztofik if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { 88552650505SPaul Walmsley /* Select slicer output as OMAP input clock */ 88665ae65c9SJanusz Krzysztofik omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, 88765ae65c9SJanusz Krzysztofik OMAP7XX_PCC_UPLD_CTRL); 88865ae65c9SJanusz Krzysztofik } 88952650505SPaul Walmsley 89052650505SPaul Walmsley /* Amstrad Delta wants BCLK high when inactive */ 89152650505SPaul Walmsley if (machine_is_ams_delta()) 89252650505SPaul Walmsley omap_writel(omap_readl(ULPD_CLOCK_CTRL) | 89352650505SPaul Walmsley (1 << SDW_MCLK_INV_BIT), 89452650505SPaul Walmsley ULPD_CLOCK_CTRL); 89552650505SPaul Walmsley 89652650505SPaul Walmsley /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 89752650505SPaul Walmsley /* (on 730, bit 13 must not be cleared) */ 89852650505SPaul Walmsley if (cpu_is_omap7xx()) 89952650505SPaul Walmsley omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 90052650505SPaul Walmsley else 90152650505SPaul Walmsley omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 90252650505SPaul Walmsley 90352650505SPaul Walmsley /* Put DSP/MPUI into reset until needed */ 90452650505SPaul Walmsley omap_writew(0, ARM_RSTCT1); 90552650505SPaul Walmsley omap_writew(1, ARM_RSTCT2); 90652650505SPaul Walmsley omap_writew(0x400, ARM_IDLECT1); 90752650505SPaul Walmsley 90852650505SPaul Walmsley /* 90952650505SPaul Walmsley * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) 91052650505SPaul Walmsley * of the ARM_IDLECT2 register must be set to zero. The power-on 91152650505SPaul Walmsley * default value of this bit is one. 91252650505SPaul Walmsley */ 91352650505SPaul Walmsley omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ 91452650505SPaul Walmsley 91552650505SPaul Walmsley /* 91652650505SPaul Walmsley * Only enable those clocks we will need, let the drivers 91752650505SPaul Walmsley * enable other clocks as necessary 91852650505SPaul Walmsley */ 91952650505SPaul Walmsley clk_enable(&armper_ck.clk); 92052650505SPaul Walmsley clk_enable(&armxor_ck.clk); 92152650505SPaul Walmsley clk_enable(&armtim_ck.clk); /* This should be done by timer code */ 92252650505SPaul Walmsley 92352650505SPaul Walmsley if (cpu_is_omap15xx()) 92452650505SPaul Walmsley clk_enable(&arm_gpio_ck); 92552650505SPaul Walmsley 92652650505SPaul Walmsley return 0; 92752650505SPaul Walmsley } 928e9b7086bSTony Lindgren 929e9b7086bSTony Lindgren #define OMAP1_DPLL1_SANE_VALUE 60000000 930e9b7086bSTony Lindgren 931e9b7086bSTony Lindgren void __init omap1_clk_late_init(void) 932e9b7086bSTony Lindgren { 9336560ee07SJanusz Krzysztofik unsigned long rate = ck_dpll1.rate; 9346560ee07SJanusz Krzysztofik 935e9b7086bSTony Lindgren /* Find the highest supported frequency and enable it */ 936e9b7086bSTony Lindgren if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 937e9b7086bSTony Lindgren pr_err("System frequencies not set, using default. Check your config.\n"); 938f9e5908fSJanusz Krzysztofik /* 939f9e5908fSJanusz Krzysztofik * Reprogramming the DPLL is tricky, it must be done from SRAM. 940f9e5908fSJanusz Krzysztofik */ 941f9e5908fSJanusz Krzysztofik omap_sram_reprogram_clock(0x2290, 0x0005); 942e9b7086bSTony Lindgren ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; 943e9b7086bSTony Lindgren } 944e9b7086bSTony Lindgren propagate_rate(&ck_dpll1); 945e9b7086bSTony Lindgren omap1_show_rates(); 9466560ee07SJanusz Krzysztofik loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); 947e9b7086bSTony Lindgren } 948