1 /* 2 * linux/arch/arm/mach-omap1/clock.h 3 * 4 * Copyright (C) 2004 - 2005 Nokia corporation 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H 14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H 15 16 static int omap1_clk_enable_generic(struct clk * clk); 17 static void omap1_clk_disable_generic(struct clk * clk); 18 static void omap1_ckctl_recalc(struct clk * clk); 19 static void omap1_watchdog_recalc(struct clk * clk); 20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); 21 static int omap1_clk_enable_dsp_domain(struct clk * clk); 22 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); 23 static void omap1_clk_disable_dsp_domain(struct clk * clk); 24 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); 25 static void omap1_uart_recalc(struct clk * clk); 26 static int omap1_clk_enable_uart_functional(struct clk * clk); 27 static void omap1_clk_disable_uart_functional(struct clk * clk); 28 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); 29 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); 30 static void omap1_init_ext_clk(struct clk * clk); 31 static int omap1_select_table_rate(struct clk * clk, unsigned long rate); 32 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); 33 static int omap1_clk_enable(struct clk *clk); 34 static void omap1_clk_disable(struct clk *clk); 35 36 struct mpu_rate { 37 unsigned long rate; 38 unsigned long xtal; 39 unsigned long pll_rate; 40 __u16 ckctl_val; 41 __u16 dpllctl_val; 42 }; 43 44 struct uart_clk { 45 struct clk clk; 46 unsigned long sysc_addr; 47 }; 48 49 /* Provide a method for preventing idling some ARM IDLECT clocks */ 50 struct arm_idlect1_clk { 51 struct clk clk; 52 unsigned long no_idle_count; 53 __u8 idlect_shift; 54 }; 55 56 /* ARM_CKCTL bit shifts */ 57 #define CKCTL_PERDIV_OFFSET 0 58 #define CKCTL_LCDDIV_OFFSET 2 59 #define CKCTL_ARMDIV_OFFSET 4 60 #define CKCTL_DSPDIV_OFFSET 6 61 #define CKCTL_TCDIV_OFFSET 8 62 #define CKCTL_DSPMMUDIV_OFFSET 10 63 /*#define ARM_TIMXO 12*/ 64 #define EN_DSPCK 13 65 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ 66 /* DSP_CKCTL bit shifts */ 67 #define CKCTL_DSPPERDIV_OFFSET 0 68 69 /* ARM_IDLECT2 bit shifts */ 70 #define EN_WDTCK 0 71 #define EN_XORPCK 1 72 #define EN_PERCK 2 73 #define EN_LCDCK 3 74 #define EN_LBCK 4 /* Not on 1610/1710 */ 75 /*#define EN_HSABCK 5*/ 76 #define EN_APICK 6 77 #define EN_TIMCK 7 78 #define DMACK_REQ 8 79 #define EN_GPIOCK 9 /* Not on 1610/1710 */ 80 /*#define EN_LBFREECK 10*/ 81 #define EN_CKOUT_ARM 11 82 83 /* ARM_IDLECT3 bit shifts */ 84 #define EN_OCPI_CK 0 85 #define EN_TC1_CK 2 86 #define EN_TC2_CK 4 87 88 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ 89 #define EN_DSPTIMCK 5 90 91 /* Various register defines for clock controls scattered around OMAP chip */ 92 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ 93 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ 94 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ 95 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ 96 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 97 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 98 #define SOFT_REQ_REG 0xfffe0834 99 #define SOFT_REQ_REG2 0xfffe0880 100 101 /*------------------------------------------------------------------------- 102 * Omap1 MPU rate table 103 *-------------------------------------------------------------------------*/ 104 static struct mpu_rate rate_table[] = { 105 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL 106 * NOTE: Comment order here is different from bits in CKCTL value: 107 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv 108 */ 109 #if defined(CONFIG_OMAP_ARM_216MHZ) 110 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ 111 #endif 112 #if defined(CONFIG_OMAP_ARM_195MHZ) 113 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ 114 #endif 115 #if defined(CONFIG_OMAP_ARM_192MHZ) 116 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ 117 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ 118 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ 119 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ 120 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ 121 #endif 122 #if defined(CONFIG_OMAP_ARM_182MHZ) 123 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ 124 #endif 125 #if defined(CONFIG_OMAP_ARM_168MHZ) 126 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ 127 #endif 128 #if defined(CONFIG_OMAP_ARM_150MHZ) 129 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ 130 #endif 131 #if defined(CONFIG_OMAP_ARM_120MHZ) 132 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ 133 #endif 134 #if defined(CONFIG_OMAP_ARM_96MHZ) 135 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ 136 #endif 137 #if defined(CONFIG_OMAP_ARM_60MHZ) 138 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ 139 #endif 140 #if defined(CONFIG_OMAP_ARM_30MHZ) 141 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ 142 #endif 143 { 0, 0, 0, 0, 0 }, 144 }; 145 146 /*------------------------------------------------------------------------- 147 * Omap1 clocks 148 *-------------------------------------------------------------------------*/ 149 150 static struct clk ck_ref = { 151 .name = "ck_ref", 152 .rate = 12000000, 153 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 154 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 155 .enable = &omap1_clk_enable_generic, 156 .disable = &omap1_clk_disable_generic, 157 }; 158 159 static struct clk ck_dpll1 = { 160 .name = "ck_dpll1", 161 .parent = &ck_ref, 162 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 163 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED, 164 .enable = &omap1_clk_enable_generic, 165 .disable = &omap1_clk_disable_generic, 166 }; 167 168 static struct arm_idlect1_clk ck_dpll1out = { 169 .clk = { 170 .name = "ck_dpll1out", 171 .parent = &ck_dpll1, 172 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, 173 .enable_reg = (void __iomem *)ARM_IDLECT2, 174 .enable_bit = EN_CKOUT_ARM, 175 .recalc = &followparent_recalc, 176 .enable = &omap1_clk_enable_generic, 177 .disable = &omap1_clk_disable_generic, 178 }, 179 .idlect_shift = 12, 180 }; 181 182 static struct clk arm_ck = { 183 .name = "arm_ck", 184 .parent = &ck_dpll1, 185 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 186 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | 187 ALWAYS_ENABLED, 188 .rate_offset = CKCTL_ARMDIV_OFFSET, 189 .recalc = &omap1_ckctl_recalc, 190 .enable = &omap1_clk_enable_generic, 191 .disable = &omap1_clk_disable_generic, 192 }; 193 194 static struct arm_idlect1_clk armper_ck = { 195 .clk = { 196 .name = "armper_ck", 197 .parent = &ck_dpll1, 198 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 199 CLOCK_IN_OMAP310 | RATE_CKCTL | 200 CLOCK_IDLE_CONTROL, 201 .enable_reg = (void __iomem *)ARM_IDLECT2, 202 .enable_bit = EN_PERCK, 203 .rate_offset = CKCTL_PERDIV_OFFSET, 204 .recalc = &omap1_ckctl_recalc, 205 .enable = &omap1_clk_enable_generic, 206 .disable = &omap1_clk_disable_generic, 207 }, 208 .idlect_shift = 2, 209 }; 210 211 static struct clk arm_gpio_ck = { 212 .name = "arm_gpio_ck", 213 .parent = &ck_dpll1, 214 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, 215 .enable_reg = (void __iomem *)ARM_IDLECT2, 216 .enable_bit = EN_GPIOCK, 217 .recalc = &followparent_recalc, 218 .enable = &omap1_clk_enable_generic, 219 .disable = &omap1_clk_disable_generic, 220 }; 221 222 static struct arm_idlect1_clk armxor_ck = { 223 .clk = { 224 .name = "armxor_ck", 225 .parent = &ck_ref, 226 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 227 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 228 .enable_reg = (void __iomem *)ARM_IDLECT2, 229 .enable_bit = EN_XORPCK, 230 .recalc = &followparent_recalc, 231 .enable = &omap1_clk_enable_generic, 232 .disable = &omap1_clk_disable_generic, 233 }, 234 .idlect_shift = 1, 235 }; 236 237 static struct arm_idlect1_clk armtim_ck = { 238 .clk = { 239 .name = "armtim_ck", 240 .parent = &ck_ref, 241 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 242 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 243 .enable_reg = (void __iomem *)ARM_IDLECT2, 244 .enable_bit = EN_TIMCK, 245 .recalc = &followparent_recalc, 246 .enable = &omap1_clk_enable_generic, 247 .disable = &omap1_clk_disable_generic, 248 }, 249 .idlect_shift = 9, 250 }; 251 252 static struct arm_idlect1_clk armwdt_ck = { 253 .clk = { 254 .name = "armwdt_ck", 255 .parent = &ck_ref, 256 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 257 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 258 .enable_reg = (void __iomem *)ARM_IDLECT2, 259 .enable_bit = EN_WDTCK, 260 .recalc = &omap1_watchdog_recalc, 261 .enable = &omap1_clk_enable_generic, 262 .disable = &omap1_clk_disable_generic, 263 }, 264 .idlect_shift = 0, 265 }; 266 267 static struct clk arminth_ck16xx = { 268 .name = "arminth_ck", 269 .parent = &arm_ck, 270 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 271 .recalc = &followparent_recalc, 272 /* Note: On 16xx the frequency can be divided by 2 by programming 273 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 274 * 275 * 1510 version is in TC clocks. 276 */ 277 .enable = &omap1_clk_enable_generic, 278 .disable = &omap1_clk_disable_generic, 279 }; 280 281 static struct clk dsp_ck = { 282 .name = "dsp_ck", 283 .parent = &ck_dpll1, 284 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 285 RATE_CKCTL, 286 .enable_reg = (void __iomem *)ARM_CKCTL, 287 .enable_bit = EN_DSPCK, 288 .rate_offset = CKCTL_DSPDIV_OFFSET, 289 .recalc = &omap1_ckctl_recalc, 290 .enable = &omap1_clk_enable_generic, 291 .disable = &omap1_clk_disable_generic, 292 }; 293 294 static struct clk dspmmu_ck = { 295 .name = "dspmmu_ck", 296 .parent = &ck_dpll1, 297 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 298 RATE_CKCTL | ALWAYS_ENABLED, 299 .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 300 .recalc = &omap1_ckctl_recalc, 301 .enable = &omap1_clk_enable_generic, 302 .disable = &omap1_clk_disable_generic, 303 }; 304 305 static struct clk dspper_ck = { 306 .name = "dspper_ck", 307 .parent = &ck_dpll1, 308 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 309 RATE_CKCTL | VIRTUAL_IO_ADDRESS, 310 .enable_reg = (void __iomem *)DSP_IDLECT2, 311 .enable_bit = EN_PERCK, 312 .rate_offset = CKCTL_PERDIV_OFFSET, 313 .recalc = &omap1_ckctl_recalc_dsp_domain, 314 .set_rate = &omap1_clk_set_rate_dsp_domain, 315 .enable = &omap1_clk_enable_dsp_domain, 316 .disable = &omap1_clk_disable_dsp_domain, 317 }; 318 319 static struct clk dspxor_ck = { 320 .name = "dspxor_ck", 321 .parent = &ck_ref, 322 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 323 VIRTUAL_IO_ADDRESS, 324 .enable_reg = (void __iomem *)DSP_IDLECT2, 325 .enable_bit = EN_XORPCK, 326 .recalc = &followparent_recalc, 327 .enable = &omap1_clk_enable_dsp_domain, 328 .disable = &omap1_clk_disable_dsp_domain, 329 }; 330 331 static struct clk dsptim_ck = { 332 .name = "dsptim_ck", 333 .parent = &ck_ref, 334 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 335 VIRTUAL_IO_ADDRESS, 336 .enable_reg = (void __iomem *)DSP_IDLECT2, 337 .enable_bit = EN_DSPTIMCK, 338 .recalc = &followparent_recalc, 339 .enable = &omap1_clk_enable_dsp_domain, 340 .disable = &omap1_clk_disable_dsp_domain, 341 }; 342 343 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ 344 static struct arm_idlect1_clk tc_ck = { 345 .clk = { 346 .name = "tc_ck", 347 .parent = &ck_dpll1, 348 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 349 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | 350 RATE_CKCTL | RATE_PROPAGATES | 351 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, 352 .rate_offset = CKCTL_TCDIV_OFFSET, 353 .recalc = &omap1_ckctl_recalc, 354 .enable = &omap1_clk_enable_generic, 355 .disable = &omap1_clk_disable_generic, 356 }, 357 .idlect_shift = 6, 358 }; 359 360 static struct clk arminth_ck1510 = { 361 .name = "arminth_ck", 362 .parent = &tc_ck.clk, 363 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 364 ALWAYS_ENABLED, 365 .recalc = &followparent_recalc, 366 /* Note: On 1510 the frequency follows TC_CK 367 * 368 * 16xx version is in MPU clocks. 369 */ 370 .enable = &omap1_clk_enable_generic, 371 .disable = &omap1_clk_disable_generic, 372 }; 373 374 static struct clk tipb_ck = { 375 /* No-idle controlled by "tc_ck" */ 376 .name = "tibp_ck", 377 .parent = &tc_ck.clk, 378 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 379 ALWAYS_ENABLED, 380 .recalc = &followparent_recalc, 381 .enable = &omap1_clk_enable_generic, 382 .disable = &omap1_clk_disable_generic, 383 }; 384 385 static struct clk l3_ocpi_ck = { 386 /* No-idle controlled by "tc_ck" */ 387 .name = "l3_ocpi_ck", 388 .parent = &tc_ck.clk, 389 .flags = CLOCK_IN_OMAP16XX, 390 .enable_reg = (void __iomem *)ARM_IDLECT3, 391 .enable_bit = EN_OCPI_CK, 392 .recalc = &followparent_recalc, 393 .enable = &omap1_clk_enable_generic, 394 .disable = &omap1_clk_disable_generic, 395 }; 396 397 static struct clk tc1_ck = { 398 .name = "tc1_ck", 399 .parent = &tc_ck.clk, 400 .flags = CLOCK_IN_OMAP16XX, 401 .enable_reg = (void __iomem *)ARM_IDLECT3, 402 .enable_bit = EN_TC1_CK, 403 .recalc = &followparent_recalc, 404 .enable = &omap1_clk_enable_generic, 405 .disable = &omap1_clk_disable_generic, 406 }; 407 408 static struct clk tc2_ck = { 409 .name = "tc2_ck", 410 .parent = &tc_ck.clk, 411 .flags = CLOCK_IN_OMAP16XX, 412 .enable_reg = (void __iomem *)ARM_IDLECT3, 413 .enable_bit = EN_TC2_CK, 414 .recalc = &followparent_recalc, 415 .enable = &omap1_clk_enable_generic, 416 .disable = &omap1_clk_disable_generic, 417 }; 418 419 static struct clk dma_ck = { 420 /* No-idle controlled by "tc_ck" */ 421 .name = "dma_ck", 422 .parent = &tc_ck.clk, 423 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 424 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 425 .recalc = &followparent_recalc, 426 .enable = &omap1_clk_enable_generic, 427 .disable = &omap1_clk_disable_generic, 428 }; 429 430 static struct clk dma_lcdfree_ck = { 431 .name = "dma_lcdfree_ck", 432 .parent = &tc_ck.clk, 433 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 434 .recalc = &followparent_recalc, 435 .enable = &omap1_clk_enable_generic, 436 .disable = &omap1_clk_disable_generic, 437 }; 438 439 static struct arm_idlect1_clk api_ck = { 440 .clk = { 441 .name = "api_ck", 442 .parent = &tc_ck.clk, 443 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 444 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 445 .enable_reg = (void __iomem *)ARM_IDLECT2, 446 .enable_bit = EN_APICK, 447 .recalc = &followparent_recalc, 448 .enable = &omap1_clk_enable_generic, 449 .disable = &omap1_clk_disable_generic, 450 }, 451 .idlect_shift = 8, 452 }; 453 454 static struct arm_idlect1_clk lb_ck = { 455 .clk = { 456 .name = "lb_ck", 457 .parent = &tc_ck.clk, 458 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 459 CLOCK_IDLE_CONTROL, 460 .enable_reg = (void __iomem *)ARM_IDLECT2, 461 .enable_bit = EN_LBCK, 462 .recalc = &followparent_recalc, 463 .enable = &omap1_clk_enable_generic, 464 .disable = &omap1_clk_disable_generic, 465 }, 466 .idlect_shift = 4, 467 }; 468 469 static struct clk rhea1_ck = { 470 .name = "rhea1_ck", 471 .parent = &tc_ck.clk, 472 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 473 .recalc = &followparent_recalc, 474 .enable = &omap1_clk_enable_generic, 475 .disable = &omap1_clk_disable_generic, 476 }; 477 478 static struct clk rhea2_ck = { 479 .name = "rhea2_ck", 480 .parent = &tc_ck.clk, 481 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 482 .recalc = &followparent_recalc, 483 .enable = &omap1_clk_enable_generic, 484 .disable = &omap1_clk_disable_generic, 485 }; 486 487 static struct clk lcd_ck_16xx = { 488 .name = "lcd_ck", 489 .parent = &ck_dpll1, 490 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, 491 .enable_reg = (void __iomem *)ARM_IDLECT2, 492 .enable_bit = EN_LCDCK, 493 .rate_offset = CKCTL_LCDDIV_OFFSET, 494 .recalc = &omap1_ckctl_recalc, 495 .enable = &omap1_clk_enable_generic, 496 .disable = &omap1_clk_disable_generic, 497 }; 498 499 static struct arm_idlect1_clk lcd_ck_1510 = { 500 .clk = { 501 .name = "lcd_ck", 502 .parent = &ck_dpll1, 503 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 504 RATE_CKCTL | CLOCK_IDLE_CONTROL, 505 .enable_reg = (void __iomem *)ARM_IDLECT2, 506 .enable_bit = EN_LCDCK, 507 .rate_offset = CKCTL_LCDDIV_OFFSET, 508 .recalc = &omap1_ckctl_recalc, 509 .enable = &omap1_clk_enable_generic, 510 .disable = &omap1_clk_disable_generic, 511 }, 512 .idlect_shift = 3, 513 }; 514 515 static struct clk uart1_1510 = { 516 .name = "uart1_ck", 517 /* Direct from ULPD, no real parent */ 518 .parent = &armper_ck.clk, 519 .rate = 12000000, 520 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 521 ENABLE_REG_32BIT | ALWAYS_ENABLED | 522 CLOCK_NO_IDLE_PARENT, 523 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 524 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ 525 .set_rate = &omap1_set_uart_rate, 526 .recalc = &omap1_uart_recalc, 527 .enable = &omap1_clk_enable_generic, 528 .disable = &omap1_clk_disable_generic, 529 }; 530 531 static struct uart_clk uart1_16xx = { 532 .clk = { 533 .name = "uart1_ck", 534 /* Direct from ULPD, no real parent */ 535 .parent = &armper_ck.clk, 536 .rate = 48000000, 537 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 538 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 539 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 540 .enable_bit = 29, 541 .enable = &omap1_clk_enable_uart_functional, 542 .disable = &omap1_clk_disable_uart_functional, 543 }, 544 .sysc_addr = 0xfffb0054, 545 }; 546 547 static struct clk uart2_ck = { 548 .name = "uart2_ck", 549 /* Direct from ULPD, no real parent */ 550 .parent = &armper_ck.clk, 551 .rate = 12000000, 552 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 553 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | 554 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, 555 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 556 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ 557 .set_rate = &omap1_set_uart_rate, 558 .recalc = &omap1_uart_recalc, 559 .enable = &omap1_clk_enable_generic, 560 .disable = &omap1_clk_disable_generic, 561 }; 562 563 static struct clk uart3_1510 = { 564 .name = "uart3_ck", 565 /* Direct from ULPD, no real parent */ 566 .parent = &armper_ck.clk, 567 .rate = 12000000, 568 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 569 ENABLE_REG_32BIT | ALWAYS_ENABLED | 570 CLOCK_NO_IDLE_PARENT, 571 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 572 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ 573 .set_rate = &omap1_set_uart_rate, 574 .recalc = &omap1_uart_recalc, 575 .enable = &omap1_clk_enable_generic, 576 .disable = &omap1_clk_disable_generic, 577 }; 578 579 static struct uart_clk uart3_16xx = { 580 .clk = { 581 .name = "uart3_ck", 582 /* Direct from ULPD, no real parent */ 583 .parent = &armper_ck.clk, 584 .rate = 48000000, 585 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 586 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 587 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 588 .enable_bit = 31, 589 .enable = &omap1_clk_enable_uart_functional, 590 .disable = &omap1_clk_disable_uart_functional, 591 }, 592 .sysc_addr = 0xfffb9854, 593 }; 594 595 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 596 .name = "usb_clko", 597 /* Direct from ULPD, no parent */ 598 .rate = 6000000, 599 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 600 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT, 601 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, 602 .enable_bit = USB_MCLK_EN_BIT, 603 .enable = &omap1_clk_enable_generic, 604 .disable = &omap1_clk_disable_generic, 605 }; 606 607 static struct clk usb_hhc_ck1510 = { 608 .name = "usb_hhc_ck", 609 /* Direct from ULPD, no parent */ 610 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 611 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 612 RATE_FIXED | ENABLE_REG_32BIT, 613 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 614 .enable_bit = USB_HOST_HHC_UHOST_EN, 615 .enable = &omap1_clk_enable_generic, 616 .disable = &omap1_clk_disable_generic, 617 }; 618 619 static struct clk usb_hhc_ck16xx = { 620 .name = "usb_hhc_ck", 621 /* Direct from ULPD, no parent */ 622 .rate = 48000000, 623 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 624 .flags = CLOCK_IN_OMAP16XX | 625 RATE_FIXED | ENABLE_REG_32BIT, 626 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, 627 .enable_bit = 8 /* UHOST_EN */, 628 .enable = &omap1_clk_enable_generic, 629 .disable = &omap1_clk_disable_generic, 630 }; 631 632 static struct clk usb_dc_ck = { 633 .name = "usb_dc_ck", 634 /* Direct from ULPD, no parent */ 635 .rate = 48000000, 636 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, 637 .enable_reg = (void __iomem *)SOFT_REQ_REG, 638 .enable_bit = 4, 639 .enable = &omap1_clk_enable_generic, 640 .disable = &omap1_clk_disable_generic, 641 }; 642 643 static struct clk mclk_1510 = { 644 .name = "mclk", 645 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 646 .rate = 12000000, 647 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 648 .enable_reg = (void __iomem *)SOFT_REQ_REG, 649 .enable_bit = 6, 650 .enable = &omap1_clk_enable_generic, 651 .disable = &omap1_clk_disable_generic, 652 }; 653 654 static struct clk mclk_16xx = { 655 .name = "mclk", 656 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 657 .flags = CLOCK_IN_OMAP16XX, 658 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, 659 .enable_bit = COM_ULPD_PLL_CLK_REQ, 660 .set_rate = &omap1_set_ext_clk_rate, 661 .round_rate = &omap1_round_ext_clk_rate, 662 .init = &omap1_init_ext_clk, 663 .enable = &omap1_clk_enable_generic, 664 .disable = &omap1_clk_disable_generic, 665 }; 666 667 static struct clk bclk_1510 = { 668 .name = "bclk", 669 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 670 .rate = 12000000, 671 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 672 .enable = &omap1_clk_enable_generic, 673 .disable = &omap1_clk_disable_generic, 674 }; 675 676 static struct clk bclk_16xx = { 677 .name = "bclk", 678 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 679 .flags = CLOCK_IN_OMAP16XX, 680 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, 681 .enable_bit = SWD_ULPD_PLL_CLK_REQ, 682 .set_rate = &omap1_set_ext_clk_rate, 683 .round_rate = &omap1_round_ext_clk_rate, 684 .init = &omap1_init_ext_clk, 685 .enable = &omap1_clk_enable_generic, 686 .disable = &omap1_clk_disable_generic, 687 }; 688 689 static struct clk mmc1_ck = { 690 .name = "mmc_ck", 691 .id = 1, 692 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 693 .parent = &armper_ck.clk, 694 .rate = 48000000, 695 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 696 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT | 697 CLOCK_NO_IDLE_PARENT, 698 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 699 .enable_bit = 23, 700 .enable = &omap1_clk_enable_generic, 701 .disable = &omap1_clk_disable_generic, 702 }; 703 704 static struct clk mmc2_ck = { 705 .name = "mmc_ck", 706 .id = 2, 707 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 708 .parent = &armper_ck.clk, 709 .rate = 48000000, 710 .flags = CLOCK_IN_OMAP16XX | 711 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 712 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 713 .enable_bit = 20, 714 .enable = &omap1_clk_enable_generic, 715 .disable = &omap1_clk_disable_generic, 716 }; 717 718 static struct clk virtual_ck_mpu = { 719 .name = "mpu", 720 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 721 CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED, 722 .parent = &arm_ck, /* Is smarter alias for */ 723 .recalc = &followparent_recalc, 724 .set_rate = &omap1_select_table_rate, 725 .round_rate = &omap1_round_to_table_rate, 726 .enable = &omap1_clk_enable_generic, 727 .disable = &omap1_clk_disable_generic, 728 }; 729 730 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK 731 remains active during MPU idle whenever this is enabled */ 732 static struct clk i2c_fck = { 733 .name = "i2c_fck", 734 .id = 1, 735 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 736 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | 737 ALWAYS_ENABLED, 738 .parent = &armxor_ck.clk, 739 .recalc = &followparent_recalc, 740 .enable = &omap1_clk_enable_generic, 741 .disable = &omap1_clk_disable_generic, 742 }; 743 744 static struct clk * onchip_clks[] = { 745 /* non-ULPD clocks */ 746 &ck_ref, 747 &ck_dpll1, 748 /* CK_GEN1 clocks */ 749 &ck_dpll1out.clk, 750 &arm_ck, 751 &armper_ck.clk, 752 &arm_gpio_ck, 753 &armxor_ck.clk, 754 &armtim_ck.clk, 755 &armwdt_ck.clk, 756 &arminth_ck1510, &arminth_ck16xx, 757 /* CK_GEN2 clocks */ 758 &dsp_ck, 759 &dspmmu_ck, 760 &dspper_ck, 761 &dspxor_ck, 762 &dsptim_ck, 763 /* CK_GEN3 clocks */ 764 &tc_ck.clk, 765 &tipb_ck, 766 &l3_ocpi_ck, 767 &tc1_ck, 768 &tc2_ck, 769 &dma_ck, 770 &dma_lcdfree_ck, 771 &api_ck.clk, 772 &lb_ck.clk, 773 &rhea1_ck, 774 &rhea2_ck, 775 &lcd_ck_16xx, 776 &lcd_ck_1510.clk, 777 /* ULPD clocks */ 778 &uart1_1510, 779 &uart1_16xx.clk, 780 &uart2_ck, 781 &uart3_1510, 782 &uart3_16xx.clk, 783 &usb_clko, 784 &usb_hhc_ck1510, &usb_hhc_ck16xx, 785 &usb_dc_ck, 786 &mclk_1510, &mclk_16xx, 787 &bclk_1510, &bclk_16xx, 788 &mmc1_ck, 789 &mmc2_ck, 790 /* Virtual clocks */ 791 &virtual_ck_mpu, 792 &i2c_fck, 793 }; 794 795 #endif 796