1 /* 2 * linux/arch/arm/mach-omap1/clock.c 3 * 4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 6 * 7 * Modified to use omap shared clock framework by 8 * Tony Lindgren <tony@atomide.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/io.h> 20 #include <linux/clkdev.h> 21 22 #include <asm/mach-types.h> 23 24 #include <plat/cpu.h> 25 #include <plat/usb.h> 26 #include <plat/clock.h> 27 #include <plat/sram.h> 28 #include <plat/clkdev_omap.h> 29 30 #include "clock.h" 31 #include "opp.h" 32 33 __u32 arm_idlect1_mask; 34 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; 35 36 /* 37 * Omap1 specific clock functions 38 */ 39 40 unsigned long omap1_uart_recalc(struct clk *clk) 41 { 42 unsigned int val = __raw_readl(clk->enable_reg); 43 return val & clk->enable_bit ? 48000000 : 12000000; 44 } 45 46 unsigned long omap1_sossi_recalc(struct clk *clk) 47 { 48 u32 div = omap_readl(MOD_CONF_CTRL_1); 49 50 div = (div >> 17) & 0x7; 51 div++; 52 53 return clk->parent->rate / div; 54 } 55 56 static void omap1_clk_allow_idle(struct clk *clk) 57 { 58 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 59 60 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 61 return; 62 63 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) 64 arm_idlect1_mask |= 1 << iclk->idlect_shift; 65 } 66 67 static void omap1_clk_deny_idle(struct clk *clk) 68 { 69 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 70 71 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 72 return; 73 74 if (iclk->no_idle_count++ == 0) 75 arm_idlect1_mask &= ~(1 << iclk->idlect_shift); 76 } 77 78 static __u16 verify_ckctl_value(__u16 newval) 79 { 80 /* This function checks for following limitations set 81 * by the hardware (all conditions must be true): 82 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 83 * ARM_CK >= TC_CK 84 * DSP_CK >= TC_CK 85 * DSPMMU_CK >= TC_CK 86 * 87 * In addition following rules are enforced: 88 * LCD_CK <= TC_CK 89 * ARMPER_CK <= TC_CK 90 * 91 * However, maximum frequencies are not checked for! 92 */ 93 __u8 per_exp; 94 __u8 lcd_exp; 95 __u8 arm_exp; 96 __u8 dsp_exp; 97 __u8 tc_exp; 98 __u8 dspmmu_exp; 99 100 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; 101 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; 102 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; 103 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; 104 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; 105 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; 106 107 if (dspmmu_exp < dsp_exp) 108 dspmmu_exp = dsp_exp; 109 if (dspmmu_exp > dsp_exp+1) 110 dspmmu_exp = dsp_exp+1; 111 if (tc_exp < arm_exp) 112 tc_exp = arm_exp; 113 if (tc_exp < dspmmu_exp) 114 tc_exp = dspmmu_exp; 115 if (tc_exp > lcd_exp) 116 lcd_exp = tc_exp; 117 if (tc_exp > per_exp) 118 per_exp = tc_exp; 119 120 newval &= 0xf000; 121 newval |= per_exp << CKCTL_PERDIV_OFFSET; 122 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; 123 newval |= arm_exp << CKCTL_ARMDIV_OFFSET; 124 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; 125 newval |= tc_exp << CKCTL_TCDIV_OFFSET; 126 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; 127 128 return newval; 129 } 130 131 static int calc_dsor_exp(struct clk *clk, unsigned long rate) 132 { 133 /* Note: If target frequency is too low, this function will return 4, 134 * which is invalid value. Caller must check for this value and act 135 * accordingly. 136 * 137 * Note: This function does not check for following limitations set 138 * by the hardware (all conditions must be true): 139 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 140 * ARM_CK >= TC_CK 141 * DSP_CK >= TC_CK 142 * DSPMMU_CK >= TC_CK 143 */ 144 unsigned long realrate; 145 struct clk * parent; 146 unsigned dsor_exp; 147 148 parent = clk->parent; 149 if (unlikely(parent == NULL)) 150 return -EIO; 151 152 realrate = parent->rate; 153 for (dsor_exp=0; dsor_exp<4; dsor_exp++) { 154 if (realrate <= rate) 155 break; 156 157 realrate /= 2; 158 } 159 160 return dsor_exp; 161 } 162 163 unsigned long omap1_ckctl_recalc(struct clk *clk) 164 { 165 /* Calculate divisor encoded as 2-bit exponent */ 166 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 167 168 return clk->parent->rate / dsor; 169 } 170 171 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) 172 { 173 int dsor; 174 175 /* Calculate divisor encoded as 2-bit exponent 176 * 177 * The clock control bits are in DSP domain, 178 * so api_ck is needed for access. 179 * Note that DSP_CKCTL virt addr = phys addr, so 180 * we must use __raw_readw() instead of omap_readw(). 181 */ 182 omap1_clk_enable(api_ck_p); 183 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); 184 omap1_clk_disable(api_ck_p); 185 186 return clk->parent->rate / dsor; 187 } 188 189 /* MPU virtual clock functions */ 190 int omap1_select_table_rate(struct clk *clk, unsigned long rate) 191 { 192 /* Find the highest supported frequency <= rate and switch to it */ 193 struct mpu_rate * ptr; 194 unsigned long dpll1_rate, ref_rate; 195 196 dpll1_rate = ck_dpll1_p->rate; 197 ref_rate = ck_ref_p->rate; 198 199 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 200 if (!(ptr->flags & cpu_mask)) 201 continue; 202 203 if (ptr->xtal != ref_rate) 204 continue; 205 206 /* Can check only after xtal frequency check */ 207 if (ptr->rate <= rate) 208 break; 209 } 210 211 if (!ptr->rate) 212 return -EINVAL; 213 214 /* 215 * In most cases we should not need to reprogram DPLL. 216 * Reprogramming the DPLL is tricky, it must be done from SRAM. 217 */ 218 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 219 220 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ 221 ck_dpll1_p->rate = ptr->pll_rate; 222 223 return 0; 224 } 225 226 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) 227 { 228 int dsor_exp; 229 u16 regval; 230 231 dsor_exp = calc_dsor_exp(clk, rate); 232 if (dsor_exp > 3) 233 dsor_exp = -EINVAL; 234 if (dsor_exp < 0) 235 return dsor_exp; 236 237 regval = __raw_readw(DSP_CKCTL); 238 regval &= ~(3 << clk->rate_offset); 239 regval |= dsor_exp << clk->rate_offset; 240 __raw_writew(regval, DSP_CKCTL); 241 clk->rate = clk->parent->rate / (1 << dsor_exp); 242 243 return 0; 244 } 245 246 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) 247 { 248 int dsor_exp = calc_dsor_exp(clk, rate); 249 if (dsor_exp < 0) 250 return dsor_exp; 251 if (dsor_exp > 3) 252 dsor_exp = 3; 253 return clk->parent->rate / (1 << dsor_exp); 254 } 255 256 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) 257 { 258 int dsor_exp; 259 u16 regval; 260 261 dsor_exp = calc_dsor_exp(clk, rate); 262 if (dsor_exp > 3) 263 dsor_exp = -EINVAL; 264 if (dsor_exp < 0) 265 return dsor_exp; 266 267 regval = omap_readw(ARM_CKCTL); 268 regval &= ~(3 << clk->rate_offset); 269 regval |= dsor_exp << clk->rate_offset; 270 regval = verify_ckctl_value(regval); 271 omap_writew(regval, ARM_CKCTL); 272 clk->rate = clk->parent->rate / (1 << dsor_exp); 273 return 0; 274 } 275 276 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) 277 { 278 /* Find the highest supported frequency <= rate */ 279 struct mpu_rate * ptr; 280 long highest_rate; 281 unsigned long ref_rate; 282 283 ref_rate = ck_ref_p->rate; 284 285 highest_rate = -EINVAL; 286 287 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 288 if (!(ptr->flags & cpu_mask)) 289 continue; 290 291 if (ptr->xtal != ref_rate) 292 continue; 293 294 highest_rate = ptr->rate; 295 296 /* Can check only after xtal frequency check */ 297 if (ptr->rate <= rate) 298 break; 299 } 300 301 return highest_rate; 302 } 303 304 static unsigned calc_ext_dsor(unsigned long rate) 305 { 306 unsigned dsor; 307 308 /* MCLK and BCLK divisor selection is not linear: 309 * freq = 96MHz / dsor 310 * 311 * RATIO_SEL range: dsor <-> RATIO_SEL 312 * 0..6: (RATIO_SEL+2) <-> (dsor-2) 313 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) 314 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 315 * can not be used. 316 */ 317 for (dsor = 2; dsor < 96; ++dsor) { 318 if ((dsor & 1) && dsor > 8) 319 continue; 320 if (rate >= 96000000 / dsor) 321 break; 322 } 323 return dsor; 324 } 325 326 /* XXX Only needed on 1510 */ 327 int omap1_set_uart_rate(struct clk *clk, unsigned long rate) 328 { 329 unsigned int val; 330 331 val = __raw_readl(clk->enable_reg); 332 if (rate == 12000000) 333 val &= ~(1 << clk->enable_bit); 334 else if (rate == 48000000) 335 val |= (1 << clk->enable_bit); 336 else 337 return -EINVAL; 338 __raw_writel(val, clk->enable_reg); 339 clk->rate = rate; 340 341 return 0; 342 } 343 344 /* External clock (MCLK & BCLK) functions */ 345 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) 346 { 347 unsigned dsor; 348 __u16 ratio_bits; 349 350 dsor = calc_ext_dsor(rate); 351 clk->rate = 96000000 / dsor; 352 if (dsor > 8) 353 ratio_bits = ((dsor - 8) / 2 + 6) << 2; 354 else 355 ratio_bits = (dsor - 2) << 2; 356 357 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; 358 __raw_writew(ratio_bits, clk->enable_reg); 359 360 return 0; 361 } 362 363 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) 364 { 365 u32 l; 366 int div; 367 unsigned long p_rate; 368 369 p_rate = clk->parent->rate; 370 /* Round towards slower frequency */ 371 div = (p_rate + rate - 1) / rate; 372 div--; 373 if (div < 0 || div > 7) 374 return -EINVAL; 375 376 l = omap_readl(MOD_CONF_CTRL_1); 377 l &= ~(7 << 17); 378 l |= div << 17; 379 omap_writel(l, MOD_CONF_CTRL_1); 380 381 clk->rate = p_rate / (div + 1); 382 383 return 0; 384 } 385 386 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) 387 { 388 return 96000000 / calc_ext_dsor(rate); 389 } 390 391 void omap1_init_ext_clk(struct clk *clk) 392 { 393 unsigned dsor; 394 __u16 ratio_bits; 395 396 /* Determine current rate and ensure clock is based on 96MHz APLL */ 397 ratio_bits = __raw_readw(clk->enable_reg) & ~1; 398 __raw_writew(ratio_bits, clk->enable_reg); 399 400 ratio_bits = (ratio_bits & 0xfc) >> 2; 401 if (ratio_bits > 6) 402 dsor = (ratio_bits - 6) * 2 + 8; 403 else 404 dsor = ratio_bits + 2; 405 406 clk-> rate = 96000000 / dsor; 407 } 408 409 int omap1_clk_enable(struct clk *clk) 410 { 411 int ret = 0; 412 413 if (clk->usecount++ == 0) { 414 if (clk->parent) { 415 ret = omap1_clk_enable(clk->parent); 416 if (ret) 417 goto err; 418 419 if (clk->flags & CLOCK_NO_IDLE_PARENT) 420 omap1_clk_deny_idle(clk->parent); 421 } 422 423 ret = clk->ops->enable(clk); 424 if (ret) { 425 if (clk->parent) 426 omap1_clk_disable(clk->parent); 427 goto err; 428 } 429 } 430 return ret; 431 432 err: 433 clk->usecount--; 434 return ret; 435 } 436 437 void omap1_clk_disable(struct clk *clk) 438 { 439 if (clk->usecount > 0 && !(--clk->usecount)) { 440 clk->ops->disable(clk); 441 if (likely(clk->parent)) { 442 omap1_clk_disable(clk->parent); 443 if (clk->flags & CLOCK_NO_IDLE_PARENT) 444 omap1_clk_allow_idle(clk->parent); 445 } 446 } 447 } 448 449 static int omap1_clk_enable_generic(struct clk *clk) 450 { 451 __u16 regval16; 452 __u32 regval32; 453 454 if (unlikely(clk->enable_reg == NULL)) { 455 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 456 clk->name); 457 return -EINVAL; 458 } 459 460 if (clk->flags & ENABLE_REG_32BIT) { 461 regval32 = __raw_readl(clk->enable_reg); 462 regval32 |= (1 << clk->enable_bit); 463 __raw_writel(regval32, clk->enable_reg); 464 } else { 465 regval16 = __raw_readw(clk->enable_reg); 466 regval16 |= (1 << clk->enable_bit); 467 __raw_writew(regval16, clk->enable_reg); 468 } 469 470 return 0; 471 } 472 473 static void omap1_clk_disable_generic(struct clk *clk) 474 { 475 __u16 regval16; 476 __u32 regval32; 477 478 if (clk->enable_reg == NULL) 479 return; 480 481 if (clk->flags & ENABLE_REG_32BIT) { 482 regval32 = __raw_readl(clk->enable_reg); 483 regval32 &= ~(1 << clk->enable_bit); 484 __raw_writel(regval32, clk->enable_reg); 485 } else { 486 regval16 = __raw_readw(clk->enable_reg); 487 regval16 &= ~(1 << clk->enable_bit); 488 __raw_writew(regval16, clk->enable_reg); 489 } 490 } 491 492 const struct clkops clkops_generic = { 493 .enable = omap1_clk_enable_generic, 494 .disable = omap1_clk_disable_generic, 495 }; 496 497 static int omap1_clk_enable_dsp_domain(struct clk *clk) 498 { 499 int retval; 500 501 retval = omap1_clk_enable(api_ck_p); 502 if (!retval) { 503 retval = omap1_clk_enable_generic(clk); 504 omap1_clk_disable(api_ck_p); 505 } 506 507 return retval; 508 } 509 510 static void omap1_clk_disable_dsp_domain(struct clk *clk) 511 { 512 if (omap1_clk_enable(api_ck_p) == 0) { 513 omap1_clk_disable_generic(clk); 514 omap1_clk_disable(api_ck_p); 515 } 516 } 517 518 const struct clkops clkops_dspck = { 519 .enable = omap1_clk_enable_dsp_domain, 520 .disable = omap1_clk_disable_dsp_domain, 521 }; 522 523 /* XXX SYSC register handling does not belong in the clock framework */ 524 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) 525 { 526 int ret; 527 struct uart_clk *uclk; 528 529 ret = omap1_clk_enable_generic(clk); 530 if (ret == 0) { 531 /* Set smart idle acknowledgement mode */ 532 uclk = (struct uart_clk *)clk; 533 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, 534 uclk->sysc_addr); 535 } 536 537 return ret; 538 } 539 540 /* XXX SYSC register handling does not belong in the clock framework */ 541 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk) 542 { 543 struct uart_clk *uclk; 544 545 /* Set force idle acknowledgement mode */ 546 uclk = (struct uart_clk *)clk; 547 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); 548 549 omap1_clk_disable_generic(clk); 550 } 551 552 /* XXX SYSC register handling does not belong in the clock framework */ 553 const struct clkops clkops_uart_16xx = { 554 .enable = omap1_clk_enable_uart_functional_16xx, 555 .disable = omap1_clk_disable_uart_functional_16xx, 556 }; 557 558 long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 559 { 560 if (clk->round_rate != NULL) 561 return clk->round_rate(clk, rate); 562 563 return clk->rate; 564 } 565 566 int omap1_clk_set_rate(struct clk *clk, unsigned long rate) 567 { 568 int ret = -EINVAL; 569 570 if (clk->set_rate) 571 ret = clk->set_rate(clk, rate); 572 return ret; 573 } 574 575 /* 576 * Omap1 clock reset and init functions 577 */ 578 579 #ifdef CONFIG_OMAP_RESET_CLOCKS 580 581 void omap1_clk_disable_unused(struct clk *clk) 582 { 583 __u32 regval32; 584 585 /* Clocks in the DSP domain need api_ck. Just assume bootloader 586 * has not enabled any DSP clocks */ 587 if (clk->enable_reg == DSP_IDLECT2) { 588 printk(KERN_INFO "Skipping reset check for DSP domain " 589 "clock \"%s\"\n", clk->name); 590 return; 591 } 592 593 /* Is the clock already disabled? */ 594 if (clk->flags & ENABLE_REG_32BIT) 595 regval32 = __raw_readl(clk->enable_reg); 596 else 597 regval32 = __raw_readw(clk->enable_reg); 598 599 if ((regval32 & (1 << clk->enable_bit)) == 0) 600 return; 601 602 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); 603 clk->ops->disable(clk); 604 printk(" done\n"); 605 } 606 607 #endif 608