1 /* 2 * linux/arch/arm/mach-omap1/clock.c 3 * 4 * Copyright (C) 2004 - 2005 Nokia corporation 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 6 * 7 * Modified to use omap shared clock framework by 8 * Tony Lindgren <tony@atomide.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/list.h> 17 #include <linux/errno.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 22 #include <asm/mach-types.h> 23 #include <asm/clkdev.h> 24 25 #include <plat/cpu.h> 26 #include <plat/usb.h> 27 #include <plat/clock.h> 28 #include <plat/sram.h> 29 30 static const struct clkops clkops_generic; 31 static const struct clkops clkops_uart; 32 static const struct clkops clkops_dspck; 33 34 #include "clock.h" 35 36 static int clk_omap1_dummy_enable(struct clk *clk) 37 { 38 return 0; 39 } 40 41 static void clk_omap1_dummy_disable(struct clk *clk) 42 { 43 } 44 45 static const struct clkops clkops_dummy = { 46 .enable = clk_omap1_dummy_enable, 47 .disable = clk_omap1_dummy_disable, 48 }; 49 50 static struct clk dummy_ck = { 51 .name = "dummy", 52 .ops = &clkops_dummy, 53 .flags = RATE_FIXED, 54 }; 55 56 struct omap_clk { 57 u32 cpu; 58 struct clk_lookup lk; 59 }; 60 61 #define CLK(dev, con, ck, cp) \ 62 { \ 63 .cpu = cp, \ 64 .lk = { \ 65 .dev_id = dev, \ 66 .con_id = con, \ 67 .clk = ck, \ 68 }, \ 69 } 70 71 #define CK_310 (1 << 0) 72 #define CK_7XX (1 << 1) 73 #define CK_1510 (1 << 2) 74 #define CK_16XX (1 << 3) 75 76 static struct omap_clk omap_clks[] = { 77 /* non-ULPD clocks */ 78 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), 79 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), 80 /* CK_GEN1 clocks */ 81 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), 82 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), 83 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), 84 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 85 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), 86 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 87 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), 88 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), 89 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), 90 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), 91 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), 92 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), 93 /* CK_GEN2 clocks */ 94 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), 95 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), 96 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), 97 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 98 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), 99 /* CK_GEN3 clocks */ 100 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 101 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), 102 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), 103 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), 104 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), 105 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), 106 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), 107 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), 108 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), 109 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), 110 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), 111 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), 112 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), 113 /* ULPD clocks */ 114 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), 115 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), 116 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), 117 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), 118 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), 119 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), 120 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), 121 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), 122 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), 123 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), 124 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), 125 CLK(NULL, "mclk", &mclk_16xx, CK_16XX), 126 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), 127 CLK(NULL, "bclk", &bclk_16xx, CK_16XX), 128 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), 129 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), 130 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 131 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), 132 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), 133 /* Virtual clocks */ 134 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), 135 CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), 136 CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), 137 CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), 138 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), 139 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), 140 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), 141 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), 142 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), 143 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), 144 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), 145 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 146 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 147 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 148 }; 149 150 static int omap1_clk_enable_generic(struct clk * clk); 151 static int omap1_clk_enable(struct clk *clk); 152 static void omap1_clk_disable_generic(struct clk * clk); 153 static void omap1_clk_disable(struct clk *clk); 154 155 __u32 arm_idlect1_mask; 156 157 /*------------------------------------------------------------------------- 158 * Omap1 specific clock functions 159 *-------------------------------------------------------------------------*/ 160 161 static unsigned long omap1_watchdog_recalc(struct clk *clk) 162 { 163 return clk->parent->rate / 14; 164 } 165 166 static unsigned long omap1_uart_recalc(struct clk *clk) 167 { 168 unsigned int val = __raw_readl(clk->enable_reg); 169 return val & clk->enable_bit ? 48000000 : 12000000; 170 } 171 172 static unsigned long omap1_sossi_recalc(struct clk *clk) 173 { 174 u32 div = omap_readl(MOD_CONF_CTRL_1); 175 176 div = (div >> 17) & 0x7; 177 div++; 178 179 return clk->parent->rate / div; 180 } 181 182 static int omap1_clk_enable_dsp_domain(struct clk *clk) 183 { 184 int retval; 185 186 retval = omap1_clk_enable(&api_ck.clk); 187 if (!retval) { 188 retval = omap1_clk_enable_generic(clk); 189 omap1_clk_disable(&api_ck.clk); 190 } 191 192 return retval; 193 } 194 195 static void omap1_clk_disable_dsp_domain(struct clk *clk) 196 { 197 if (omap1_clk_enable(&api_ck.clk) == 0) { 198 omap1_clk_disable_generic(clk); 199 omap1_clk_disable(&api_ck.clk); 200 } 201 } 202 203 static const struct clkops clkops_dspck = { 204 .enable = &omap1_clk_enable_dsp_domain, 205 .disable = &omap1_clk_disable_dsp_domain, 206 }; 207 208 static int omap1_clk_enable_uart_functional(struct clk *clk) 209 { 210 int ret; 211 struct uart_clk *uclk; 212 213 ret = omap1_clk_enable_generic(clk); 214 if (ret == 0) { 215 /* Set smart idle acknowledgement mode */ 216 uclk = (struct uart_clk *)clk; 217 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, 218 uclk->sysc_addr); 219 } 220 221 return ret; 222 } 223 224 static void omap1_clk_disable_uart_functional(struct clk *clk) 225 { 226 struct uart_clk *uclk; 227 228 /* Set force idle acknowledgement mode */ 229 uclk = (struct uart_clk *)clk; 230 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); 231 232 omap1_clk_disable_generic(clk); 233 } 234 235 static const struct clkops clkops_uart = { 236 .enable = &omap1_clk_enable_uart_functional, 237 .disable = &omap1_clk_disable_uart_functional, 238 }; 239 240 static void omap1_clk_allow_idle(struct clk *clk) 241 { 242 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 243 244 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 245 return; 246 247 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) 248 arm_idlect1_mask |= 1 << iclk->idlect_shift; 249 } 250 251 static void omap1_clk_deny_idle(struct clk *clk) 252 { 253 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 254 255 if (!(clk->flags & CLOCK_IDLE_CONTROL)) 256 return; 257 258 if (iclk->no_idle_count++ == 0) 259 arm_idlect1_mask &= ~(1 << iclk->idlect_shift); 260 } 261 262 static __u16 verify_ckctl_value(__u16 newval) 263 { 264 /* This function checks for following limitations set 265 * by the hardware (all conditions must be true): 266 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 267 * ARM_CK >= TC_CK 268 * DSP_CK >= TC_CK 269 * DSPMMU_CK >= TC_CK 270 * 271 * In addition following rules are enforced: 272 * LCD_CK <= TC_CK 273 * ARMPER_CK <= TC_CK 274 * 275 * However, maximum frequencies are not checked for! 276 */ 277 __u8 per_exp; 278 __u8 lcd_exp; 279 __u8 arm_exp; 280 __u8 dsp_exp; 281 __u8 tc_exp; 282 __u8 dspmmu_exp; 283 284 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; 285 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; 286 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; 287 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; 288 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; 289 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; 290 291 if (dspmmu_exp < dsp_exp) 292 dspmmu_exp = dsp_exp; 293 if (dspmmu_exp > dsp_exp+1) 294 dspmmu_exp = dsp_exp+1; 295 if (tc_exp < arm_exp) 296 tc_exp = arm_exp; 297 if (tc_exp < dspmmu_exp) 298 tc_exp = dspmmu_exp; 299 if (tc_exp > lcd_exp) 300 lcd_exp = tc_exp; 301 if (tc_exp > per_exp) 302 per_exp = tc_exp; 303 304 newval &= 0xf000; 305 newval |= per_exp << CKCTL_PERDIV_OFFSET; 306 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; 307 newval |= arm_exp << CKCTL_ARMDIV_OFFSET; 308 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; 309 newval |= tc_exp << CKCTL_TCDIV_OFFSET; 310 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; 311 312 return newval; 313 } 314 315 static int calc_dsor_exp(struct clk *clk, unsigned long rate) 316 { 317 /* Note: If target frequency is too low, this function will return 4, 318 * which is invalid value. Caller must check for this value and act 319 * accordingly. 320 * 321 * Note: This function does not check for following limitations set 322 * by the hardware (all conditions must be true): 323 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 324 * ARM_CK >= TC_CK 325 * DSP_CK >= TC_CK 326 * DSPMMU_CK >= TC_CK 327 */ 328 unsigned long realrate; 329 struct clk * parent; 330 unsigned dsor_exp; 331 332 parent = clk->parent; 333 if (unlikely(parent == NULL)) 334 return -EIO; 335 336 realrate = parent->rate; 337 for (dsor_exp=0; dsor_exp<4; dsor_exp++) { 338 if (realrate <= rate) 339 break; 340 341 realrate /= 2; 342 } 343 344 return dsor_exp; 345 } 346 347 static unsigned long omap1_ckctl_recalc(struct clk *clk) 348 { 349 /* Calculate divisor encoded as 2-bit exponent */ 350 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 351 352 return clk->parent->rate / dsor; 353 } 354 355 static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) 356 { 357 int dsor; 358 359 /* Calculate divisor encoded as 2-bit exponent 360 * 361 * The clock control bits are in DSP domain, 362 * so api_ck is needed for access. 363 * Note that DSP_CKCTL virt addr = phys addr, so 364 * we must use __raw_readw() instead of omap_readw(). 365 */ 366 omap1_clk_enable(&api_ck.clk); 367 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); 368 omap1_clk_disable(&api_ck.clk); 369 370 return clk->parent->rate / dsor; 371 } 372 373 /* MPU virtual clock functions */ 374 static int omap1_select_table_rate(struct clk * clk, unsigned long rate) 375 { 376 /* Find the highest supported frequency <= rate and switch to it */ 377 struct mpu_rate * ptr; 378 379 if (clk != &virtual_ck_mpu) 380 return -EINVAL; 381 382 for (ptr = rate_table; ptr->rate; ptr++) { 383 if (ptr->xtal != ck_ref.rate) 384 continue; 385 386 /* DPLL1 cannot be reprogrammed without risking system crash */ 387 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) 388 continue; 389 390 /* Can check only after xtal frequency check */ 391 if (ptr->rate <= rate) 392 break; 393 } 394 395 if (!ptr->rate) 396 return -EINVAL; 397 398 /* 399 * In most cases we should not need to reprogram DPLL. 400 * Reprogramming the DPLL is tricky, it must be done from SRAM. 401 * (on 730, bit 13 must always be 1) 402 */ 403 if (cpu_is_omap7xx()) 404 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); 405 else 406 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 407 408 ck_dpll1.rate = ptr->pll_rate; 409 return 0; 410 } 411 412 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) 413 { 414 int dsor_exp; 415 u16 regval; 416 417 dsor_exp = calc_dsor_exp(clk, rate); 418 if (dsor_exp > 3) 419 dsor_exp = -EINVAL; 420 if (dsor_exp < 0) 421 return dsor_exp; 422 423 regval = __raw_readw(DSP_CKCTL); 424 regval &= ~(3 << clk->rate_offset); 425 regval |= dsor_exp << clk->rate_offset; 426 __raw_writew(regval, DSP_CKCTL); 427 clk->rate = clk->parent->rate / (1 << dsor_exp); 428 429 return 0; 430 } 431 432 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) 433 { 434 int dsor_exp = calc_dsor_exp(clk, rate); 435 if (dsor_exp < 0) 436 return dsor_exp; 437 if (dsor_exp > 3) 438 dsor_exp = 3; 439 return clk->parent->rate / (1 << dsor_exp); 440 } 441 442 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) 443 { 444 int dsor_exp; 445 u16 regval; 446 447 dsor_exp = calc_dsor_exp(clk, rate); 448 if (dsor_exp > 3) 449 dsor_exp = -EINVAL; 450 if (dsor_exp < 0) 451 return dsor_exp; 452 453 regval = omap_readw(ARM_CKCTL); 454 regval &= ~(3 << clk->rate_offset); 455 regval |= dsor_exp << clk->rate_offset; 456 regval = verify_ckctl_value(regval); 457 omap_writew(regval, ARM_CKCTL); 458 clk->rate = clk->parent->rate / (1 << dsor_exp); 459 return 0; 460 } 461 462 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) 463 { 464 /* Find the highest supported frequency <= rate */ 465 struct mpu_rate * ptr; 466 long highest_rate; 467 468 if (clk != &virtual_ck_mpu) 469 return -EINVAL; 470 471 highest_rate = -EINVAL; 472 473 for (ptr = rate_table; ptr->rate; ptr++) { 474 if (ptr->xtal != ck_ref.rate) 475 continue; 476 477 highest_rate = ptr->rate; 478 479 /* Can check only after xtal frequency check */ 480 if (ptr->rate <= rate) 481 break; 482 } 483 484 return highest_rate; 485 } 486 487 static unsigned calc_ext_dsor(unsigned long rate) 488 { 489 unsigned dsor; 490 491 /* MCLK and BCLK divisor selection is not linear: 492 * freq = 96MHz / dsor 493 * 494 * RATIO_SEL range: dsor <-> RATIO_SEL 495 * 0..6: (RATIO_SEL+2) <-> (dsor-2) 496 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) 497 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 498 * can not be used. 499 */ 500 for (dsor = 2; dsor < 96; ++dsor) { 501 if ((dsor & 1) && dsor > 8) 502 continue; 503 if (rate >= 96000000 / dsor) 504 break; 505 } 506 return dsor; 507 } 508 509 /* Only needed on 1510 */ 510 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) 511 { 512 unsigned int val; 513 514 val = __raw_readl(clk->enable_reg); 515 if (rate == 12000000) 516 val &= ~(1 << clk->enable_bit); 517 else if (rate == 48000000) 518 val |= (1 << clk->enable_bit); 519 else 520 return -EINVAL; 521 __raw_writel(val, clk->enable_reg); 522 clk->rate = rate; 523 524 return 0; 525 } 526 527 /* External clock (MCLK & BCLK) functions */ 528 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) 529 { 530 unsigned dsor; 531 __u16 ratio_bits; 532 533 dsor = calc_ext_dsor(rate); 534 clk->rate = 96000000 / dsor; 535 if (dsor > 8) 536 ratio_bits = ((dsor - 8) / 2 + 6) << 2; 537 else 538 ratio_bits = (dsor - 2) << 2; 539 540 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; 541 __raw_writew(ratio_bits, clk->enable_reg); 542 543 return 0; 544 } 545 546 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) 547 { 548 u32 l; 549 int div; 550 unsigned long p_rate; 551 552 p_rate = clk->parent->rate; 553 /* Round towards slower frequency */ 554 div = (p_rate + rate - 1) / rate; 555 div--; 556 if (div < 0 || div > 7) 557 return -EINVAL; 558 559 l = omap_readl(MOD_CONF_CTRL_1); 560 l &= ~(7 << 17); 561 l |= div << 17; 562 omap_writel(l, MOD_CONF_CTRL_1); 563 564 clk->rate = p_rate / (div + 1); 565 566 return 0; 567 } 568 569 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) 570 { 571 return 96000000 / calc_ext_dsor(rate); 572 } 573 574 static void omap1_init_ext_clk(struct clk * clk) 575 { 576 unsigned dsor; 577 __u16 ratio_bits; 578 579 /* Determine current rate and ensure clock is based on 96MHz APLL */ 580 ratio_bits = __raw_readw(clk->enable_reg) & ~1; 581 __raw_writew(ratio_bits, clk->enable_reg); 582 583 ratio_bits = (ratio_bits & 0xfc) >> 2; 584 if (ratio_bits > 6) 585 dsor = (ratio_bits - 6) * 2 + 8; 586 else 587 dsor = ratio_bits + 2; 588 589 clk-> rate = 96000000 / dsor; 590 } 591 592 static int omap1_clk_enable(struct clk *clk) 593 { 594 int ret = 0; 595 596 if (clk->usecount++ == 0) { 597 if (clk->parent) { 598 ret = omap1_clk_enable(clk->parent); 599 if (ret) 600 goto err; 601 602 if (clk->flags & CLOCK_NO_IDLE_PARENT) 603 omap1_clk_deny_idle(clk->parent); 604 } 605 606 ret = clk->ops->enable(clk); 607 if (ret) { 608 if (clk->parent) 609 omap1_clk_disable(clk->parent); 610 goto err; 611 } 612 } 613 return ret; 614 615 err: 616 clk->usecount--; 617 return ret; 618 } 619 620 static void omap1_clk_disable(struct clk *clk) 621 { 622 if (clk->usecount > 0 && !(--clk->usecount)) { 623 clk->ops->disable(clk); 624 if (likely(clk->parent)) { 625 omap1_clk_disable(clk->parent); 626 if (clk->flags & CLOCK_NO_IDLE_PARENT) 627 omap1_clk_allow_idle(clk->parent); 628 } 629 } 630 } 631 632 static int omap1_clk_enable_generic(struct clk *clk) 633 { 634 __u16 regval16; 635 __u32 regval32; 636 637 if (unlikely(clk->enable_reg == NULL)) { 638 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 639 clk->name); 640 return -EINVAL; 641 } 642 643 if (clk->flags & ENABLE_REG_32BIT) { 644 regval32 = __raw_readl(clk->enable_reg); 645 regval32 |= (1 << clk->enable_bit); 646 __raw_writel(regval32, clk->enable_reg); 647 } else { 648 regval16 = __raw_readw(clk->enable_reg); 649 regval16 |= (1 << clk->enable_bit); 650 __raw_writew(regval16, clk->enable_reg); 651 } 652 653 return 0; 654 } 655 656 static void omap1_clk_disable_generic(struct clk *clk) 657 { 658 __u16 regval16; 659 __u32 regval32; 660 661 if (clk->enable_reg == NULL) 662 return; 663 664 if (clk->flags & ENABLE_REG_32BIT) { 665 regval32 = __raw_readl(clk->enable_reg); 666 regval32 &= ~(1 << clk->enable_bit); 667 __raw_writel(regval32, clk->enable_reg); 668 } else { 669 regval16 = __raw_readw(clk->enable_reg); 670 regval16 &= ~(1 << clk->enable_bit); 671 __raw_writew(regval16, clk->enable_reg); 672 } 673 } 674 675 static const struct clkops clkops_generic = { 676 .enable = &omap1_clk_enable_generic, 677 .disable = &omap1_clk_disable_generic, 678 }; 679 680 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 681 { 682 if (clk->flags & RATE_FIXED) 683 return clk->rate; 684 685 if (clk->round_rate != NULL) 686 return clk->round_rate(clk, rate); 687 688 return clk->rate; 689 } 690 691 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) 692 { 693 int ret = -EINVAL; 694 695 if (clk->set_rate) 696 ret = clk->set_rate(clk, rate); 697 return ret; 698 } 699 700 /*------------------------------------------------------------------------- 701 * Omap1 clock reset and init functions 702 *-------------------------------------------------------------------------*/ 703 704 #ifdef CONFIG_OMAP_RESET_CLOCKS 705 706 static void __init omap1_clk_disable_unused(struct clk *clk) 707 { 708 __u32 regval32; 709 710 /* Clocks in the DSP domain need api_ck. Just assume bootloader 711 * has not enabled any DSP clocks */ 712 if (clk->enable_reg == DSP_IDLECT2) { 713 printk(KERN_INFO "Skipping reset check for DSP domain " 714 "clock \"%s\"\n", clk->name); 715 return; 716 } 717 718 /* Is the clock already disabled? */ 719 if (clk->flags & ENABLE_REG_32BIT) 720 regval32 = __raw_readl(clk->enable_reg); 721 else 722 regval32 = __raw_readw(clk->enable_reg); 723 724 if ((regval32 & (1 << clk->enable_bit)) == 0) 725 return; 726 727 /* FIXME: This clock seems to be necessary but no-one 728 * has asked for its activation. */ 729 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ 730 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ 731 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ 732 ) { 733 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", 734 clk->name); 735 return; 736 } 737 738 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); 739 clk->ops->disable(clk); 740 printk(" done\n"); 741 } 742 743 #else 744 #define omap1_clk_disable_unused NULL 745 #endif 746 747 static struct clk_functions omap1_clk_functions = { 748 .clk_enable = omap1_clk_enable, 749 .clk_disable = omap1_clk_disable, 750 .clk_round_rate = omap1_clk_round_rate, 751 .clk_set_rate = omap1_clk_set_rate, 752 .clk_disable_unused = omap1_clk_disable_unused, 753 }; 754 755 int __init omap1_clk_init(void) 756 { 757 struct omap_clk *c; 758 const struct omap_clock_config *info; 759 int crystal_type = 0; /* Default 12 MHz */ 760 u32 reg, cpu_mask; 761 762 #ifdef CONFIG_DEBUG_LL 763 /* Resets some clocks that may be left on from bootloader, 764 * but leaves serial clocks on. 765 */ 766 omap_writel(0x3 << 29, MOD_CONF_CTRL_0); 767 #endif 768 769 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 770 reg = omap_readw(SOFT_REQ_REG) & (1 << 4); 771 omap_writew(reg, SOFT_REQ_REG); 772 if (!cpu_is_omap15xx()) 773 omap_writew(0, SOFT_REQ_REG2); 774 775 clk_init(&omap1_clk_functions); 776 777 /* By default all idlect1 clocks are allowed to idle */ 778 arm_idlect1_mask = ~0; 779 780 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 781 clk_preinit(c->lk.clk); 782 783 cpu_mask = 0; 784 if (cpu_is_omap16xx()) 785 cpu_mask |= CK_16XX; 786 if (cpu_is_omap1510()) 787 cpu_mask |= CK_1510; 788 if (cpu_is_omap7xx()) 789 cpu_mask |= CK_7XX; 790 if (cpu_is_omap310()) 791 cpu_mask |= CK_310; 792 793 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) 794 if (c->cpu & cpu_mask) { 795 clkdev_add(&c->lk); 796 clk_register(c->lk.clk); 797 } 798 799 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); 800 if (info != NULL) { 801 if (!cpu_is_omap15xx()) 802 crystal_type = info->system_clock_type; 803 } 804 805 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 806 ck_ref.rate = 13000000; 807 #elif defined(CONFIG_ARCH_OMAP16XX) 808 if (crystal_type == 2) 809 ck_ref.rate = 19200000; 810 #endif 811 812 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", 813 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), 814 omap_readw(ARM_CKCTL)); 815 816 /* We want to be in syncronous scalable mode */ 817 omap_writew(0x1000, ARM_SYSST); 818 819 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER 820 /* Use values set by bootloader. Determine PLL rate and recalculate 821 * dependent clocks as if kernel had changed PLL or divisors. 822 */ 823 { 824 unsigned pll_ctl_val = omap_readw(DPLL_CTL); 825 826 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ 827 if (pll_ctl_val & 0x10) { 828 /* PLL enabled, apply multiplier and divisor */ 829 if (pll_ctl_val & 0xf80) 830 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; 831 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; 832 } else { 833 /* PLL disabled, apply bypass divisor */ 834 switch (pll_ctl_val & 0xc) { 835 case 0: 836 break; 837 case 0x4: 838 ck_dpll1.rate /= 2; 839 break; 840 default: 841 ck_dpll1.rate /= 4; 842 break; 843 } 844 } 845 } 846 #else 847 /* Find the highest supported frequency and enable it */ 848 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 849 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 850 /* Guess sane values (60MHz) */ 851 omap_writew(0x2290, DPLL_CTL); 852 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); 853 ck_dpll1.rate = 60000000; 854 } 855 #endif 856 propagate_rate(&ck_dpll1); 857 /* Cache rates for clocks connected to ck_ref (not dpll1) */ 858 propagate_rate(&ck_ref); 859 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " 860 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 861 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, 862 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 863 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 864 865 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) 866 /* Select slicer output as OMAP input clock */ 867 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); 868 #endif 869 870 /* Amstrad Delta wants BCLK high when inactive */ 871 if (machine_is_ams_delta()) 872 omap_writel(omap_readl(ULPD_CLOCK_CTRL) | 873 (1 << SDW_MCLK_INV_BIT), 874 ULPD_CLOCK_CTRL); 875 876 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 877 /* (on 730, bit 13 must not be cleared) */ 878 if (cpu_is_omap7xx()) 879 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 880 else 881 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 882 883 /* Put DSP/MPUI into reset until needed */ 884 omap_writew(0, ARM_RSTCT1); 885 omap_writew(1, ARM_RSTCT2); 886 omap_writew(0x400, ARM_IDLECT1); 887 888 /* 889 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) 890 * of the ARM_IDLECT2 register must be set to zero. The power-on 891 * default value of this bit is one. 892 */ 893 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ 894 895 /* 896 * Only enable those clocks we will need, let the drivers 897 * enable other clocks as necessary 898 */ 899 clk_enable(&armper_ck.clk); 900 clk_enable(&armxor_ck.clk); 901 clk_enable(&armtim_ck.clk); /* This should be done by timer code */ 902 903 if (cpu_is_omap15xx()) 904 clk_enable(&arm_gpio_ck); 905 906 return 0; 907 } 908