1*0fdebc5eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c3f08d0dSAndrew Lunn /* 3c3f08d0dSAndrew Lunn * arch/arm/mach-mvebu/kirkwood.h 4c3f08d0dSAndrew Lunn * 5c3f08d0dSAndrew Lunn * Generic definitions for Marvell Kirkwood SoC flavors: 6c3f08d0dSAndrew Lunn * 88F6180, 88F6192 and 88F6281. 7c3f08d0dSAndrew Lunn */ 8c3f08d0dSAndrew Lunn 9c3f08d0dSAndrew Lunn #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 10c3f08d0dSAndrew Lunn #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) 11c3f08d0dSAndrew Lunn #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) 12c3f08d0dSAndrew Lunn 13c3f08d0dSAndrew Lunn #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) 14c3f08d0dSAndrew Lunn 15c3f08d0dSAndrew Lunn #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100) 16c3f08d0dSAndrew Lunn #define CPU_CONFIG_ERROR_PROP 0x00000004 17c3f08d0dSAndrew Lunn 18c3f08d0dSAndrew Lunn #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) 19c3f08d0dSAndrew Lunn #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118) 20