1 /* 2 * Device Tree support for Armada 370 and XP platforms. 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/of_address.h> 18 #include <linux/of_fdt.h> 19 #include <linux/of_platform.h> 20 #include <linux/io.h> 21 #include <linux/clocksource.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/memblock.h> 24 #include <linux/mbus.h> 25 #include <linux/signal.h> 26 #include <linux/slab.h> 27 #include <linux/irqchip.h> 28 #include <asm/hardware/cache-l2x0.h> 29 #include <asm/mach/arch.h> 30 #include <asm/mach/map.h> 31 #include <asm/mach/time.h> 32 #include <asm/smp_scu.h> 33 #include "armada-370-xp.h" 34 #include "common.h" 35 #include "coherency.h" 36 #include "mvebu-soc-id.h" 37 38 static void __iomem *scu_base; 39 40 /* 41 * Enables the SCU when available. Obviously, this is only useful on 42 * Cortex-A based SOCs, not on PJ4B based ones. 43 */ 44 static void __init mvebu_scu_enable(void) 45 { 46 struct device_node *np = 47 of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); 48 if (np) { 49 scu_base = of_iomap(np, 0); 50 scu_enable(scu_base); 51 of_node_put(np); 52 } 53 } 54 55 void __iomem *mvebu_get_scu_base(void) 56 { 57 return scu_base; 58 } 59 60 /* 61 * When returning from suspend, the platform goes through the 62 * bootloader, which executes its DDR3 training code. This code has 63 * the unfortunate idea of using the first 10 KB of each DRAM bank to 64 * exercise the RAM and calculate the optimal timings. Therefore, this 65 * area of RAM is overwritten, and shouldn't be used by the kernel if 66 * suspend/resume is supported. 67 */ 68 69 #ifdef CONFIG_SUSPEND 70 #define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K) 71 static int __init mvebu_scan_mem(unsigned long node, const char *uname, 72 int depth, void *data) 73 { 74 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 75 const __be32 *reg, *endp; 76 int l; 77 78 if (type == NULL || strcmp(type, "memory")) 79 return 0; 80 81 reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); 82 if (reg == NULL) 83 reg = of_get_flat_dt_prop(node, "reg", &l); 84 if (reg == NULL) 85 return 0; 86 87 endp = reg + (l / sizeof(__be32)); 88 while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { 89 u64 base, size; 90 91 base = dt_mem_next_cell(dt_root_addr_cells, ®); 92 size = dt_mem_next_cell(dt_root_size_cells, ®); 93 94 memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ); 95 } 96 97 return 0; 98 } 99 100 static void __init mvebu_memblock_reserve(void) 101 { 102 of_scan_flat_dt(mvebu_scan_mem, NULL); 103 } 104 #else 105 static void __init mvebu_memblock_reserve(void) {} 106 #endif 107 108 /* 109 * Early versions of Armada 375 SoC have a bug where the BootROM 110 * leaves an external data abort pending. The kernel is hit by this 111 * data abort as soon as it enters userspace, because it unmasks the 112 * data aborts at this moment. We register a custom abort handler 113 * below to ignore the first data abort to work around this 114 * problem. 115 */ 116 static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr, 117 struct pt_regs *regs) 118 { 119 static int ignore_first; 120 121 if (!ignore_first && fsr == 0x1406) { 122 ignore_first = 1; 123 return 0; 124 } 125 126 return 1; 127 } 128 129 static void __init mvebu_init_irq(void) 130 { 131 irqchip_init(); 132 mvebu_scu_enable(); 133 coherency_init(); 134 BUG_ON(mvebu_mbus_dt_init(coherency_available())); 135 } 136 137 static void __init external_abort_quirk(void) 138 { 139 u32 dev, rev; 140 141 if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV) 142 return; 143 144 hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0, 145 "imprecise external abort"); 146 } 147 148 static void __init i2c_quirk(void) 149 { 150 struct device_node *np; 151 u32 dev, rev; 152 153 /* 154 * Only revisons more recent than A0 support the offload 155 * mechanism. We can exit only if we are sure that we can 156 * get the SoC revision and it is more recent than A0. 157 */ 158 if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV) 159 return; 160 161 for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") { 162 struct property *new_compat; 163 164 new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL); 165 166 new_compat->name = kstrdup("compatible", GFP_KERNEL); 167 new_compat->length = sizeof("marvell,mv78230-a0-i2c"); 168 new_compat->value = kstrdup("marvell,mv78230-a0-i2c", 169 GFP_KERNEL); 170 171 of_update_property(np, new_compat); 172 } 173 return; 174 } 175 176 static void __init mvebu_dt_init(void) 177 { 178 if (of_machine_is_compatible("marvell,armadaxp")) 179 i2c_quirk(); 180 if (of_machine_is_compatible("marvell,a375-db")) 181 external_abort_quirk(); 182 183 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 184 } 185 186 static const char * const armada_370_xp_dt_compat[] __initconst = { 187 "marvell,armada-370-xp", 188 NULL, 189 }; 190 191 DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") 192 .l2c_aux_val = 0, 193 .l2c_aux_mask = ~0, 194 /* 195 * The following field (.smp) is still needed to ensure backward 196 * compatibility with old Device Trees that were not specifying the 197 * cpus enable-method property. 198 */ 199 .smp = smp_ops(armada_xp_smp_ops), 200 .init_machine = mvebu_dt_init, 201 .init_irq = mvebu_init_irq, 202 .restart = mvebu_restart, 203 .reserve = mvebu_memblock_reserve, 204 .dt_compat = armada_370_xp_dt_compat, 205 MACHINE_END 206 207 static const char * const armada_375_dt_compat[] __initconst = { 208 "marvell,armada375", 209 NULL, 210 }; 211 212 DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") 213 .l2c_aux_val = 0, 214 .l2c_aux_mask = ~0, 215 .init_irq = mvebu_init_irq, 216 .init_machine = mvebu_dt_init, 217 .restart = mvebu_restart, 218 .dt_compat = armada_375_dt_compat, 219 MACHINE_END 220 221 static const char * const armada_38x_dt_compat[] __initconst = { 222 "marvell,armada380", 223 "marvell,armada385", 224 NULL, 225 }; 226 227 DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)") 228 .l2c_aux_val = 0, 229 .l2c_aux_mask = ~0, 230 .init_irq = mvebu_init_irq, 231 .restart = mvebu_restart, 232 .dt_compat = armada_38x_dt_compat, 233 MACHINE_END 234 235 static const char * const armada_39x_dt_compat[] __initconst = { 236 "marvell,armada390", 237 "marvell,armada398", 238 NULL, 239 }; 240 241 DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)") 242 .l2c_aux_val = 0, 243 .l2c_aux_mask = ~0, 244 .init_irq = mvebu_init_irq, 245 .restart = mvebu_restart, 246 .dt_compat = armada_39x_dt_compat, 247 MACHINE_END 248