xref: /linux/arch/arm/mach-mv78xx0/mv78xx0.h (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Generic definitions for Marvell MV78xx0 SoC flavors:
4  *  MV781x0 and MV782x0.
5  */
6 
7 #ifndef __ASM_ARCH_MV78XX0_H
8 #define __ASM_ARCH_MV78XX0_H
9 
10 #include "irqs.h"
11 
12 /*
13  * Marvell MV78xx0 address maps.
14  *
15  * phys
16  * c0000000	PCIe Memory space
17  * f0800000	PCIe #0 I/O space
18  * f0900000	PCIe #1 I/O space
19  * f0a00000	PCIe #2 I/O space
20  * f0b00000	PCIe #3 I/O space
21  * f0c00000	PCIe #4 I/O space
22  * f0d00000	PCIe #5 I/O space
23  * f0e00000	PCIe #6 I/O space
24  * f0f00000	PCIe #7 I/O space
25  * f1000000	on-chip peripheral registers
26  *
27  * virt		phys		size
28  * fe400000	f102x000	16K	core-specific peripheral registers
29  * fee00000	f0800000	64K	PCIe #0 I/O space
30  * fee10000	f0900000	64K	PCIe #1 I/O space
31  * fee20000	f0a00000	64K	PCIe #2 I/O space
32  * fee30000	f0b00000	64K	PCIe #3 I/O space
33  * fee40000	f0c00000	64K	PCIe #4 I/O space
34  * fee50000	f0d00000	64K	PCIe #5 I/O space
35  * fee60000	f0e00000	64K	PCIe #6 I/O space
36  * fee70000	f0f00000	64K	PCIe #7 I/O space
37  * fec00000	f1000000	1M	on-chip peripheral registers
38  */
39 #define MV78XX0_CORE0_REGS_PHYS_BASE	0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE	0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE	IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE	0xfe400000
43 #define MV78XX0_CORE_REGS_SIZE		SZ_16K
44 
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i)	(0xf0800000 + ((i) << 20))
46 #define MV78XX0_PCIE_IO_SIZE		SZ_1M
47 
48 #define MV78XX0_REGS_PHYS_BASE		0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE		IOMEM(0xfec00000)
50 #define MV78XX0_REGS_SIZE		SZ_1M
51 
52 #define MV78XX0_PCIE_MEM_PHYS_BASE	0xc0000000
53 #define MV78XX0_PCIE_MEM_SIZE		0x30000000
54 
55 /*
56  * Core-specific peripheral registers.
57  */
58 #define BRIDGE_VIRT_BASE	(MV78XX0_CORE_REGS_VIRT_BASE)
59 #define BRIDGE_PHYS_BASE	(MV78XX0_CORE_REGS_PHYS_BASE)
60 #define  BRIDGE_WINS_CPU0_BASE  (MV78XX0_CORE0_REGS_PHYS_BASE)
61 #define  BRIDGE_WINS_CPU1_BASE  (MV78XX0_CORE1_REGS_PHYS_BASE)
62 #define  BRIDGE_WINS_SZ         (0xA000)
63 
64 /*
65  * Register Map
66  */
67 #define DDR_VIRT_BASE		(MV78XX0_REGS_VIRT_BASE + 0x00000)
68 #define DDR_PHYS_BASE           (MV78XX0_REGS_PHYS_BASE + 0x00000)
69 #define  DDR_WINDOW_CPU0_BASE	(DDR_PHYS_BASE + 0x1500)
70 #define  DDR_WINDOW_CPU1_BASE	(DDR_PHYS_BASE + 0x1570)
71 #define  DDR_WINDOW_CPU_SZ      (0x20)
72 
73 #define DEV_BUS_PHYS_BASE	(MV78XX0_REGS_PHYS_BASE + 0x10000)
74 #define DEV_BUS_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x10000)
75 #define  SAMPLE_AT_RESET_LOW	(DEV_BUS_VIRT_BASE + 0x0030)
76 #define  SAMPLE_AT_RESET_HIGH	(DEV_BUS_VIRT_BASE + 0x0034)
77 #define  GPIO_VIRT_BASE		(DEV_BUS_VIRT_BASE + 0x0100)
78 #define  I2C_0_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x1000)
79 #define  I2C_1_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x1100)
80 #define  UART0_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2000)
81 #define  UART0_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2000)
82 #define  UART1_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2100)
83 #define  UART1_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2100)
84 #define  UART2_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2200)
85 #define  UART2_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2200)
86 #define  UART3_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2300)
87 #define  UART3_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2300)
88 
89 #define GE10_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x30000)
90 #define GE11_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x34000)
91 
92 #define PCIE00_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x40000)
93 #define PCIE01_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x44000)
94 #define PCIE02_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x48000)
95 #define PCIE03_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x4c000)
96 
97 #define USB0_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x50000)
98 #define USB1_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x51000)
99 #define USB2_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x52000)
100 
101 #define GE00_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x70000)
102 #define GE01_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x74000)
103 
104 #define PCIE10_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x80000)
105 #define PCIE11_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x84000)
106 #define PCIE12_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x88000)
107 #define PCIE13_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x8c000)
108 
109 #define SATA_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0xa0000)
110 
111 /*
112  * Supported devices and revisions.
113  */
114 #define MV78X00_Z0_DEV_ID	0x6381
115 #define MV78X00_REV_Z0		1
116 
117 #define MV78100_DEV_ID		0x7810
118 #define MV78100_REV_A0		1
119 #define MV78100_REV_A1		2
120 
121 #define MV78200_DEV_ID		0x7820
122 #define MV78200_REV_A0		1
123 
124 #endif
125