1 /* 2 * arch/arm/mach-mv78xx0/common.c 3 * 4 * Core functions for Marvell MV78xx0 SoCs 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/platform_device.h> 14 #include <linux/serial_8250.h> 15 #include <linux/ata_platform.h> 16 #include <linux/ethtool.h> 17 #include <asm/mach/map.h> 18 #include <asm/mach/time.h> 19 #include <mach/mv78xx0.h> 20 #include <mach/bridge-regs.h> 21 #include <plat/cache-feroceon-l2.h> 22 #include <plat/orion_nand.h> 23 #include <plat/time.h> 24 #include <plat/common.h> 25 #include <plat/addr-map.h> 26 #include "common.h" 27 28 static int get_tclk(void); 29 30 /***************************************************************************** 31 * Common bits 32 ****************************************************************************/ 33 int mv78xx0_core_index(void) 34 { 35 u32 extra; 36 37 /* 38 * Read Extra Features register. 39 */ 40 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); 41 42 return !!(extra & 0x00004000); 43 } 44 45 static int get_hclk(void) 46 { 47 int hclk; 48 49 /* 50 * HCLK tick rate is configured by DEV_D[7:5] pins. 51 */ 52 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { 53 case 0: 54 hclk = 166666667; 55 break; 56 case 1: 57 hclk = 200000000; 58 break; 59 case 2: 60 hclk = 266666667; 61 break; 62 case 3: 63 hclk = 333333333; 64 break; 65 case 4: 66 hclk = 400000000; 67 break; 68 default: 69 panic("unknown HCLK PLL setting: %.8x\n", 70 readl(SAMPLE_AT_RESET_LOW)); 71 } 72 73 return hclk; 74 } 75 76 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) 77 { 78 u32 cfg; 79 80 /* 81 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 82 * PCLK/L2CLK by bits [19:14]. 83 */ 84 if (core_index == 0) { 85 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; 86 } else { 87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; 88 } 89 90 /* 91 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK 92 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). 93 */ 94 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; 95 96 /* 97 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK 98 * ratio (1, 2, 3). 99 */ 100 *l2clk = *pclk / (((cfg >> 4) & 3) + 1); 101 } 102 103 static int get_tclk(void) 104 { 105 int tclk; 106 107 /* 108 * TCLK tick rate is configured by DEV_A[2:0] strap pins. 109 */ 110 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { 111 case 1: 112 tclk = 166666667; 113 break; 114 case 3: 115 tclk = 200000000; 116 break; 117 default: 118 panic("unknown TCLK PLL setting: %.8x\n", 119 readl(SAMPLE_AT_RESET_HIGH)); 120 } 121 122 return tclk; 123 } 124 125 126 /***************************************************************************** 127 * I/O Address Mapping 128 ****************************************************************************/ 129 static struct map_desc mv78xx0_io_desc[] __initdata = { 130 { 131 .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 132 .pfn = 0, 133 .length = MV78XX0_CORE_REGS_SIZE, 134 .type = MT_DEVICE, 135 }, { 136 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), 137 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), 138 .length = MV78XX0_PCIE_IO_SIZE * 8, 139 .type = MT_DEVICE, 140 }, { 141 .virtual = MV78XX0_REGS_VIRT_BASE, 142 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 143 .length = MV78XX0_REGS_SIZE, 144 .type = MT_DEVICE, 145 }, 146 }; 147 148 void __init mv78xx0_map_io(void) 149 { 150 unsigned long phys; 151 152 /* 153 * Map the right set of per-core registers depending on 154 * which core we are running on. 155 */ 156 if (mv78xx0_core_index() == 0) { 157 phys = MV78XX0_CORE0_REGS_PHYS_BASE; 158 } else { 159 phys = MV78XX0_CORE1_REGS_PHYS_BASE; 160 } 161 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); 162 163 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); 164 } 165 166 167 /***************************************************************************** 168 * EHCI 169 ****************************************************************************/ 170 void __init mv78xx0_ehci0_init(void) 171 { 172 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 173 } 174 175 176 /***************************************************************************** 177 * EHCI1 178 ****************************************************************************/ 179 void __init mv78xx0_ehci1_init(void) 180 { 181 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); 182 } 183 184 185 /***************************************************************************** 186 * EHCI2 187 ****************************************************************************/ 188 void __init mv78xx0_ehci2_init(void) 189 { 190 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); 191 } 192 193 194 /***************************************************************************** 195 * GE00 196 ****************************************************************************/ 197 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 198 { 199 orion_ge00_init(eth_data, 200 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 201 IRQ_MV78XX0_GE_ERR, get_tclk()); 202 } 203 204 205 /***************************************************************************** 206 * GE01 207 ****************************************************************************/ 208 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 209 { 210 orion_ge01_init(eth_data, 211 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 212 NO_IRQ, get_tclk()); 213 } 214 215 216 /***************************************************************************** 217 * GE10 218 ****************************************************************************/ 219 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 220 { 221 u32 dev, rev; 222 223 /* 224 * On the Z0, ge10 and ge11 are internally connected back 225 * to back, and not brought out. 226 */ 227 mv78xx0_pcie_id(&dev, &rev); 228 if (dev == MV78X00_Z0_DEV_ID) { 229 eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 230 eth_data->speed = SPEED_1000; 231 eth_data->duplex = DUPLEX_FULL; 232 } 233 234 orion_ge10_init(eth_data, 235 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 236 NO_IRQ, get_tclk()); 237 } 238 239 240 /***************************************************************************** 241 * GE11 242 ****************************************************************************/ 243 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 244 { 245 u32 dev, rev; 246 247 /* 248 * On the Z0, ge10 and ge11 are internally connected back 249 * to back, and not brought out. 250 */ 251 mv78xx0_pcie_id(&dev, &rev); 252 if (dev == MV78X00_Z0_DEV_ID) { 253 eth_data->phy_addr = MV643XX_ETH_PHY_NONE; 254 eth_data->speed = SPEED_1000; 255 eth_data->duplex = DUPLEX_FULL; 256 } 257 258 orion_ge11_init(eth_data, 259 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 260 NO_IRQ, get_tclk()); 261 } 262 263 /***************************************************************************** 264 * I2C 265 ****************************************************************************/ 266 void __init mv78xx0_i2c_init(void) 267 { 268 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); 269 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); 270 } 271 272 /***************************************************************************** 273 * SATA 274 ****************************************************************************/ 275 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 276 { 277 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); 278 } 279 280 281 /***************************************************************************** 282 * UART0 283 ****************************************************************************/ 284 void __init mv78xx0_uart0_init(void) 285 { 286 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 287 IRQ_MV78XX0_UART_0, get_tclk()); 288 } 289 290 291 /***************************************************************************** 292 * UART1 293 ****************************************************************************/ 294 void __init mv78xx0_uart1_init(void) 295 { 296 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 297 IRQ_MV78XX0_UART_1, get_tclk()); 298 } 299 300 301 /***************************************************************************** 302 * UART2 303 ****************************************************************************/ 304 void __init mv78xx0_uart2_init(void) 305 { 306 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, 307 IRQ_MV78XX0_UART_2, get_tclk()); 308 } 309 310 /***************************************************************************** 311 * UART3 312 ****************************************************************************/ 313 void __init mv78xx0_uart3_init(void) 314 { 315 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, 316 IRQ_MV78XX0_UART_3, get_tclk()); 317 } 318 319 /***************************************************************************** 320 * Time handling 321 ****************************************************************************/ 322 void __init mv78xx0_init_early(void) 323 { 324 orion_time_set_base(TIMER_VIRT_BASE); 325 } 326 327 static void mv78xx0_timer_init(void) 328 { 329 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 330 IRQ_MV78XX0_TIMER_1, get_tclk()); 331 } 332 333 struct sys_timer mv78xx0_timer = { 334 .init = mv78xx0_timer_init, 335 }; 336 337 338 /***************************************************************************** 339 * General 340 ****************************************************************************/ 341 static char * __init mv78xx0_id(void) 342 { 343 u32 dev, rev; 344 345 mv78xx0_pcie_id(&dev, &rev); 346 347 if (dev == MV78X00_Z0_DEV_ID) { 348 if (rev == MV78X00_REV_Z0) 349 return "MV78X00-Z0"; 350 else 351 return "MV78X00-Rev-Unsupported"; 352 } else if (dev == MV78100_DEV_ID) { 353 if (rev == MV78100_REV_A0) 354 return "MV78100-A0"; 355 else if (rev == MV78100_REV_A1) 356 return "MV78100-A1"; 357 else 358 return "MV78100-Rev-Unsupported"; 359 } else if (dev == MV78200_DEV_ID) { 360 if (rev == MV78100_REV_A0) 361 return "MV78200-A0"; 362 else 363 return "MV78200-Rev-Unsupported"; 364 } else { 365 return "Device-Unknown"; 366 } 367 } 368 369 static int __init is_l2_writethrough(void) 370 { 371 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); 372 } 373 374 void __init mv78xx0_init(void) 375 { 376 int core_index; 377 int hclk; 378 int pclk; 379 int l2clk; 380 int tclk; 381 382 core_index = mv78xx0_core_index(); 383 hclk = get_hclk(); 384 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); 385 tclk = get_tclk(); 386 387 printk(KERN_INFO "%s ", mv78xx0_id()); 388 printk("core #%d, ", core_index); 389 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); 390 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); 391 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 392 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); 393 394 mv78xx0_setup_cpu_mbus(); 395 396 #ifdef CONFIG_CACHE_FEROCEON_L2 397 feroceon_l2_init(is_l2_writethrough()); 398 #endif 399 } 400 401 void mv78xx0_restart(char mode, const char *cmd) 402 { 403 /* 404 * Enable soft reset to assert RSTOUTn. 405 */ 406 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 407 408 /* 409 * Assert soft reset. 410 */ 411 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 412 413 while (1) 414 ; 415 } 416