1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mach-mmp/time.c
4 *
5 * Support for clocksource and clockevents
6 *
7 * Copyright (C) 2008 Marvell International Ltd.
8 * All rights reserved.
9 *
10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
11 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
12 *
13 * The timers module actually includes three timers, each timer with up to
14 * three match comparators. Timer #0 is used here in free-running mode as
15 * the clock source, and match comparator #1 used as clock event device.
16 */
17
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/clockchips.h>
22 #include <linux/clk.h>
23
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/sched_clock.h>
30 #include <asm/mach/time.h>
31
32 #include "regs-timers.h"
33 #include <linux/soc/mmp/cputype.h>
34
35 #define MAX_DELTA (0xfffffffe)
36 #define MIN_DELTA (16)
37
38 static void __iomem *mmp_timer_base;
39
40 /*
41 * Read the timer through the CVWR register. Delay is required after requesting
42 * a read. The CR register cannot be directly read due to metastability issues
43 * documented in the PXA168 software manual.
44 */
timer_read(void)45 static inline uint32_t timer_read(void)
46 {
47 uint32_t val;
48 int delay = 3;
49
50 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
51
52 while (delay--)
53 val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
54
55 return val;
56 }
57
mmp_read_sched_clock(void)58 static u64 notrace mmp_read_sched_clock(void)
59 {
60 return timer_read();
61 }
62
timer_interrupt(int irq,void * dev_id)63 static irqreturn_t timer_interrupt(int irq, void *dev_id)
64 {
65 struct clock_event_device *c = dev_id;
66
67 /*
68 * Clear pending interrupt status.
69 */
70 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
71
72 /*
73 * Disable timer 0.
74 */
75 __raw_writel(0x02, mmp_timer_base + TMR_CER);
76
77 c->event_handler(c);
78
79 return IRQ_HANDLED;
80 }
81
timer_set_next_event(unsigned long delta,struct clock_event_device * dev)82 static int timer_set_next_event(unsigned long delta,
83 struct clock_event_device *dev)
84 {
85 unsigned long flags;
86
87 local_irq_save(flags);
88
89 /*
90 * Disable timer 0.
91 */
92 __raw_writel(0x02, mmp_timer_base + TMR_CER);
93
94 /*
95 * Clear and enable timer match 0 interrupt.
96 */
97 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
98 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
99
100 /*
101 * Setup new clockevent timer value.
102 */
103 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
104
105 /*
106 * Enable timer 0.
107 */
108 __raw_writel(0x03, mmp_timer_base + TMR_CER);
109
110 local_irq_restore(flags);
111
112 return 0;
113 }
114
timer_set_shutdown(struct clock_event_device * evt)115 static int timer_set_shutdown(struct clock_event_device *evt)
116 {
117 unsigned long flags;
118
119 local_irq_save(flags);
120 /* disable the matching interrupt */
121 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
122 local_irq_restore(flags);
123
124 return 0;
125 }
126
127 static struct clock_event_device ckevt = {
128 .name = "clockevent",
129 .features = CLOCK_EVT_FEAT_ONESHOT,
130 .rating = 200,
131 .set_next_event = timer_set_next_event,
132 .set_state_shutdown = timer_set_shutdown,
133 .set_state_oneshot = timer_set_shutdown,
134 };
135
clksrc_read(struct clocksource * cs)136 static u64 clksrc_read(struct clocksource *cs)
137 {
138 return timer_read();
139 }
140
141 static struct clocksource cksrc = {
142 .name = "clocksource",
143 .rating = 200,
144 .read = clksrc_read,
145 .mask = CLOCKSOURCE_MASK(32),
146 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
147 };
148
timer_config(void)149 static void __init timer_config(void)
150 {
151 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
152
153 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
154
155 ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
156 (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
157 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
158 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
159
160 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
161 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
162
163 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
164 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
165 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
166
167 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
168 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
169 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
170
171 /* enable timer 1 counter */
172 __raw_writel(0x2, mmp_timer_base + TMR_CER);
173 }
174
mmp_timer_init(int irq,unsigned long rate)175 static void __init mmp_timer_init(int irq, unsigned long rate)
176 {
177 timer_config();
178
179 sched_clock_register(mmp_read_sched_clock, 32, rate);
180
181 ckevt.cpumask = cpumask_of(0);
182
183 if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
184 "timer", &ckevt))
185 pr_err("Failed to request irq %d (timer)\n", irq);
186
187 clocksource_register_hz(&cksrc, rate);
188 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
189 }
190
mmp_dt_init_timer(struct device_node * np)191 static int __init mmp_dt_init_timer(struct device_node *np)
192 {
193 struct clk *clk;
194 int irq, ret;
195 unsigned long rate;
196
197 clk = of_clk_get(np, 0);
198 if (!IS_ERR(clk)) {
199 ret = clk_prepare_enable(clk);
200 if (ret)
201 return ret;
202 rate = clk_get_rate(clk);
203 } else if (cpu_is_pj4()) {
204 rate = 6500000;
205 } else {
206 rate = 3250000;
207 }
208
209 irq = irq_of_parse_and_map(np, 0);
210 if (!irq)
211 return -EINVAL;
212
213 mmp_timer_base = of_iomap(np, 0);
214 if (!mmp_timer_base)
215 return -ENOMEM;
216
217 mmp_timer_init(irq, rate);
218 return 0;
219 }
220
221 TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
222