1 /* 2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/device.h> 16 #include <linux/errno.h> 17 #include <linux/io.h> 18 #include <linux/irqdomain.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 22 #include <asm/mach/irq.h> 23 #include <asm/exception.h> 24 25 #include "common.h" 26 #include "hardware.h" 27 #include "irq-common.h" 28 29 /* 30 ***************************************** 31 * TZIC Registers * 32 ***************************************** 33 */ 34 35 #define TZIC_INTCNTL 0x0000 /* Control register */ 36 #define TZIC_INTTYPE 0x0004 /* Controller Type register */ 37 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ 38 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ 39 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ 40 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ 41 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ 42 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ 43 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ 44 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ 45 #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ 46 #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ 47 #define TZIC_PND0 0x0D00 /* Pending Register 0 */ 48 #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */ 49 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ 50 #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ 51 #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ 52 53 static void __iomem *tzic_base; 54 static struct irq_domain *domain; 55 56 #define TZIC_NUM_IRQS 128 57 58 #ifdef CONFIG_FIQ 59 static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) 60 { 61 unsigned int index, mask, value; 62 63 index = irq >> 5; 64 if (unlikely(index >= 4)) 65 return -EINVAL; 66 mask = 1U << (irq & 0x1F); 67 68 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; 69 if (type) 70 value &= ~mask; 71 __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); 72 73 return 0; 74 } 75 #else 76 #define tzic_set_irq_fiq NULL 77 #endif 78 79 #ifdef CONFIG_PM 80 static void tzic_irq_suspend(struct irq_data *d) 81 { 82 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 83 int idx = d->hwirq >> 5; 84 85 __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); 86 } 87 88 static void tzic_irq_resume(struct irq_data *d) 89 { 90 int idx = d->hwirq >> 5; 91 92 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), 93 tzic_base + TZIC_WAKEUP0(idx)); 94 } 95 96 #else 97 #define tzic_irq_suspend NULL 98 #define tzic_irq_resume NULL 99 #endif 100 101 static struct mxc_extra_irq tzic_extra_irq = { 102 #ifdef CONFIG_FIQ 103 .set_irq_fiq = tzic_set_irq_fiq, 104 #endif 105 }; 106 107 static __init void tzic_init_gc(int idx, unsigned int irq_start) 108 { 109 struct irq_chip_generic *gc; 110 struct irq_chip_type *ct; 111 112 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, 113 handle_level_irq); 114 gc->private = &tzic_extra_irq; 115 gc->wake_enabled = IRQ_MSK(32); 116 117 ct = gc->chip_types; 118 ct->chip.irq_mask = irq_gc_mask_disable_reg; 119 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 120 ct->chip.irq_set_wake = irq_gc_set_wake; 121 ct->chip.irq_suspend = tzic_irq_suspend; 122 ct->chip.irq_resume = tzic_irq_resume; 123 ct->regs.disable = TZIC_ENCLEAR0(idx); 124 ct->regs.enable = TZIC_ENSET0(idx); 125 126 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 127 } 128 129 static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) 130 { 131 u32 stat; 132 int i, irqofs, handled; 133 134 do { 135 handled = 0; 136 137 for (i = 0; i < 4; i++) { 138 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & 139 __raw_readl(tzic_base + TZIC_INTSEC0(i)); 140 141 while (stat) { 142 handled = 1; 143 irqofs = fls(stat) - 1; 144 handle_domain_irq(domain, irqofs + i * 32, regs); 145 stat &= ~(1 << irqofs); 146 } 147 } 148 } while (handled); 149 } 150 151 /* 152 * This function initializes the TZIC hardware and disables all the 153 * interrupts. It registers the interrupt enable and disable functions 154 * to the kernel for each interrupt source. 155 */ 156 void __init tzic_init_irq(void) 157 { 158 struct device_node *np; 159 int irq_base; 160 int i; 161 162 np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); 163 tzic_base = of_iomap(np, 0); 164 WARN_ON(!tzic_base); 165 166 /* put the TZIC into the reset value with 167 * all interrupts disabled 168 */ 169 i = __raw_readl(tzic_base + TZIC_INTCNTL); 170 171 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); 172 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); 173 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); 174 175 for (i = 0; i < 4; i++) 176 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); 177 178 /* disable all interrupts */ 179 for (i = 0; i < 4; i++) 180 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); 181 182 /* all IRQ no FIQ Warning :: No selection */ 183 184 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); 185 WARN_ON(irq_base < 0); 186 187 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, 188 &irq_domain_simple_ops, NULL); 189 WARN_ON(!domain); 190 191 for (i = 0; i < 4; i++, irq_base += 32) 192 tzic_init_gc(i, irq_base); 193 194 set_handle_irq(tzic_handle_irq); 195 196 #ifdef CONFIG_FIQ 197 /* Initialize FIQ */ 198 init_FIQ(FIQ_START); 199 #endif 200 201 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 202 } 203 204 /** 205 * tzic_enable_wake() - enable wakeup interrupt 206 * 207 * @return 0 if successful; non-zero otherwise 208 * 209 * This function provides an interrupt synchronization point that is required 210 * by tzic enabled platforms before entering imx specific low power modes (ie, 211 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode). 212 */ 213 int tzic_enable_wake(void) 214 { 215 unsigned int i; 216 217 __raw_writel(1, tzic_base + TZIC_DSMINT); 218 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) 219 return -EAGAIN; 220 221 for (i = 0; i < 4; i++) 222 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), 223 tzic_base + TZIC_WAKEUP0(i)); 224 225 return 0; 226 } 227