1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/smp.h> 18 19 #define SRC_SCR 0x000 20 #define SRC_GPR1 0x020 21 #define BP_SRC_SCR_WARM_RESET_ENABLE 0 22 #define BP_SRC_SCR_CORE1_RST 14 23 #define BP_SRC_SCR_CORE1_ENABLE 22 24 25 static void __iomem *src_base; 26 27 #ifndef CONFIG_SMP 28 #define cpu_logical_map(cpu) 0 29 #endif 30 31 void imx_enable_cpu(int cpu, bool enable) 32 { 33 u32 mask, val; 34 35 cpu = cpu_logical_map(cpu); 36 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); 37 val = readl_relaxed(src_base + SRC_SCR); 38 val = enable ? val | mask : val & ~mask; 39 writel_relaxed(val, src_base + SRC_SCR); 40 } 41 42 void imx_set_cpu_jump(int cpu, void *jump_addr) 43 { 44 cpu = cpu_logical_map(cpu); 45 writel_relaxed(virt_to_phys(jump_addr), 46 src_base + SRC_GPR1 + cpu * 8); 47 } 48 49 void imx_src_prepare_restart(void) 50 { 51 u32 val; 52 53 /* clear enable bits of secondary cores */ 54 val = readl_relaxed(src_base + SRC_SCR); 55 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); 56 writel_relaxed(val, src_base + SRC_SCR); 57 58 /* clear persistent entry register of primary core */ 59 writel_relaxed(0, src_base + SRC_GPR1); 60 } 61 62 void __init imx_src_init(void) 63 { 64 struct device_node *np; 65 u32 val; 66 67 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); 68 src_base = of_iomap(np, 0); 69 WARN_ON(!src_base); 70 71 /* 72 * force warm reset sources to generate cold reset 73 * for a more reliable restart 74 */ 75 val = readl_relaxed(src_base + SRC_SCR); 76 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); 77 writel_relaxed(val, src_base + SRC_SCR); 78 } 79