xref: /linux/arch/arm/mach-imx/mxc.h (revision 3459f0d78ffe27a1b341c22eb158b622eaaea3fc)
1 /*
2  * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17  * MA 02110-1301, USA.
18  */
19 
20 #ifndef __ASM_ARCH_MXC_H__
21 #define __ASM_ARCH_MXC_H__
22 
23 #include <linux/types.h>
24 
25 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
26 #error "Do not include directly."
27 #endif
28 
29 #define MXC_CPU_MX1		1
30 #define MXC_CPU_MX21		21
31 #define MXC_CPU_MX25		25
32 #define MXC_CPU_MX27		27
33 #define MXC_CPU_MX31		31
34 #define MXC_CPU_MX35		35
35 #define MXC_CPU_MX51		51
36 #define MXC_CPU_MX53		53
37 #define MXC_CPU_IMX6SL		0x60
38 #define MXC_CPU_IMX6DL		0x61
39 #define MXC_CPU_IMX6SX		0x62
40 #define MXC_CPU_IMX6Q		0x63
41 
42 #define IMX_CHIP_REVISION_1_0		0x10
43 #define IMX_CHIP_REVISION_1_1		0x11
44 #define IMX_CHIP_REVISION_1_2		0x12
45 #define IMX_CHIP_REVISION_1_3		0x13
46 #define IMX_CHIP_REVISION_1_4		0x14
47 #define IMX_CHIP_REVISION_1_5		0x15
48 #define IMX_CHIP_REVISION_2_0		0x20
49 #define IMX_CHIP_REVISION_2_1		0x21
50 #define IMX_CHIP_REVISION_2_2		0x22
51 #define IMX_CHIP_REVISION_2_3		0x23
52 #define IMX_CHIP_REVISION_3_0		0x30
53 #define IMX_CHIP_REVISION_3_1		0x31
54 #define IMX_CHIP_REVISION_3_2		0x32
55 #define IMX_CHIP_REVISION_3_3		0x33
56 #define IMX_CHIP_REVISION_UNKNOWN	0xff
57 
58 #define IMX_DDR_TYPE_LPDDR2		1
59 
60 #ifndef __ASSEMBLY__
61 extern unsigned int __mxc_cpu_type;
62 #endif
63 
64 #ifdef CONFIG_SOC_IMX1
65 # ifdef mxc_cpu_type
66 #  undef mxc_cpu_type
67 #  define mxc_cpu_type __mxc_cpu_type
68 # else
69 #  define mxc_cpu_type MXC_CPU_MX1
70 # endif
71 # define cpu_is_mx1()		(mxc_cpu_type == MXC_CPU_MX1)
72 #else
73 # define cpu_is_mx1()		(0)
74 #endif
75 
76 #ifdef CONFIG_SOC_IMX21
77 # ifdef mxc_cpu_type
78 #  undef mxc_cpu_type
79 #  define mxc_cpu_type __mxc_cpu_type
80 # else
81 #  define mxc_cpu_type MXC_CPU_MX21
82 # endif
83 # define cpu_is_mx21()		(mxc_cpu_type == MXC_CPU_MX21)
84 #else
85 # define cpu_is_mx21()		(0)
86 #endif
87 
88 #ifdef CONFIG_SOC_IMX25
89 # ifdef mxc_cpu_type
90 #  undef mxc_cpu_type
91 #  define mxc_cpu_type __mxc_cpu_type
92 # else
93 #  define mxc_cpu_type MXC_CPU_MX25
94 # endif
95 # define cpu_is_mx25()		(mxc_cpu_type == MXC_CPU_MX25)
96 #else
97 # define cpu_is_mx25()		(0)
98 #endif
99 
100 #ifdef CONFIG_SOC_IMX27
101 # ifdef mxc_cpu_type
102 #  undef mxc_cpu_type
103 #  define mxc_cpu_type __mxc_cpu_type
104 # else
105 #  define mxc_cpu_type MXC_CPU_MX27
106 # endif
107 # define cpu_is_mx27()		(mxc_cpu_type == MXC_CPU_MX27)
108 #else
109 # define cpu_is_mx27()		(0)
110 #endif
111 
112 #ifdef CONFIG_SOC_IMX31
113 # ifdef mxc_cpu_type
114 #  undef mxc_cpu_type
115 #  define mxc_cpu_type __mxc_cpu_type
116 # else
117 #  define mxc_cpu_type MXC_CPU_MX31
118 # endif
119 # define cpu_is_mx31()		(mxc_cpu_type == MXC_CPU_MX31)
120 #else
121 # define cpu_is_mx31()		(0)
122 #endif
123 
124 #ifdef CONFIG_SOC_IMX35
125 # ifdef mxc_cpu_type
126 #  undef mxc_cpu_type
127 #  define mxc_cpu_type __mxc_cpu_type
128 # else
129 #  define mxc_cpu_type MXC_CPU_MX35
130 # endif
131 # define cpu_is_mx35()		(mxc_cpu_type == MXC_CPU_MX35)
132 #else
133 # define cpu_is_mx35()		(0)
134 #endif
135 
136 #ifdef CONFIG_SOC_IMX51
137 # ifdef mxc_cpu_type
138 #  undef mxc_cpu_type
139 #  define mxc_cpu_type __mxc_cpu_type
140 # else
141 #  define mxc_cpu_type MXC_CPU_MX51
142 # endif
143 # define cpu_is_mx51()		(mxc_cpu_type == MXC_CPU_MX51)
144 #else
145 # define cpu_is_mx51()		(0)
146 #endif
147 
148 #ifdef CONFIG_SOC_IMX53
149 # ifdef mxc_cpu_type
150 #  undef mxc_cpu_type
151 #  define mxc_cpu_type __mxc_cpu_type
152 # else
153 #  define mxc_cpu_type MXC_CPU_MX53
154 # endif
155 # define cpu_is_mx53()		(mxc_cpu_type == MXC_CPU_MX53)
156 #else
157 # define cpu_is_mx53()		(0)
158 #endif
159 
160 #ifndef __ASSEMBLY__
161 #ifdef CONFIG_SOC_IMX6SL
162 static inline bool cpu_is_imx6sl(void)
163 {
164 	return __mxc_cpu_type == MXC_CPU_IMX6SL;
165 }
166 #else
167 static inline bool cpu_is_imx6sl(void)
168 {
169 	return false;
170 }
171 #endif
172 
173 static inline bool cpu_is_imx6dl(void)
174 {
175 	return __mxc_cpu_type == MXC_CPU_IMX6DL;
176 }
177 
178 static inline bool cpu_is_imx6sx(void)
179 {
180 	return __mxc_cpu_type == MXC_CPU_IMX6SX;
181 }
182 
183 static inline bool cpu_is_imx6q(void)
184 {
185 	return __mxc_cpu_type == MXC_CPU_IMX6Q;
186 }
187 
188 struct cpu_op {
189 	u32 cpu_rate;
190 };
191 
192 int tzic_enable_wake(void);
193 
194 extern struct cpu_op *(*get_cpu_op)(int *op);
195 #endif
196 
197 #define cpu_is_mx3()	(cpu_is_mx31() || cpu_is_mx35())
198 #define cpu_is_mx2()	(cpu_is_mx21() || cpu_is_mx27())
199 
200 #endif /*  __ASM_ARCH_MXC_H__ */
201