1 /* 2 * Copyright (C) 1999,2000 Arm Limited 3 * Copyright (C) 2000 Deep Blue Solutions Ltd 4 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 6 * - add MX31 specific definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/mm.h> 20 #include <linux/init.h> 21 #include <linux/err.h> 22 23 #include <asm/pgtable.h> 24 #include <asm/hardware/cache-l2x0.h> 25 #include <asm/mach/map.h> 26 27 #include <mach/common.h> 28 #include <mach/devices-common.h> 29 #include <mach/hardware.h> 30 #include <mach/iomux-v3.h> 31 #include <mach/irqs.h> 32 33 static void imx3_idle(void) 34 { 35 unsigned long reg = 0; 36 __asm__ __volatile__( 37 /* disable I and D cache */ 38 "mrc p15, 0, %0, c1, c0, 0\n" 39 "bic %0, %0, #0x00001000\n" 40 "bic %0, %0, #0x00000004\n" 41 "mcr p15, 0, %0, c1, c0, 0\n" 42 /* invalidate I cache */ 43 "mov %0, #0\n" 44 "mcr p15, 0, %0, c7, c5, 0\n" 45 /* clear and invalidate D cache */ 46 "mov %0, #0\n" 47 "mcr p15, 0, %0, c7, c14, 0\n" 48 /* WFI */ 49 "mov %0, #0\n" 50 "mcr p15, 0, %0, c7, c0, 4\n" 51 "nop\n" "nop\n" "nop\n" "nop\n" 52 "nop\n" "nop\n" "nop\n" 53 /* enable I and D cache */ 54 "mrc p15, 0, %0, c1, c0, 0\n" 55 "orr %0, %0, #0x00001000\n" 56 "orr %0, %0, #0x00000004\n" 57 "mcr p15, 0, %0, c1, c0, 0\n" 58 : "=r" (reg)); 59 } 60 61 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, 62 unsigned int mtype) 63 { 64 if (mtype == MT_DEVICE) { 65 /* 66 * Access all peripherals below 0x80000000 as nonshared device 67 * on mx3, but leave l2cc alone. Otherwise cache corruptions 68 * can occur. 69 */ 70 if (phys_addr < 0x80000000 && 71 !addr_in_module(phys_addr, MX3x_L2CC)) 72 mtype = MT_DEVICE_NONSHARED; 73 } 74 75 return __arm_ioremap(phys_addr, size, mtype); 76 } 77 78 void imx3_init_l2x0(void) 79 { 80 void __iomem *l2x0_base; 81 void __iomem *clkctl_base; 82 83 /* 84 * First of all, we must repair broken chip settings. There are some 85 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These 86 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. 87 * Workaraound is to setup the correct register setting prior enabling the 88 * L2 cache. This should not hurt already working CPUs, as they are using the 89 * same value. 90 */ 91 #define L2_MEM_VAL 0x10 92 93 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); 94 if (clkctl_base != NULL) { 95 writel(0x00000515, clkctl_base + L2_MEM_VAL); 96 iounmap(clkctl_base); 97 } else { 98 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); 99 } 100 101 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); 102 if (IS_ERR(l2x0_base)) { 103 printk(KERN_ERR "remapping L2 cache area failed with %ld\n", 104 PTR_ERR(l2x0_base)); 105 return; 106 } 107 108 l2x0_init(l2x0_base, 0x00030024, 0x00000000); 109 } 110 111 static struct map_desc mx31_io_desc[] __initdata = { 112 imx_map_entry(MX31, X_MEMC, MT_DEVICE), 113 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), 114 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), 115 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), 116 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), 117 }; 118 119 /* 120 * This function initializes the memory map. It is called during the 121 * system startup to create static physical to virtual memory mappings 122 * for the IO modules. 123 */ 124 void __init mx31_map_io(void) 125 { 126 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); 127 } 128 129 static struct map_desc mx35_io_desc[] __initdata = { 130 imx_map_entry(MX35, X_MEMC, MT_DEVICE), 131 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), 132 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), 133 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), 134 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), 135 }; 136 137 void __init mx35_map_io(void) 138 { 139 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); 140 } 141 142 void __init imx31_init_early(void) 143 { 144 mxc_set_cpu_type(MXC_CPU_MX31); 145 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 146 imx_idle = imx3_idle; 147 imx_ioremap = imx3_ioremap; 148 } 149 150 void __init imx35_init_early(void) 151 { 152 mxc_set_cpu_type(MXC_CPU_MX35); 153 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 154 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 155 imx_idle = imx3_idle; 156 imx_ioremap = imx3_ioremap; 157 } 158 159 void __init mx31_init_irq(void) 160 { 161 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 162 } 163 164 void __init mx35_init_irq(void) 165 { 166 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); 167 } 168 169 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { 170 .per_2_per_addr = 1677, 171 }; 172 173 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { 174 .ap_2_ap_addr = 423, 175 .ap_2_bp_addr = 829, 176 .bp_2_ap_addr = 1029, 177 }; 178 179 static struct sdma_platform_data imx31_sdma_pdata __initdata = { 180 .fw_name = "sdma-imx31-to2.bin", 181 .script_addrs = &imx31_to2_sdma_script, 182 }; 183 184 void __init imx31_soc_init(void) 185 { 186 int to_version = mx31_revision() >> 4; 187 188 imx3_init_l2x0(); 189 190 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); 191 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); 192 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); 193 194 if (to_version == 1) { 195 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", 196 strlen(imx31_sdma_pdata.fw_name)); 197 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; 198 } 199 200 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 201 } 202 203 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { 204 .ap_2_ap_addr = 642, 205 .uart_2_mcu_addr = 817, 206 .mcu_2_app_addr = 747, 207 .uartsh_2_mcu_addr = 1183, 208 .per_2_shp_addr = 1033, 209 .mcu_2_shp_addr = 961, 210 .ata_2_mcu_addr = 1333, 211 .mcu_2_ata_addr = 1252, 212 .app_2_mcu_addr = 683, 213 .shp_2_per_addr = 1111, 214 .shp_2_mcu_addr = 892, 215 }; 216 217 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { 218 .ap_2_ap_addr = 729, 219 .uart_2_mcu_addr = 904, 220 .per_2_app_addr = 1597, 221 .mcu_2_app_addr = 834, 222 .uartsh_2_mcu_addr = 1270, 223 .per_2_shp_addr = 1120, 224 .mcu_2_shp_addr = 1048, 225 .ata_2_mcu_addr = 1429, 226 .mcu_2_ata_addr = 1339, 227 .app_2_per_addr = 1531, 228 .app_2_mcu_addr = 770, 229 .shp_2_per_addr = 1198, 230 .shp_2_mcu_addr = 979, 231 }; 232 233 static struct sdma_platform_data imx35_sdma_pdata __initdata = { 234 .fw_name = "sdma-imx35-to2.bin", 235 .script_addrs = &imx35_to2_sdma_script, 236 }; 237 238 void __init imx35_soc_init(void) 239 { 240 int to_version = mx35_revision() >> 4; 241 242 imx3_init_l2x0(); 243 244 /* i.mx35 has the i.mx31 type gpio */ 245 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 246 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 247 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); 248 249 if (to_version == 1) { 250 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", 251 strlen(imx35_sdma_pdata.fw_name)); 252 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; 253 } 254 255 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 256 } 257