1 /* 2 * Copyright (C) 1999,2000 Arm Limited 3 * Copyright (C) 2000 Deep Blue Solutions Ltd 4 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 6 * - add MX31 specific definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/mm.h> 20 #include <linux/init.h> 21 #include <linux/err.h> 22 #include <linux/pinctrl/machine.h> 23 24 #include <asm/pgtable.h> 25 #include <asm/system_misc.h> 26 #include <asm/hardware/cache-l2x0.h> 27 #include <asm/mach/map.h> 28 29 #include <mach/common.h> 30 #include <mach/devices-common.h> 31 #include <mach/hardware.h> 32 #include <mach/iomux-v3.h> 33 #include <mach/irqs.h> 34 35 #include "crmregs-imx3.h" 36 37 void __iomem *mx3_ccm_base; 38 39 static void imx3_idle(void) 40 { 41 unsigned long reg = 0; 42 43 mx3_cpu_lp_set(MX3_WAIT); 44 45 __asm__ __volatile__( 46 /* disable I and D cache */ 47 "mrc p15, 0, %0, c1, c0, 0\n" 48 "bic %0, %0, #0x00001000\n" 49 "bic %0, %0, #0x00000004\n" 50 "mcr p15, 0, %0, c1, c0, 0\n" 51 /* invalidate I cache */ 52 "mov %0, #0\n" 53 "mcr p15, 0, %0, c7, c5, 0\n" 54 /* clear and invalidate D cache */ 55 "mov %0, #0\n" 56 "mcr p15, 0, %0, c7, c14, 0\n" 57 /* WFI */ 58 "mov %0, #0\n" 59 "mcr p15, 0, %0, c7, c0, 4\n" 60 "nop\n" "nop\n" "nop\n" "nop\n" 61 "nop\n" "nop\n" "nop\n" 62 /* enable I and D cache */ 63 "mrc p15, 0, %0, c1, c0, 0\n" 64 "orr %0, %0, #0x00001000\n" 65 "orr %0, %0, #0x00000004\n" 66 "mcr p15, 0, %0, c1, c0, 0\n" 67 : "=r" (reg)); 68 } 69 70 static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size, 71 unsigned int mtype, void *caller) 72 { 73 if (mtype == MT_DEVICE) { 74 /* 75 * Access all peripherals below 0x80000000 as nonshared device 76 * on mx3, but leave l2cc alone. Otherwise cache corruptions 77 * can occur. 78 */ 79 if (phys_addr < 0x80000000 && 80 !addr_in_module(phys_addr, MX3x_L2CC)) 81 mtype = MT_DEVICE_NONSHARED; 82 } 83 84 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 85 } 86 87 void __init imx3_init_l2x0(void) 88 { 89 #ifdef CONFIG_CACHE_L2X0 90 void __iomem *l2x0_base; 91 void __iomem *clkctl_base; 92 93 /* 94 * First of all, we must repair broken chip settings. There are some 95 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These 96 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. 97 * Workaraound is to setup the correct register setting prior enabling the 98 * L2 cache. This should not hurt already working CPUs, as they are using the 99 * same value. 100 */ 101 #define L2_MEM_VAL 0x10 102 103 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); 104 if (clkctl_base != NULL) { 105 writel(0x00000515, clkctl_base + L2_MEM_VAL); 106 iounmap(clkctl_base); 107 } else { 108 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); 109 } 110 111 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); 112 if (IS_ERR(l2x0_base)) { 113 printk(KERN_ERR "remapping L2 cache area failed with %ld\n", 114 PTR_ERR(l2x0_base)); 115 return; 116 } 117 118 l2x0_init(l2x0_base, 0x00030024, 0x00000000); 119 #endif 120 } 121 122 #ifdef CONFIG_SOC_IMX31 123 static struct map_desc mx31_io_desc[] __initdata = { 124 imx_map_entry(MX31, X_MEMC, MT_DEVICE), 125 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), 126 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), 127 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), 128 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), 129 }; 130 131 /* 132 * This function initializes the memory map. It is called during the 133 * system startup to create static physical to virtual memory mappings 134 * for the IO modules. 135 */ 136 void __init mx31_map_io(void) 137 { 138 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); 139 } 140 141 void __init imx31_init_early(void) 142 { 143 mxc_set_cpu_type(MXC_CPU_MX31); 144 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 145 arch_ioremap_caller = imx3_ioremap_caller; 146 arm_pm_idle = imx3_idle; 147 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); 148 } 149 150 void __init mx31_init_irq(void) 151 { 152 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 153 } 154 155 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { 156 .per_2_per_addr = 1677, 157 }; 158 159 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { 160 .ap_2_ap_addr = 423, 161 .ap_2_bp_addr = 829, 162 .bp_2_ap_addr = 1029, 163 }; 164 165 static struct sdma_platform_data imx31_sdma_pdata __initdata = { 166 .fw_name = "sdma-imx31-to2.bin", 167 .script_addrs = &imx31_to2_sdma_script, 168 }; 169 170 static const struct resource imx31_audmux_res[] __initconst = { 171 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), 172 }; 173 174 void __init imx31_soc_init(void) 175 { 176 int to_version = mx31_revision() >> 4; 177 178 imx3_init_l2x0(); 179 180 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); 181 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); 182 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); 183 184 pinctrl_provide_dummies(); 185 186 if (to_version == 1) { 187 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", 188 strlen(imx31_sdma_pdata.fw_name)); 189 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; 190 } 191 192 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 193 194 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); 195 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); 196 197 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, 198 ARRAY_SIZE(imx31_audmux_res)); 199 } 200 #endif /* ifdef CONFIG_SOC_IMX31 */ 201 202 #ifdef CONFIG_SOC_IMX35 203 static struct map_desc mx35_io_desc[] __initdata = { 204 imx_map_entry(MX35, X_MEMC, MT_DEVICE), 205 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), 206 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), 207 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), 208 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), 209 }; 210 211 void __init mx35_map_io(void) 212 { 213 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); 214 } 215 216 void __init imx35_init_early(void) 217 { 218 mxc_set_cpu_type(MXC_CPU_MX35); 219 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 220 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 221 arm_pm_idle = imx3_idle; 222 arch_ioremap_caller = imx3_ioremap_caller; 223 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); 224 } 225 226 void __init mx35_init_irq(void) 227 { 228 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); 229 } 230 231 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { 232 .ap_2_ap_addr = 642, 233 .uart_2_mcu_addr = 817, 234 .mcu_2_app_addr = 747, 235 .uartsh_2_mcu_addr = 1183, 236 .per_2_shp_addr = 1033, 237 .mcu_2_shp_addr = 961, 238 .ata_2_mcu_addr = 1333, 239 .mcu_2_ata_addr = 1252, 240 .app_2_mcu_addr = 683, 241 .shp_2_per_addr = 1111, 242 .shp_2_mcu_addr = 892, 243 }; 244 245 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { 246 .ap_2_ap_addr = 729, 247 .uart_2_mcu_addr = 904, 248 .per_2_app_addr = 1597, 249 .mcu_2_app_addr = 834, 250 .uartsh_2_mcu_addr = 1270, 251 .per_2_shp_addr = 1120, 252 .mcu_2_shp_addr = 1048, 253 .ata_2_mcu_addr = 1429, 254 .mcu_2_ata_addr = 1339, 255 .app_2_per_addr = 1531, 256 .app_2_mcu_addr = 770, 257 .shp_2_per_addr = 1198, 258 .shp_2_mcu_addr = 979, 259 }; 260 261 static struct sdma_platform_data imx35_sdma_pdata __initdata = { 262 .fw_name = "sdma-imx35-to2.bin", 263 .script_addrs = &imx35_to2_sdma_script, 264 }; 265 266 static const struct resource imx35_audmux_res[] __initconst = { 267 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), 268 }; 269 270 void __init imx35_soc_init(void) 271 { 272 int to_version = mx35_revision() >> 4; 273 274 imx3_init_l2x0(); 275 276 /* i.mx35 has the i.mx31 type gpio */ 277 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 278 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 279 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); 280 281 pinctrl_provide_dummies(); 282 if (to_version == 1) { 283 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", 284 strlen(imx35_sdma_pdata.fw_name)); 285 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; 286 } 287 288 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 289 290 /* Setup AIPS registers */ 291 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); 292 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); 293 294 /* i.mx35 has the i.mx31 type audmux */ 295 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, 296 ARRAY_SIZE(imx35_audmux_res)); 297 } 298 #endif /* ifdef CONFIG_SOC_IMX35 */ 299