150f2de61SShawn Guo /* 2df595746SAnson Huang * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved. 350f2de61SShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 450f2de61SShawn Guo * 550f2de61SShawn Guo * This program is free software; you can redistribute it and/or 650f2de61SShawn Guo * modify it under the terms of the GNU General Public License 750f2de61SShawn Guo * as published by the Free Software Foundation; either version 2 850f2de61SShawn Guo * of the License, or (at your option) any later version. 950f2de61SShawn Guo * This program is distributed in the hope that it will be useful, 1050f2de61SShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 1150f2de61SShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1250f2de61SShawn Guo * GNU General Public License for more details. 1350f2de61SShawn Guo * 1450f2de61SShawn Guo * You should have received a copy of the GNU General Public License 1550f2de61SShawn Guo * along with this program; if not, write to the Free Software 1650f2de61SShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 1750f2de61SShawn Guo * MA 02110-1301, USA. 1850f2de61SShawn Guo */ 1950f2de61SShawn Guo 2050f2de61SShawn Guo #ifndef __ASM_ARCH_MXC_HARDWARE_H__ 2150f2de61SShawn Guo #define __ASM_ARCH_MXC_HARDWARE_H__ 2250f2de61SShawn Guo 23df595746SAnson Huang #ifndef __ASSEMBLY__ 2424a83fe4SShawn Guo #include <asm/io.h> 259bbef187SShawn Guo #include <soc/imx/revision.h> 26df595746SAnson Huang #endif 2750f2de61SShawn Guo #include <asm/sizes.h> 2850f2de61SShawn Guo 2950f2de61SShawn Guo #define addr_in_module(addr, mod) \ 3050f2de61SShawn Guo ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) 3150f2de61SShawn Guo 3250f2de61SShawn Guo #define IMX_IO_P2V_MODULE(addr, module) \ 3350f2de61SShawn Guo (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ 3450f2de61SShawn Guo (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) 3550f2de61SShawn Guo 3650f2de61SShawn Guo /* 3750f2de61SShawn Guo * This is rather complicated for humans and ugly to verify, but for a machine 3850f2de61SShawn Guo * it's OK. Still more as it is usually only applied to constants. The upsides 3950f2de61SShawn Guo * on using this approach are: 4050f2de61SShawn Guo * 4150f2de61SShawn Guo * - same mapping on all i.MX machines 4250f2de61SShawn Guo * - works for assembler, too 4350f2de61SShawn Guo * - no need to nurture #defines for virtual addresses 4450f2de61SShawn Guo * 4550f2de61SShawn Guo * The downside it, it's hard to verify (but I have a script for that). 4650f2de61SShawn Guo * 4750f2de61SShawn Guo * Obviously this needs to be injective for each SoC. In general it maps the 4850f2de61SShawn Guo * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] 4950f2de61SShawn Guo * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). 5050f2de61SShawn Guo * 5150f2de61SShawn Guo * It applies the following mappings for the different SoCs: 5250f2de61SShawn Guo * 5350f2de61SShawn Guo * mx1: 5450f2de61SShawn Guo * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 5550f2de61SShawn Guo * mx21: 5650f2de61SShawn Guo * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 5750f2de61SShawn Guo * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000 5850f2de61SShawn Guo * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 5950f2de61SShawn Guo * mx25: 6050f2de61SShawn Guo * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 6150f2de61SShawn Guo * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 6250f2de61SShawn Guo * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 6350f2de61SShawn Guo * mx27: 6450f2de61SShawn Guo * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 6550f2de61SShawn Guo * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000 6650f2de61SShawn Guo * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 6750f2de61SShawn Guo * mx31: 6850f2de61SShawn Guo * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 6950f2de61SShawn Guo * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 7050f2de61SShawn Guo * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 7150f2de61SShawn Guo * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 7250f2de61SShawn Guo * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 7350f2de61SShawn Guo * mx35: 7450f2de61SShawn Guo * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 7550f2de61SShawn Guo * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 7650f2de61SShawn Guo * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 7750f2de61SShawn Guo * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 7850f2de61SShawn Guo * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 7950f2de61SShawn Guo * mx51: 8050f2de61SShawn Guo * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 8150f2de61SShawn Guo * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 8250f2de61SShawn Guo * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 8350f2de61SShawn Guo * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 8450f2de61SShawn Guo * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 8550f2de61SShawn Guo * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000 8650f2de61SShawn Guo * mx53: 8750f2de61SShawn Guo * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 8850f2de61SShawn Guo * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000 8950f2de61SShawn Guo * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 9050f2de61SShawn Guo * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 9150f2de61SShawn Guo * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 9250f2de61SShawn Guo * mx6q: 9350f2de61SShawn Guo * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000 9450f2de61SShawn Guo * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 9550f2de61SShawn Guo * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 9650f2de61SShawn Guo * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 9750f2de61SShawn Guo */ 9850f2de61SShawn Guo #define IMX_IO_P2V(x) ( \ 9950f2de61SShawn Guo (((x) & 0x80000000) >> 7) | \ 10050f2de61SShawn Guo (0xf4000000 + \ 10150f2de61SShawn Guo (((x) & 0x50000000) >> 6) + \ 10250f2de61SShawn Guo (((x) & 0x0b000000) >> 4) + \ 10350f2de61SShawn Guo (((x) & 0x000fffff)))) 10450f2de61SShawn Guo 10550f2de61SShawn Guo #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) 10650f2de61SShawn Guo 10750f2de61SShawn Guo #include "mxc.h" 10850f2de61SShawn Guo 10950f2de61SShawn Guo #include "mx3x.h" 11050f2de61SShawn Guo #include "mx31.h" 11150f2de61SShawn Guo #include "mx35.h" 11250f2de61SShawn Guo #include "mx2x.h" 11350f2de61SShawn Guo #include "mx21.h" 11450f2de61SShawn Guo #include "mx27.h" 11550f2de61SShawn Guo 11650f2de61SShawn Guo #define imx_map_entry(soc, name, _type) { \ 11750f2de61SShawn Guo .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 11850f2de61SShawn Guo .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ 11950f2de61SShawn Guo .length = soc ## _ ## name ## _SIZE, \ 12050f2de61SShawn Guo .type = _type, \ 12150f2de61SShawn Guo } 12250f2de61SShawn Guo 123*3481bdceSMartin Kaiser /* There's an off-by-one between the gpio bank number and the gpiochip */ 12450f2de61SShawn Guo /* range e.g. GPIO_1_5 is gpio 5 under linux */ 12550f2de61SShawn Guo #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) 12650f2de61SShawn Guo 12750f2de61SShawn Guo #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 128