1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/irqchip/arm-gic.h> 19 #include "common.h" 20 21 #define GPC_IMR1 0x008 22 #define GPC_PGC_CPU_PDN 0x2a0 23 24 #define IMR_NUM 4 25 26 static void __iomem *gpc_base; 27 static u32 gpc_wake_irqs[IMR_NUM]; 28 static u32 gpc_saved_imrs[IMR_NUM]; 29 30 void imx_gpc_pre_suspend(bool arm_power_off) 31 { 32 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 33 int i; 34 35 /* Tell GPC to power off ARM core when suspend */ 36 if (arm_power_off) 37 writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); 38 39 for (i = 0; i < IMR_NUM; i++) { 40 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 41 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); 42 } 43 } 44 45 void imx_gpc_post_resume(void) 46 { 47 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 48 int i; 49 50 /* Keep ARM core powered on for other low-power modes */ 51 writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN); 52 53 for (i = 0; i < IMR_NUM; i++) 54 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 55 } 56 57 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) 58 { 59 unsigned int idx = d->hwirq / 32 - 1; 60 u32 mask; 61 62 /* Sanity check for SPI irq */ 63 if (d->hwirq < 32) 64 return -EINVAL; 65 66 mask = 1 << d->hwirq % 32; 67 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : 68 gpc_wake_irqs[idx] & ~mask; 69 70 return 0; 71 } 72 73 void imx_gpc_mask_all(void) 74 { 75 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 76 int i; 77 78 for (i = 0; i < IMR_NUM; i++) { 79 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 80 writel_relaxed(~0, reg_imr1 + i * 4); 81 } 82 83 } 84 85 void imx_gpc_restore_all(void) 86 { 87 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 88 int i; 89 90 for (i = 0; i < IMR_NUM; i++) 91 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 92 } 93 94 void imx_gpc_hwirq_unmask(unsigned int hwirq) 95 { 96 void __iomem *reg; 97 u32 val; 98 99 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4; 100 val = readl_relaxed(reg); 101 val &= ~(1 << hwirq % 32); 102 writel_relaxed(val, reg); 103 } 104 105 void imx_gpc_hwirq_mask(unsigned int hwirq) 106 { 107 void __iomem *reg; 108 u32 val; 109 110 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4; 111 val = readl_relaxed(reg); 112 val |= 1 << (hwirq % 32); 113 writel_relaxed(val, reg); 114 } 115 116 static void imx_gpc_irq_unmask(struct irq_data *d) 117 { 118 /* Sanity check for SPI irq */ 119 if (d->hwirq < 32) 120 return; 121 122 imx_gpc_hwirq_unmask(d->hwirq); 123 } 124 125 static void imx_gpc_irq_mask(struct irq_data *d) 126 { 127 /* Sanity check for SPI irq */ 128 if (d->hwirq < 32) 129 return; 130 131 imx_gpc_hwirq_mask(d->hwirq); 132 } 133 134 void __init imx_gpc_init(void) 135 { 136 struct device_node *np; 137 int i; 138 139 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); 140 gpc_base = of_iomap(np, 0); 141 WARN_ON(!gpc_base); 142 143 /* Initially mask all interrupts */ 144 for (i = 0; i < IMR_NUM; i++) 145 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); 146 147 /* Register GPC as the secondary interrupt controller behind GIC */ 148 gic_arch_extn.irq_mask = imx_gpc_irq_mask; 149 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; 150 gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; 151 } 152