1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 21 #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 22 23 #define CKIH_CLK_FREQ 26000000 24 #define CKIH_CLK_FREQ_27MHZ 27000000 25 #define CKIL_CLK_FREQ 32768 26 27 extern void __iomem *mx3_ccm_base; 28 29 /* Register addresses */ 30 #define MXC_CCM_CCMR 0x00 31 #define MXC_CCM_PDR0 0x04 32 #define MXC_CCM_PDR1 0x08 33 #define MX35_CCM_PDR2 0x0C 34 #define MXC_CCM_RCSR 0x0C 35 #define MX35_CCM_PDR3 0x10 36 #define MXC_CCM_MPCTL 0x10 37 #define MX35_CCM_PDR4 0x14 38 #define MXC_CCM_UPCTL 0x14 39 #define MX35_CCM_RCSR 0x18 40 #define MXC_CCM_SRPCTL 0x18 41 #define MX35_CCM_MPCTL 0x1C 42 #define MXC_CCM_COSR 0x1C 43 #define MX35_CCM_PPCTL 0x20 44 #define MXC_CCM_CGR0 0x20 45 #define MX35_CCM_ACMR 0x24 46 #define MXC_CCM_CGR1 0x24 47 #define MX35_CCM_COSR 0x28 48 #define MXC_CCM_CGR2 0x28 49 #define MX35_CCM_CGR0 0x2C 50 #define MXC_CCM_WIMR 0x2C 51 #define MX35_CCM_CGR1 0x30 52 #define MXC_CCM_LDC 0x30 53 #define MX35_CCM_CGR2 0x34 54 #define MXC_CCM_DCVR0 0x34 55 #define MX35_CCM_CGR3 0x38 56 #define MXC_CCM_DCVR1 0x38 57 #define MXC_CCM_DCVR2 0x3C 58 #define MXC_CCM_DCVR3 0x40 59 #define MXC_CCM_LTR0 0x44 60 #define MXC_CCM_LTR1 0x48 61 #define MXC_CCM_LTR2 0x4C 62 #define MXC_CCM_LTR3 0x50 63 #define MXC_CCM_LTBR0 0x54 64 #define MXC_CCM_LTBR1 0x58 65 #define MXC_CCM_PMCR0 0x5C 66 #define MXC_CCM_PMCR1 0x60 67 #define MXC_CCM_PDR2 0x64 68 69 /* Register bit definitions */ 70 #define MXC_CCM_CCMR_WBEN (1 << 27) 71 #define MXC_CCM_CCMR_CSCS (1 << 25) 72 #define MXC_CCM_CCMR_PERCS (1 << 24) 73 #define MXC_CCM_CCMR_SSI1S_OFFSET 18 74 #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) 75 #define MXC_CCM_CCMR_SSI2S_OFFSET 21 76 #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) 77 #define MXC_CCM_CCMR_LPM_OFFSET 14 78 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 79 #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) 80 #define MXC_CCM_CCMR_FIRS_OFFSET 11 81 #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) 82 #define MXC_CCM_CCMR_UPE (1 << 9) 83 #define MXC_CCM_CCMR_SPE (1 << 8) 84 #define MXC_CCM_CCMR_MDS (1 << 7) 85 #define MXC_CCM_CCMR_SBYCS (1 << 4) 86 #define MXC_CCM_CCMR_MPE (1 << 3) 87 #define MXC_CCM_CCMR_PRCS_OFFSET 1 88 #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) 89 90 #define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 91 #define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) 92 #define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 93 #define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) 94 #define MXC_CCM_PDR0_PER_PODF_OFFSET 16 95 #define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) 96 #define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 97 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) 98 #define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 99 #define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) 100 #define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 101 #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) 102 #define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 103 #define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) 104 #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 105 #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 106 107 #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 108 #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 109 #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 110 #define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) 111 #define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 112 #define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) 113 #define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 114 #define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) 115 #define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 116 #define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) 117 #define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 118 #define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) 119 #define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 120 #define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) 121 #define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 122 #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F 123 124 /* Bit definitions for RCSR */ 125 #define MXC_CCM_RCSR_NF16B 0x80000000 126 127 /* 128 * LTR0 register offsets 129 */ 130 #define MXC_CCM_LTR0_DIV3CK_OFFSET 1 131 #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) 132 #define MXC_CCM_LTR0_DNTHR_OFFSET 16 133 #define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) 134 #define MXC_CCM_LTR0_UPTHR_OFFSET 22 135 #define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) 136 137 /* 138 * LTR1 register offsets 139 */ 140 #define MXC_CCM_LTR1_PNCTHR_OFFSET 0 141 #define MXC_CCM_LTR1_PNCTHR_MASK 0x3F 142 #define MXC_CCM_LTR1_UPCNT_OFFSET 6 143 #define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) 144 #define MXC_CCM_LTR1_DNCNT_OFFSET 14 145 #define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) 146 #define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 147 #define MXC_CCM_LTR1_LTBRSR_OFFSET 22 148 #define MXC_CCM_LTR1_LTBRSR 0x400000 149 #define MXC_CCM_LTR1_LTBRSH 0x800000 150 151 /* 152 * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 153 */ 154 #define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) 155 #define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ 156 MXC_CCM_LTR2_WSW_OFFSET((x))) 157 #define MXC_CCM_LTR2_EMAC_OFFSET 0 158 #define MXC_CCM_LTR2_EMAC_MASK 0x1FF 159 160 /* 161 * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 162 */ 163 #define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) 164 #define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ 165 MXC_CCM_LTR3_WSW_OFFSET((x))) 166 167 #define MXC_CCM_PMCR0_DFSUP1 0x80000000 168 #define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) 169 #define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) 170 #define MXC_CCM_PMCR0_DFSUP0 0x40000000 171 #define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) 172 #define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) 173 #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) 174 175 #define DVSUP_TURBO 0 176 #define DVSUP_HIGH 1 177 #define DVSUP_MEDIUM 2 178 #define DVSUP_LOW 3 179 #define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) 180 #define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) 181 #define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) 182 #define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) 183 #define MXC_CCM_PMCR0_DVSUP_OFFSET 28 184 #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) 185 #define MXC_CCM_PMCR0_UDSC 0x08000000 186 #define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) 187 #define MXC_CCM_PMCR0_UDSC_UP (1 << 27) 188 #define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) 189 190 #define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) 191 #define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) 192 #define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) 193 #define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) 194 #define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) 195 #define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) 196 #define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) 197 #define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) 198 #define MXC_CCM_PMCR0_VSCNT_OFFSET 24 199 #define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) 200 #define MXC_CCM_PMCR0_DVFEV 0x00800000 201 #define MXC_CCM_PMCR0_DVFIS 0x00400000 202 #define MXC_CCM_PMCR0_LBMI 0x00200000 203 #define MXC_CCM_PMCR0_LBFL 0x00100000 204 #define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) 205 #define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) 206 #define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) 207 #define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) 208 #define MXC_CCM_PMCR0_LBCF_OFFSET 18 209 #define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) 210 #define MXC_CCM_PMCR0_PTVIS 0x00020000 211 #define MXC_CCM_PMCR0_UPDTEN 0x00010000 212 #define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) 213 #define MXC_CCM_PMCR0_FSVAIM 0x00008000 214 #define MXC_CCM_PMCR0_FSVAI_OFFSET 13 215 #define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) 216 #define MXC_CCM_PMCR0_DPVCR 0x00001000 217 #define MXC_CCM_PMCR0_DPVV 0x00000800 218 #define MXC_CCM_PMCR0_WFIM 0x00000400 219 #define MXC_CCM_PMCR0_DRCE3 0x00000200 220 #define MXC_CCM_PMCR0_DRCE2 0x00000100 221 #define MXC_CCM_PMCR0_DRCE1 0x00000080 222 #define MXC_CCM_PMCR0_DRCE0 0x00000040 223 #define MXC_CCM_PMCR0_DCR 0x00000020 224 #define MXC_CCM_PMCR0_DVFEN 0x00000010 225 #define MXC_CCM_PMCR0_PTVAIM 0x00000008 226 #define MXC_CCM_PMCR0_PTVAI_OFFSET 1 227 #define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) 228 #define MXC_CCM_PMCR0_DPTEN 0x00000001 229 230 #define MXC_CCM_PMCR1_DVGP_OFFSET 0 231 #define MXC_CCM_PMCR1_DVGP_MASK (0xF) 232 233 #define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) 234 #define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) 235 236 #define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) 237 #define MXC_CCM_DCVR_ULV_OFFSET 22 238 #define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) 239 #define MXC_CCM_DCVR_LLV_OFFSET 12 240 #define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) 241 #define MXC_CCM_DCVR_ELV_OFFSET 2 242 243 #define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) 244 #define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 245 #define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F 246 #define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 247 248 #define MXC_CCM_COSR_CLKOSEL_MASK 0x0F 249 #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 250 #define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) 251 #define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 252 #define MXC_CCM_COSR_CLKOEN (1 << 9) 253 254 /* 255 * PMCR0 register offsets 256 */ 257 #define MXC_CCM_PMCR0_LBFL_OFFSET 20 258 #define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 259 #define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 260 261 #endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ 262